HX8368-A AN v01 090727read.pudn.com/downloads228/doc/comm/1074215/HX8368-A_AN_v… · HX8368-A PAD Assignment Figure 2.1 HX8368-A PAD Assignment. Himax Confidential -P.6- This information

HX8368-A (N) 320RGB x 240 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver Preliminary version 01July, 2009

( DOC No. HX8368-A-AN)

- P.1- Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. July, 2009

1. Introduction ....................................... ..................................................................................................4

2. HX8368-A PAD Assignment............................ ....................................................................................5

2.1 Bump Arrangement ......................................................................................................................6 2.2 Alignment mark ............................................................................................................................7

3. Pin Description.................................... ................................................................................................8

4. HX8368-A Reference FPC Circuit ..................... ...............................................................................12

4.1 TYPE-B Reference FPC Circuit .................................................................................................12 4.2 TYPE-C Reference FPC Circuit .................................................................................................12 4.3 MDDI Reference FPC Circuit .....................................................................................................13 4.4 MIPI Reference FPC Circuit .......................................................................................................13 4.5 External Components Connection .............................................................................................14

5. Initial Code For Reference ......................... ......................................................................................15

5.1 Initial Procedure .........................................................................................................................15 5.1.1 Display on (29h) .....................................................................................................................15 5.1.2 Display off (28h) .....................................................................................................................15 5.1.3 Sleep in(10h)..........................................................................................................................16 5.1.4 Sleep out (11h).......................................................................................................................16

5.2 The reference setting of normal display (for TYPE-B) ...............................................................17 5.3 The reference setting of normal display (for TYPE-C) ...............................................................17

6. OTP Programing..................................... ...........................................................................................18

6.1 OTP Table...................................................................................................................................18 6.2 OTP programming flow ..............................................................................................................22 6.3 Programming sequence .............................................................................................................23 6.4 OTP Programming Circuitry .......................................................................................................24

7. Revision History................................... .............................................................................................25

HX8368-A (N) 320RGB x 240 dot, 262K color, with internal GRAM, TFT Mobile Single Chip Driver List of Contents July, 2009


Figure 2.1 HX8368-A PAD Assignment........................................................................................5 Figure 4.1 HX8368-A TYPE-B Reference FPC Circuit ..............................................................12 Figure 4.2 HX8368-A TYPE-C Reference FPC Circuit ..............................................................12 Figure 4.3 HX8368-A MDDI Reference FPC Circuit ..................................................................13 Figure 4.4 HX8368-A MIPI Reference FPC Circuit ....................................................................13 Figure 6.1 OTP Programming Sequence...................................................................................22 Figure 6.2 OTP Programming Circuitry......................................................................................24



Table 4.1 External Components Connection..............................................................................14 Table 6.1 OTP Programming sequence .....................................................................................23



1. Introduction

This document describes HX8368-A is 320RGBx240 dots resolution driving controller. The

HX8368-A is designed to provide a single-chip solution that combines a gate driver, a

source driver, power supply circuit for 262,144 colors to drive a TFT panel with

320RGBx240 dots at maximum.

The HX8368-A can be operated in low-voltage (1.65V) condition for the interface and

integrated internal boosters that produce the liquid crystal voltage, breeder resistance and

the voltage follower circuit for liquid crystal driver. In addition, The HX8368-A also supports

various functions to reduce the power consumption of a LCD system via software control.

The HX8368-A supports several interface modes, including DBI TYPE-B, DBI TYPE-C

interface mode, DPI transfer interface mode, DSI interface mode and MDDI (Mobile

Display Digital Interface) interface mode. The interface mode is selected by the external

hardware pins BS3~0.

The HX8368-A is suitable for small portable battery-driven and long-term driving products,

such as small PDAs, digital cellular phones and bi-directional pagers.


- P.5-

APPLICATION NOTE V01DATA SHEET Preliminary V01

Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. July, 2009

HX8368-A (N) 320RGB x 240 dot, 262K color, TFT Mobile Single Chip Driver

2. HX8368-A PAD Assignment

Figure 2.1 HX8368-A PAD Assignment

-P.6- Himax Confidential This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Himax. February, 2009

HX8368-A (N) 320RGB x 240 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01

DATA SHEET Preliminary V012.1 Bump Arrangement

Input PAD

(No.1 ~ No.436)

Output PAD

(No.437 ~

No.1672)

110um

110um


HX8368-A (N) 320RGB x 240 dot, 262K color, TFT Mobile Single Chip Driver APPLICATION NOTE V01

DATA SHEET Preliminary V01 2.2 Alignment mark



APPLICATION NOTE V01

3. Pin Description

Input Parts

Signals I/O Pin Number

Connected with Description

BS3, BS2, BS1, BS0 I 4 VSSD/

IOVCC

System interface select.

BS3 BS2 BS1 BS0 Interface mode DB pins Display mode

0 1 0 0 DBI TYPE-B 8-bit DB17-DB8: Unused. DB7-DB0: Data Type 1

0 1 0 1 DBI TYPE-B 9-bit DB17-DB9:Unused, DB8-DB0: Data

Type 1

0 1 1 0 DBI TYPE-B 16-bit DB17-DB16: Unused, DB15-DB0: Data

Type 1

0 1 1 1 DBI TYPE-B 18bit DB17-DB0: Data Type 1

1 0 0 0 DSI (Command mode) DSI_CLKP, DSI_CLKN, DSI_D0P, DSI_D0N

Type 1

1 0 0 1 DBI type C (1) , MDDI I/F

MDDI_STBP, MDDI_STBN, MDDI_DATAP, MDDI_DATAN, SDI, SDO

--

1 1 0 0 DSI (Video mode) DSI_CLKP, DSI_CLKN, DSI_D0P, DSI_D0N Type 3

1 1 0 1 DPI/DBI TYPE-C Option 1 SDI, SDO, DB17-DB0 Type 3 1 1 1 0 DPI/DBI TYPE-C Option 2 SDI, SDO, DB17-DB0 Type 3 1 1 1 1 DPI/DBI TYPE-C Option 3 SDI, SDO, DB17-DB0 Type 3

Pixel format (RGB444/RGB565/RGB666) is selected by DCS command (0x3Ah) Display mode: Type 1: The display data will from GRAM. Type 3: The display data will from Interface input. Note1: Under BS(3-0)=1001, DBI type C(Option 1) jus t support to asscess CMD,

when MDDI into hibernation mode. And the RB9h(SETEXTC) command need to be set first, when user want to use MDDI I/F.

IFSEL I 1 MPU Interface format select pin

IFSEL Interface Format Selection 1 Command-Parameter interface mode

CSX (NCS/ NCS1) I 1/1 MPU

Chip select signal. Low: chip can be accessed. High: chip cannot be accessed. If not use, let it open or connected to IOVCC.

RESX (NRESET/ NRESET1)

I 1/1 MPU or reset circuit

Reset pin. Setting either pin low initializes the LSI. Must be reset after power is supplied. Must be connected to VSSD or IOVCC.

WRX_DCX (NWR_RNW) I 1 MPU

TYPE-B I/F mode: Serves as a write signal and write data at the low level. If not use, let it open or connected to IOVCC.

RDX_E (NRD_E) I 1 MPU

TYPE-B I/F mode: Serves as a read signal and read data at the low level. If not use, let it open or connected to IOVCC.

DCX_SCL (DNC_SCL/ DNC_SCL1)

I 1/1 MPU Data / Command Selection pin When under SPI interface, it servers as SCL (Serial Clock) If not use, let it open or connected to IOVCC.

BURN I 1 MPU

Free Running mode If BURN=Hi, this can enable free running mode for burn in test. The display data alternates between full black and full white independent of input data in free running mode. (weak pull low)

VS (VSYNC) I 1 MPU Frame synchronizing signal for DPI I/F mode.

If not used, please let it open connected to VSSD o r IOVCC. HS

(HSYNC) I 1 MPU Line synchronizing signal for DPI I/F mode.. If not used, please let it open connected to VSSD o r IOVCC.

PCLK I 1 MPU Pixel clock signal for DPI I/F mode.. If not used, please let it open connected to VSSD o r IOVCC.




Input Parts



DE I 1 MPU A data ENABLE signal for DPI I/F mode. If not used, please let it open connected to VSSD o r IOVCC.

OSC I 1 Oscillation Resistor

Oscillator input for test purpose. If not used, please let it open or connected to VSS D.

VCOMR I 2 Resistor or open

A VCOMH reference voltage. When adjusting VCOMH externally, set registers to halt the VCOMH internal adjusting circuit and place a variable resistor between VREG1 and VSSD. Otherwise, leave this pin open and adjust VCOMH by setting the internal register of the HX8368-A.

VGS I 1 VSSD or external resistor

Connect to a variable resistor to adjust internal gamma reference voltage for matching the characteristic of different panel used.

SDI I 1 MPU Serial data input pin in serial bus system interface. The data is inputted on the rising edge of the SCL signal. If not used, please open this pin.

Output Part



S1~S960 O 960 LCD Output voltages applied to the liquid crystal. G1~G240 O 240 LCD Gate driver output pins. These pins output VGH, VGL.

VCOM O 8 TFT

common electrode

The power supply of common voltage in TFT driving. The voltage amplitude between VCOMH and VCOML is output. Connect this pin to the common electrode in TFT panel.

TE/TE1 O 2/2 MPU Tearing effect output. If not used, please open this pin.

NISD O 2 Open

Image Sticking Discharge signal. This pin is used for monitoring image sticking discharge phenomena. When the NISD goes low, the VGL, Source and VCOM would be discharged to VSSA. When the NISD goes high, the VGL, Source and VCOM are normal operation.

PWM_OUT/ PWM_OUT1 O 2/2 LED driver

IC Backlight On/Off control pin. If use ABC function, the pin can connect to external LED driver IC. The output voltage rage = VSSD~ IOVCC.

SDO O 2 MPU Serial data output pin in serial bus system interface. The output data can lacth on the rising edge of the SCL signal. If not used, please open this pin.

NWR2 O 2 Sub Panel 80-interface NWR signal output pin for Sub Panel E2 O 2 Sub Panel 80-interface Enable signal output pin for Sub Panel

NCS2 O 2 Sub Panel The signal is Chip select for Sub Panel.

RS2 O 2 Sub Panel The signal is register index or register parameter select for Sub Panel.

Input/Output Part



C11A,C11B CX11A,CX11B I/O 10,10,

10,10 Step-up

Capacitor Connect to the step-up capacitors according to the step-up 1 factor. Leave this pin open if the internal step-up circuit is not used.

C12A, C12B I/O 8,8 Step-up Capacitor

Connect to the step-up capacitors for step up circuit 3 operation. Leave this pin open if the internal step-up circuit is not used.

C21A,C21B C22A,C22B I/O 12,12

12,12 Step-up

Capacitor

Connect these pins to the capacitors for the step-up circuit 2. According to the step-up rate. When not using the step-up circuit2, disconnect the m.

DB17~0 I/O 36 MPU

When Operates in MPU interface mode, it is used like an 18-bit bi-directional data bus. When Operation in RGB interface mode, it is an 18-bit RGB data bus. Let unused pins to open.




GPIO7~0 I/O 16 - Standard input / output Pin. As for GPIO7 ~ 0 to terminal, setting of an input a nd output direction is possible.

Hihg Speed Interface Parts



DSI_CLKP, DSI_CLKN I 3,3 High speed

Host High Speed Interface Clock differential signal input pins

DSI_D0P, DSI_D0N, I/O 3,3 High speed

Host High Speed Interface Data differential signal input pins.

DSI_VCC P 4 Power supply

Power supply for the High Speed Interface analog power.DSI_VCC = 1.65V ~ 3.3V. If not used, please let it connected to IOVCC.

DSI_LDO P 4 Power

supply or Capacitor

Power supply for the High Speed Interface analog power. DSI_LDO output = 1.2V ~ 1.3V.

DSI_VSS P 8 Ground High Speed Interface analog ground. DSI_VSS = 0V. When using the COG method, connect to VSSD on the FPC to prevent noise. If not used, please let it connected to VSSD.

DSI_LDO_EN I 1 VSSD/ IOVCC

If DSI_LDO_EN = high, the internal DSI_LDO regulator will be turned on. If DSI_LDO_EN = low, the internal DSI_LDO regulator will be turned off, DSI_LDO should connect to external power supply, the voltage range 1.2V~1.3V. Must be connected to IOVCC or VSSD.

VSEL/VSEL1 I 1/1 IOVCC VSEL = IOVCC, TE/PWM_OUT output range: 0V ~ 1.8V.

MDDI Interface Parts



MDDI_STBP, MDDI_STBN I 2,2 MDDI Host

MDDI Strobe differential signal input pins. STBP pin for Strobe+ and STBN pin for Strobe-. Connect to a terminal resistance (100Ω) between STBP and STBN. If not used, please let it connected to VSSD.

MDDI_DATAPMDDI_DATAN I/O 2,2 MDDI Host

MDDI Data differential signal input pins. DATAP pin for Data+ and DATAN pin for Data-. Connect to a terminal resistance (100Ω) between DATAP and DATAN. If not used, please let it connected to VSSD.

MDDI_VCC P 5 Power Supply

MDDI I/O power supply pin, 2.3V~3.3V. If not used, please let it connected to VCI.

MDDI_VSS P 10 Ground MDDI I/O ground pin. If not used, please let it connected to VSSD.

MDDI_LDO O 5 Capacitor

MDDI regulator output pin. Connect to a stabilizing capacitor between MDDI_VSS and MDDI_LDO If not used, please open these pins.

Power Part



IOVCC P 24 Power Supply

IO Pad and Digital power supply, 1.65V~3.3V Must set smaller than or equal to VCI and VCC.

VCC P 2 Power Supply Analog power supply, 2.3V~4.8V

VCI P 10 Power Supply Analog power supply, 2.3V~4.8V

VPP P 3 Power Supply

Power supply pin used in OTP program mode and operates at 7.5V±




Power Part



0.2V. If not in OTP program mode, please let it open.

VSSD P 33 Ground Digital ground VSSA P 16 Ground Analog ground

VDDD O 8 Stabilizing Capacitor

Output from internal logic voltage (1.6V). Connect to a stabilizing capacitor

REGVDD I 1 IOVCC REGVDD connect to high, the internal VDDD regulator will be turned on.

VREG1 (VREG1_OUT) P 2 Open Internal generated stable power for source driver unit.

VREG3 P 4 Stabilizing Capacitor A reference voltage for VGH&VGL.

VREF O 2 Open Internal reference voltage output pin, please open this pin.

VCOMH P 4 Open Connect this pin to the capacitor for stabilization. This pin indicates a high level of VCOM amplitude generated in driving the VCOM alternation.

VCOML P 7 Open When the VCOM alternation is driven, this pin indicates a low level of VCOM amplitude. Connect this pin to a capacitor for stabilization.

VCL P 6 Stabilizing capacitor A negative voltage for VCOML circuit, VCL=-VREG3.

DDVDH P 6 Stabilizing capacitor

An output from the step-up circuit1. Connect to a stabilizing capacitor between VSSA and DDVDH.

VGH P 6 Stabilizing capacitor

An output from the step-up circuit2 or 3DDVDH ~ 2DDVDH. The step-up rate is determined with BT3-0 bits. Connect to a stabilizing capacitor between VSSD and VGH.

VGL P 6 Stabilizing capacitor

An output from the step-up circuit2 or -VREG3 - 2DDVDH ~ VREG3 - 2DDVDH. The step-up rate is determined with BT3-0 bits. Connect to a stabilizing capacitor between VSSD and VGL.

Test Pin and Others



TEST3-1 I 3 Ground Test pin input (Internal pull low) TS7~0 O 8 Open A test pin. Disconnect it. VTEST O 1 Open A test pin. Disconnect it.

TVCOMHI O 1 Open A test pin. Disconnect it. DUMMY - 49 Open Dummy pads

DUMMYR1-2 - 2 Open Dummy pads. Available for measuring the COG contact resistance. DUMMYR1 and DUMMYR2 are short-circuited within the chip.

DUMMYR3-4 - 2 Open Dummy pads. Available for measuring the COG contact resistance. DUMMYR3 and DUMMYR4 are short-circuited within the chip.

-P.12-

Him

ax Confidential

This inform

ation contained herein is the exclusive property of Him

ax and shall not be distributed, reproduced, or disclosed in w

hole or in part without prior w

ritten permission of H

imax.

February, 2009

HX8368-A (N

) 320R

GB

x 240 dot, 262K color, T

FT

Mobile S

ingle Chip D

river

AP

PLIC

AT

ION

NO

TE

V01

4. HX

8368-A R

eference FP

C C

ircuit 4.1

TY

PE

-B R

eference FP

C C

ircuit

DB4DB5

DB2DB3

DB0DB1

DB15DB16DB17

DB12DB13DB14

DB10DB11

DB7DB8DB9

DNC_SCLCSX

DB6

NWR_RNWNRD_E

TY

PE-B 9-bit

0 1 0 10 1 0 0

0 1 1 1

BS3 / BS

2 / BS1 / BS

0

TY

PE-B 8-bit

TY

PE-B 18-bit

VCOM_L

Interface

0 1 1 0T

YP

E-B 16-bit

R6

0402/0R

VDD

R5

0402/0R/O

PE

NR

20402/0R

R8

0402/0R

R3

0402/0R/O

PE

N

DB4DB5

R7

0402/0R/O

PE

N

DB3

DB1DB2

R9

0402/0R/O

PE

N

DB0R

40402/0R

Interface

Se

lect

BS

3

VDDI

BS

2

VDDI

DNC_SCLCSX

BS

1B

S0

NWR_RNWNRD_E

DB17

DB15DB16

DB14

DB11DB12DB13

DB8DB9DB10

DB6DB7

GND

BS3

BS0

BS2

BS1

VDD

VDDI

C1

1u 10V X5R

C0402_055

VDDI

CX11A

C11A

VDD

C7

1u 10V X5R

C0402_055

VGL

C12B

C3

1u 25V X5R

C0603_055

VGH

C6

1u 10V X5R

C0402_055

CX11B

C4

1u 25V X5R

C0603_055

C12A

C8

1u 10V X5R

C0402_055

PWM_OUTTE

C21B

C21A

NRESET

C9

1u 10V X5R

C0402_055

NRESET

C10

1u 10V X5R

C0402_055

VPP

DDVDH

TE

VP

P

VCL

PW

M_O

UT C5

1u 10V X5R

C0402_055

VCOM_R

VDD

C2

1u 10V X5R

C0402_055

C22A

C22B

Golden Finger Up

C11B

VC

OM

_L

J1FP

C56-0.5-4.0L

VCI1

VCI2

GND3

VCC4

IOVCC5

nRESET6

DB177

DB168

DB159

DB1410

DB1311

DB1212

DB1113

DB1014

DB915

DB816

DB717

DB618

DB519

DB420

DB321

DB222

DB123

DB024

nRD_E25

NWR_RNW26

DNC_SCL27

nCS28

FLM29

GND30

NA31

VSYNC32

HSYNC33

DOTCLK34

ENABLE35

NA36

SDA37

NA38

NA39

DSI_VSS40

DSI_CLKP41

DSI_CLKN42

DSI_VSS43

DSI_D0P44

DSI_D0N45

GND46

NA47

MDDI_VSS48

MDDI_STBN49

MDDI_STBP50

MDDI_VSS51

MDDI_DATAN52

MDDI_DATAP53

GND54

BL+/NC55

BL_GND/NC56

R1

0402/100RV

CO

M_R

VDDI

VP

P1

TES

T PO

INT

1

PW

M_O

UT1

TES

T PO

INT

1

U1

HX8368-A

TYP

E-B

FP

C

VCOM3

VCOM4

VCOM5

VCOM6

VDDD8

VDDD9

VSSA10

VSSA11

VSSA12

VSSA13

VSSD14

VSSD15

VSSD16

IOVCC17

IOVCC18

IFSEL19

DSI_VSS36 DSI_VSS35 DE34 PCLK33 HSYNC32 VSYNC31 SDO30 SDI29 VSSD28 BS027 IOVCC26 BS125 VSSD24 BS223 IOVCC22 BS321 VSSD20

DB869

DSI_VCC54

DSI_VCC55

NRD_E56

NWR_RNW57

DNC_SCL58

DB1463

DB1364

DB1265

DB1166

DB1067

DB968

NCS59

DB1760

DB1661

DB1562

DB671

DB572

DB473

DB374

DB275

DB176

DB077

VSSD78

VPP80

NRESET81

IOVCC82

IOVCC83

VCI84

VCI85

VCI86

VCI87

TE88

PWM_OUT89

MDDI_VCC90

MDDI_VCC91

MDDI_LDO92

MDDI_LDO93

MDDI_VSS94

MDDI_VSS95

MDDI_VSS96

MDDI_STBN98

MDDI_VSS99

MDDI_STBP100

MDDI_STBP101

MDDI_VSS102

MDDI_DATAN103

MDDI_DATAN104

MDDI_VSS105

MDDI_DATAP106

MDDI_DATAP107

MDDI_VSS108

VSSD109

VSSA110

VCL112

VCL113

VGH115

VGH116

VGL118

VGL119

DDVDH121

DDVDH122

DDVDH123

CX11B124

CX11B125

CX11B126

CX11A127

CX11A128

C11B130

C11A135

VCC136

VCI137

VCI138

MDDI_STBN97

DUMMY2

C12B139

DUMMY1

C12B140

VSSD79

IOVCC49

DB770

C11B131

C11B132

C11A133

C11A134

C12A141

C12A142

C21B143

C21B144

C21A145

C21A146

C22B147

C22B148

C22A149

C22A150

VCOM151

VCOM152

VCOM153

VCOM154

DUMMY155

DUMMY156

CX11A129

VDDD7

DUMMY114

DUMMY117

DUMMY120

DSI_CLKP37

DSI_CLKP38

DSI_VSS39

DSI_VSS42 DSI_CLKN41 DSI_CLKN40

DSI_D0P43

DSI_D0P44

DSI_VSS45

DSI_D0N46

DSI_VSS48 DSI_D0N47

VSSD51 DSI_LDO_EN50

DSI_LDO52

DSI_LDO53

VGS111

F

igure 4.1 HX

8368-A T

YP

E-B

Reference F

PC

Circuit

4.2

TY

PE

-C R

eference FP

C C

ircuit

TEPWM_OUT

DDVDH

NRESET

NRESET

VCL

VPP

C5

1u 10V X5R

C0402_055

TE

VP

P

VCOM_R

PW

M_O

UT

VDD

C2

1u 10V X5R

C0402_055

C22B

C22A

C11B

VDD

Golden Finger Up

C11A

VC

OM

_L

C7

1u 10V X5R

C0402_055

VGL

VGH

C12B

C3

1u 25V X5R

C0603_055

J1FP

C56-0.5-4.0L

VCI1

VCI2

GND3

VCC4

IOVCC5

nRESET6

DB177

DB168

DB159

DB1410

DB1311

DB1212

DB1113

DB1014

DB915

DB816

DB717

DB618

DB519

DB420

DB321

DB222

DB123

DB024

nRD_E25

NWR_RNW26

DNC_SCL27

nCS28

FLM29

GND30

NA31

VSYNC32

HSYNC33

DOTCLK34

ENABLE35

NA36

SDA37

NA38

NA39

DSI_VSS40

DSI_CLKP41

DSI_CLKN42

DSI_VSS43

DSI_D0P44

DSI_D0N45

GND46

NA47

MDDI_VSS48

MDDI_STBN49

MDDI_STBP50

MDDI_VSS51

MDDI_DATAN52

MDDI_DATAP53

GND54

BL+/NC55

BL_GND/NC56

R2

0402/100RV

CO

M_R

VDDI

VP

P1

TES

T PO

INT

1

CX11A

SDI

C6

1u 10V X5R

C0402_055

PW

M_O

UT1

TES

T PO

INT

1

CX11B

C4

1u 25V X5R

C0603_055

C8

1u 10V X5R

C0402_055

C21B

C21A

C12A

C9

1u 10V X5R

C0402_055

C10

1u 10V X5R

C0402_055

R3

0402/0R

VDDI

DB4DB5

DB1DB2DB3

DB16DB17

DB0

DB14DB15

DB11DB12DB13

DB8DB9DB10

DB6DB7

DB4DB5

DB2DB3

DB17

DB0DB1

DB14DB15DB16

DB12DB13

DB9DB10DB11

DB6DB7DB8

U1

HX8368-A

TYP

E-C

FP

C

VCOM3

VCOM4

VCOM5

VCOM6

VDDD8

VDDD9

VSSA10

VSSA11

VSSA12

VSSA13

VSSD14

VSSD15

VSSD16

IOVCC17

IOVCC18

IFSEL19


DB869

DSI_VCC54

DSI_VCC55

NRD_E56

NWR_RNW57

DNC_SCL58

DB1463

DB1364

DB1265

DB1166

DB1067

DB968

NCS59

DB1760

DB1661

DB1562

DB671

DB572

DB473

DB374

DB275

DB176

DB077

VSSD78

VPP80

NRESET81

IOVCC82

IOVCC83

VCI84

VCI85

VCI86

VCI87

TE88

PWM_OUT89

MDDI_VCC90

MDDI_VCC91

MDDI_LDO92

MDDI_LDO93

MDDI_VSS94

MDDI_VSS95

MDDI_VSS96

MDDI_STBN98

MDDI_VSS99

MDDI_STBP100

MDDI_STBP101

MDDI_VSS102

MDDI_DATAN103

MDDI_DATAN104

MDDI_VSS105

MDDI_DATAP106

MDDI_DATAP107

MDDI_VSS108

VSSD109

VSSA110

VCL112

VCL113

VGH115

VGH116

VGL118

VGL119

DDVDH121

DDVDH122

DDVDH123

CX11B124

CX11B125

CX11B126

CX11A127

CX11A128

C11B130

C11A135

VCC136

VCI137

VCI138

MDDI_STBN97

DUMMY2

C12B139

DUMMY1

C12B140

VSSD79

IOVCC49

DB770

C11B131

C11B132

C11A133

C11A134

C12A141

C12A142

C21B143

C21B144

C21A145

C21A146

C22B147

C22B148

C22A149

C22A150

VCOM151

VCOM152

VCOM153

VCOM154

DUMMY155

DUMMY156

CX11A129

VDDD7

DUMMY114

DUMMY117

DUMMY120

DSI_CLKP37

DSI_CLKP38

DSI_VSS39


DSI_D0P43

DSI_D0P44

DSI_VSS45

DSI_D0N46

DSI_VSS48 DSI_D0N47

VSSD51 DSI_LDO_EN50

DSI_LDO52

DSI_LDO53

VGS111

NWR_RNWDNC_SCLCSX

SDO

NWR_RNWDNC_SCLCSX

BS3 / BS

2 / BS1 / BS

0

R1

0402/0R

SDI

Interface

SDO

R7

0402/0RR

60402/0R

/OP

EN

R10

0402/0R

R4

0402/0R/O

PE

N

R8

0402/0R/O

PE

NR

90402/0R

/OP

EN

Interface

Se

lect

R5

0402/0R

VDDI

BS

3B

S2

VDDI

BS

1B

S0

BS3

BS2

BS1

BS0

VDD

PCLKHSYNCVSYNC

VDDI

DE

TY

PE-C

Option1

1 1 0 1

VSYNC

1 1 1 0T

YP

E-C O

ption2T

YP

E-C O

ption3

VCOM_L

C1

1u 10V X5R

C0402_055

1 1 1 1

HSYNC

VDDI

PCLK

VDD

DE

F

igure 4.2 HX

8368-A T

YP

E-C

Reference F

PC

Circuit

-P.13-

Him

ax Confidential

This inform

ation contained herein is the exclusive property of Him

ax and shall not be distributed, reproduced, or disclosed in w

hole or in part without prior w

ritten permission of H

imax.

February, 2009

HX8368-A (N

) 320R

GB

x 240 dot, 262K color, T

FT

Mobile S

ingle Chip D

river

AP

PLIC

AT

ION

NO

TE

V01

4.3 M

DD

I Reference F

PC

Circuit

C11A

C8

1u 10V X5R

C0402_055

VGL

C12B

C4

1u 25V X5R

C0603_055

VGH

CX11A

C7

1u 10V X5R

C0402_055

CX11B

C5

1u 25V X5R

C0603_055

C12A

C9

1u 10V X5R

C0402_055

C21A

C21BC10

1u 10V X5R

C0402_055

C11

1u 10V X5R

C0402_055

DDVDH

VCL

C6

1u 10V X5R

C0402_055

VCOM_R

VDD

C3

1u 10V X5R

C0402_055

C22A

C22B

C11B

VDDI

VDDI

SDO

MDDI_VCC

MDDI_DATAN

DNC_SCLCSX

1 0 0 1M

DD

I+TY

PE-C

BS3 / BS

2 / BS1 / BS

0

R3

0402/0R

SDOSDI

Interface

VDDI

DNC_SCLCSX

MDDI_STBNMDDI_STBP

VDD

R1

0402/100R

VDDI

MDDI_VSS

R2

0402/100R

VCOM_L

C1

1u 10V X5R

C0402_055

VDDI

C2

1u 10V X5R

C0402_055

VDDTEPWM_OUT

MDDI_STBN

MDDI_LDO

MDDI_STBP

MDDI_VSS

NRESET

NRESET

VPP

TE

VP

P

PW

M_O

UT

MDDI_VCC

MDDI_DATAP

MDDI_DATAN

Golden Finger Up

MDDI_DATAP

J1FP

C56-0.5-4.0L

VCI1

VCI2

GND3

VCC4

IOVCC5

nRESET6

DB177

DB168

DB159

DB1410

DB1311

DB1212

DB1113

DB1014

DB915

DB816

DB717

DB618

DB519

DB420

DB321

DB222

DB123

DB024

nRD_E25

NWR_RNW26

DNC_SCL27

nCS28

FLM29

GND30

NA31

VSYNC32

HSYNC33

DOTCLK34

ENABLE35

NA36

SDA37

NA38

NA39

DSI_VSS40

DSI_CLKP41

DSI_CLKN42

DSI_VSS43

DSI_D0P44

DSI_D0N45

GND46

NA47

MDDI_VSS48

MDDI_STBN49

MDDI_STBP50

MDDI_VSS51

MDDI_DATAN52

MDDI_DATAP53

GND54

BL+/NC55

BL_GND/NC56

VC

OM

_LR

40402/100R

VC

OM

_R

VDDI

VP

P1

TES

T PO

INT

1

PW

M_O

UT1

TES

T PO

INT

1

SDI

MD

DI_S

TBN

U1

HX8368-A

MD

DI+TY

PE

-C F

PC

VCOM3

VCOM4

VCOM5

VCOM6

VDDD8

VDDD9

VSSA10

VSSA11

VSSA12

VSSA13

VSSD14

VSSD15

VSSD16

IOVCC17

IOVCC18

IFSEL19


DB869

DSI_VCC54

DSI_VCC55

NRD_E56

NWR_RNW57

DNC_SCL58

DB1463

DB1364

DB1265

DB1166

DB1067

DB968

NCS59

DB1760

DB1661

DB1562

DB671

DB572

DB473

DB374

DB275

DB176

DB077

VSSD78

VPP80

NRESET81

IOVCC82

IOVCC83

VCI84

VCI85

VCI86

VCI87

TE88

PWM_OUT89

MDDI_VCC90

MDDI_VCC91

MDDI_LDO92

MDDI_LDO93

MDDI_VSS94

MDDI_VSS95

MDDI_VSS96

MDDI_STBN98

MDDI_VSS99

MDDI_STBP100

MDDI_STBP101

MDDI_VSS102

MDDI_DATAN103

MDDI_DATAN104

MDDI_VSS105

MDDI_DATAP106

MDDI_DATAP107

MDDI_VSS108

VSSD109

VSSA110

VCL112

VCL113

VGH115

VGH116

VGL118

VGL119

DDVDH121

DDVDH122

DDVDH123

CX11B124

CX11B125

CX11B126

CX11A127

CX11A128

C11B130

C11A135

VCC136

VCI137

VCI138

MDDI_STBN97

DUMMY2

C12B139

DUMMY1

C12B140

VSSD79

IOVCC49

DB770

C11B131

C11B132

C11A133

C11A134

C12A141

C12A142

C21B143

C21B144

C21A145

C21A146

C22B147

C22B148

C22A149

C22A150

VCOM151

VCOM152

VCOM153

VCOM154

DUMMY155

DUMMY156

CX11A129

VDDD7

DUMMY114

DUMMY117

DUMMY120

DSI_CLKP37

DSI_CLKP38

DSI_VSS39


DSI_D0P43

DSI_D0P44

DSI_VSS45

DSI_D0N46

DSI_VSS48 DSI_D0N47

VSSD51 DSI_LDO_EN50

DSI_LDO52

DSI_LDO53

VGS111

MD

DI_D

ATA

PM

DD

I_DA

TAN

MD

DI_S

TBP

MDDI_VSS

F

igure 4.3 HX

8368-A M

DD

I Reference F

PC

Circuit

4.4

MIP

I Reference F

PC

Circuit

U

1H

X8368-A M

IPI F

PC

VCOM3

VCOM4

VCOM5

VCOM6

VDDD8

VDDD9

VSSA10

VSSA11

VSSA12

VSSA13

VSSD14

VSSD15

VSSD16

IOVCC17

IOVCC18

IFSEL19


DB869

DSI_VCC54

DSI_VCC55

NRD_E56

NWR_RNW57

DNC_SCL58

DB1463

DB1364

DB1265

DB1166

DB1067

DB968

NCS59

DB1760

DB1661

DB1562

DB671

DB572

DB473

DB374

DB275

DB176

DB077

VSSD78

VPP80

NRESET81

IOVCC82

IOVCC83

VCI84

VCI85

VCI86

VCI87

TE88

PWM_OUT89

MDDI_VCC90

MDDI_VCC91

MDDI_LDO92

MDDI_LDO93

MDDI_VSS94

MDDI_VSS95

MDDI_VSS96

MDDI_STBN98

MDDI_VSS99

MDDI_STBP100

MDDI_STBP101

MDDI_VSS102

MDDI_DATAN103

MDDI_DATAN104

MDDI_VSS105

MDDI_DATAP106

MDDI_DATAP107

MDDI_VSS108

VSSD109

VSSA110

VCL112

VCL113

VGH115

VGH116

VGL118

VGL119

DDVDH121

DDVDH122

DDVDH123

CX11B124

CX11B125

CX11B126

CX11A127

CX11A128

C11B130

C11A135

VCC136

VCI137

VCI138

MDDI_STBN97

DUMMY2

C12B139

DUMMY1

C12B140

VSSD79

IOVCC49

DB770

C11B131

C11B132

C11A133

C11A134

C12A141

C12A142

C21B143

C21B144

C21A145

C21A146

C22B147

C22B148

C22A149

C22A150

VCOM151

VCOM152

VCOM153

VCOM154

DUMMY155

DUMMY156

CX11A129

VDDD7

DUMMY114

DUMMY117

DUMMY120

DSI_CLKP37

DSI_CLKP38

DSI_VSS39


DSI_D0P43

DSI_D0P44

DSI_VSS45

DSI_D0N46

DSI_VSS48 DSI_D0N47

VSSD51 DSI_LDO_EN50

DSI_LDO52

DSI_LDO53

VGS111

C11A

C8

1u 10V X5R

C0402_055

VGL

C12B

C3

1u 25V X5R

C0603_055

VGH

CX11A

C7

1u 10V X5R

C0402_055

CX11B

C4

1u 25V X5R

C0603_055

C12AC

9

1u 10V X5R

C0402_055

C21A

C21BC10

1u 10V X5R

C0402_055

C11

1u 10V X5R

C0402_055

DDVDH

VCL

C5

1u 10V X5R

C0402_055

VCOM_R

VDD

C2

1u 10V X5R

C0402_055

C22A

C11B

C22B

1 0 0 0

BS3 / BS

2 / BS1 / BS

0

DS

I (Vide

o mode

)1 1 0 0

Interface

DS

I(Com

mand m

ode)

R3

0402/0R/O

PE

NR

20402/0R

Interface

Se

lect

VDDI

BS

2

VDDI

GND

BS2

DSI_LDO

VDD

VDDI

VCOM_L

C1

1u 10V X5R

C0402_055

VDDI

VDDTEPWM_OUT

NRESET

NRESET

VPP

TE

VP

P

PW

M_O

UT

VDD

Golden Finger Up

DSI_D0P

DSI_D0N

C6

1u 10V X5R

C0402_055

J1FP

C56-0.5-4.0L

VCI1

VCI2

GND3

VCC4

IOVCC5

nRESET6

DB177

DB168

DB159

DB1410

DB1311

DB1212

DB1113

DB1014

DB915

DB816

DB717

DB618

DB519

DB420

DB321

DB222

DB123

DB024

nRD_E25

NWR_RNW26

DNC_SCL27

nCS28

FLM29

GND30

NA31

VSYNC32

HSYNC33

DOTCLK34

ENABLE35

NA36

SDA37

NA38

NA39

DSI_VSS40

DSI_CLKP41

DSI_CLKN42

DSI_VSS43

DSI_D0P44

DSI_D0N45

GND46

NA47

MDDI_VSS48

MDDI_STBN49

MDDI_STBP50

MDDI_VSS51

MDDI_DATAN52

MDDI_DATAP53

GND54

BL+/NC55

BL_GND/NC56

VC

OM

_LR

10402/100R

VC

OM

_R

DSI_D0PDSI_D0N

DSI_CLKPDSI_CLKN

GND

VDDI

DSI_CLKN

DSI_CLKP

VP

P1

TES

T PO

INT

1

PW

M_O

UT1

TES

T PO

INT

1

DSI_VSSDSI_VSS

DSI_VSS

VDDI

VDDI

F

igure 4.4 HX

8368-A M

IPI R

eference FP

C C

ircuit

Note: T

he VG

S need connect to F

PC

than connect with

resistor to ground or VS

SD

/VS

SA

directly.




4.5 External Components Connection

Capacitor Recommended voltage Capacity

C1 (DDVDH-VSSA) 10V 1 µF (B characteristics) C2 (VGH-VSSA) 25V 1 µF (B characteristics) C3 (VGL-VSSA) 16V 1 µF (B characteristics) C4 (VCL-VSSA) 6V 1 µF (B characteristics) C5(VDDD-VSSA) 6V 1 µF (B characteristics) C11AB (C11A/B) 6V 1 µF (B characteristics) CX11AB (CX11A/B) 6V 1 µF (B characteristics) C12AB (C12A/B) 6V 1 µF (B characteristics) C21AB (C21A/B) 10V 1 µF (B characteristics) C22AB (C22A/B) 10V 1 µF (B characteristics) C6 (MDDI_LDO-MDDI_VSS) 6V 1 µF (B characteristics) C7 (DSI_LDO-DSI_VSS) 6V 1 µF (B characteristics)

Note: If not use DSI I/F or DSI_LDO_EN=0, the C7 can removed.

Table 4.1 External Components Connection




5. Initial Code For Reference 5.1 Initial Procedure 5.1.1 Display on (29h)

This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory

is enabled. This command makes no change of contents of frame memory. This command

does not change any other status.

5.1.2 Display off (28h)

This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame

Memory is disabled and blank page inserted. This command makes no change of contents of

frame memory. This command does not change any other status. There will be no abnormal

visible effect on the display.




5.1.3 Sleep in(10h)

This command causes the LCD module to enter the minimum power consumption mode. In

this mode the DC/DC converter is stopped, Internal oscillator is stopped, and panel scanning

is stopped.

It takes 120msec to get into Sleep In mode after SLPIN command issued.

5.1.4 Sleep out (11h)

This command turns off sleep mode .In this mode the DC/DC converter is enabled, internal

oscillator is started, and panel scanning is started.

It takes 120msec to become Sleep Out mode after SLPOUT command issued.

Legend

Command

Parameter

Display

Action

Mode

Sequential

transfer

SLPOUT

Charge Offset

voltage for LCDPanel

Sleep Out Mode

Start Internal

Oscillator

StartDC-DCConverter

Display whole blankscreen for 2 frames(Automatic No effect to

DISP ON/OFFCommands)

Display Memorycontents in accordance

with the currentcommand table settings




5.2 The reference setting of normal display (for TY PE-B) RESET(); DelayX1ms(10); Set_NOKIA_8B_CMD(0x11); DelayX1ms(5); Set_NOKIA_8B_CMD(0x29); DelayX1ms(120); Set_NOKIA_8B_CMD(0xB9); //Set PASSWORD to enable Himax command Set_NOKIA_8B_PA(0xFF); Set_NOKIA_8B_PA(0x83); Set_NOKIA_8B_PA(0x68); DelayX1ms(5); Set_NOKIA_8B_CMD(0x2C); //Write SRAM Send Date(); 5.3 The reference setting of normal display (for TY PE-C) RESET(); DelayX1ms(10); SPI_3W_SET_CMD(0x11); DelayX1ms(5); SPI_3W_SET_CMD(0x29); DelayX1ms(120); SPI_3W_SET_CMD(0xB9); // Set PASSWORD to enable Himax command SPI_3W_SET_PAs(0xFF); SPI_3W_SET_PAs(0x83); SPI_3W_SET_PAs(0x68); DelayX1ms(5); SPI_3W_SET_CMD (0x2C); //Write SRAM Send Date();




6. OTP Programing 6.1 OTP Table OTP_INDEX D7 D6 D5 D4 D3 D2 D1 D0

0x00h ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 0x01h ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 0x02h ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 0x03h VMF17 VMF16 VMF15 VMF14 VMF13 VMF12 VMF11 VMF10 0x04h VMF27 VMF26 VMF25 VMF24 VMF23 VMF22 VMF21 VMF20 0x05h VMF37 VMF36 VMF35 VMF34 VMF33 VMF32 VMF31 VMF30 0x06h VMH7 VMH6 VMH5 VMH4 VMH3 VMH2 VMH1 VMH0 0x07h VML7 VML6 VML5 VML4 VML3 VML2 VML1 VML0

0x08h Vaild_ID (not open) (not open) Valid_VML Valid_VMH Valid_VMF3

Valid_VMF2

Valid_VMF1

0x09h Valid_panel (not open) DDVDH_TRI

SM_Panel SS_Panel GS_Panel REV_Panel

BGR_Panel

0x0Ah Himax internal use (not open) 0x0Bh Himax internal use (not open) 0x0Ch Himax internal use (not open) 0x0Dh Himax internal use (not open) 0x0Eh Himax internal use (not open) 0x0Fh Himax internal use (not open) 0x10h Himax internal use (not open) 0x11h Himax internal use (not open) 0x12h Himax internal use (not open) 0x13h Himax internal use (not open) 0x14h Himax internal use (not open) 0x15h Himax internal use (not open) 0x16h Himax internal use (not open) 0x17h Himax internal use (not open) 0x18h ID47 ID46 ID45 ID44 ID43 ID42 ID41 ID40 0x19h Himax internal use (not open) 0x1Ah Himax internal use (not open) 0x1Bh Himax internal use (not open) 0x1Ch Himax internal use (not open) 0x1Dh Himax internal use (not open) 0x1Eh Himax internal use (not open) 0x1Fh Himax internal use (not open) 0x20h Himax internal use (not open) 0x21h Himax internal use (not open) 0x22h Himax internal use (not open)

0x23h Valid_gamma1

(no use) VRN0[5:0]

0x24h (no use) (no use) VRN1[5:0] 0x25h (no use) (no use) VRN2[5:0] 0x26h (no use) (no use) VRN3[5:0] 0x27h (no use) PRN0[6:0] 0x28h (no use) RPN1[6:0] 0x29h VRN4[5:3] PKN0[4:0] 0x2Ah VRN4[2:0] PKN1[4:0] 0x2Bh VRN5[5:3] PKN2[4:0] 0x2Ch VRN5[2:0] PKN3[4:0] 0x2Dh (no use) (no use) (no use) PKN4[4:0] 0x2Eh (no use) (no use) VRP0[5:0]




0x2Fh (no use) (no use) VRP1[5:0] 0x30h (no use) (no use) VRP2[5:0] 0x31h (no use) (no use) VRP3[5:0] 0x32h (no use) PRP0[6:0] 0x33h (no use) PRP1[6:0] 0x34h VRP4[5:3] PKP0[4:0] 0x35h VRP4[2:0] PKP1[4:0] 0x36h VRP5[5:3] PKP2[4:0] 0x37h VRP5[2:0] PKP3[4:0] 0x38h (no use) (no use) (no use) PKP4[4:0] 0x39h CGMP1[1:0] CGMP0[1:0] CGMN1[1:0] CGMN0[1:0]

0x3Ah Valid_gamma2

(no use) VRN0[5:0]

0x3Bh (no use) (no use) VRN1[5:0] 0x3Ch (no use) (no use) VRN2[5:0] 0x3Dh (no use) (no use) VRN3[5:0] 0x3Eh (no use) PRN0[6:0] 0x3Fh (no use) RPN1[6:0] 0x40h VRN4[5:3] PKN0[4:0] 0x41h VRN4[2:0] PKN1[4:0] 0x42h VRN5[5:3] PKN2[4:0] 0x43h VRN5[2:0] PKN3[4:0] 0x44h (no use) (no use) (no use) PKN4[4:0] 0x45h (no use) (no use) VRP0[5:0] 0x46h (no use) (no use) VRP1[5:0] 0x47h (no use) (no use) VRP2[5:0] 0x48h (no use) (no use) VRP3[5:0] 0x49h (no use) PRP0[6:0] 0x4Ah (no use) PRP1[6:0] 0x4Bh VRP4[5:3] PKP0[4:0] 0x4Ch VRP4[2:0] PKP1[4:0] 0x4Dh VRP5[5:3] PKP2[4:0] 0x4Eh VRP5[2:0] PKP3[4:0] 0x4Fh (no use) (no use) (no use) PKP4[4:0] 0x50h CGMP1[1:0] CGMP0[1:0] CGMN1[1:0] CGMN0[1:0]

0x51h Valid_gamma3

(no use) VRN0[5:0]

0x52h (no use) (no use) VRN1[5:0] 0x53h (no use) (no use) VRN2[5:0] 0x54h (no use) (no use) VRN3[5:0] 0x55h (no use) PRN0[6:0] 0x56h (no use) RPN1[6:0] 0x57h VRN4[5:3] PKN0[4:0] 0x58h VRN4[2:0] PKN1[4:0] 0x59h VRN5[5:3] PKN2[4:0] 0x5Ah VRN5[2:0] PKN3[4:0] 0x5Bh (no use) (no use) (no use) PKN4[4:0] 0x5Ch (no use) (no use) VRP0[5:0] 0x5Dh (no use) (no use) VRP1[5:0] 0x5Eh (no use) (no use) VRP2[5:0] 0x5Fh (no use) (no use) VRP3[5:0] 0x60h (no use) PRP0[6:0] 0x61h (no use) PRP1[6:0] 0x62h VRP4[5:3] PKP0[4:0]




0x63h VRP4[2:0] PKP1[4:0] 0x64h VRP5[5:3] PKP2[4:0] 0x65h VRP5[2:0] PKP3[4:0] 0x66h (no use) (no use) (no use) PKP4[4:0] 0x67h CGMP1[1:0] CGMP0[1:0] CGMN1[1:0] CGMN0[1:0]

0x68h Valid_gamma4

(no use) VRN0[5:0]

0x69h (no use) (no use) VRN1[5:0] 0x6Ah (no use) (no use) VRN2[5:0] 0x6Bh (no use) (no use) VRN3[5:0] 0x6Ch (no use) PRN0[6:0] 0x6Dh (no use) RPN1[6:0] 0x6Eh VRN4[5:3] PKN0[4:0] 0x6Fh VRN4[2:0] PKN1[4:0] 0x70h VRN5[5:3] PKN2[4:0] 0x71h VRN5[2:0] PKN3[4:0] 0x72h (no use) (no use) (no use) PKN4[4:0] 0x73h (no use) (no use) VRP0[5:0] 0x74h (no use) (no use) VRP1[5:0] 0x75h (no use) (no use) VRP2[5:0] 0x76h (no use) (no use) VRP3[5:0] 0x77h (no use) PRP0[6:0] 0x78h (no use) PRP1[6:0] 0x79h VRP4[5:3] PKP0[4:0] 0x7Ah VRP4[2:0] PKP1[4:0] 0x7Bh VRP5[5:3] PKP2[4:0] 0x7Ch VRP5[2:0] PKP3[4:0] 0x7Dh (no use) (no use) (no use) PKP4[4:0] 0x7Eh CGMP1[1:0] CGMP0[1:0] CGMN1[1:0] CGMN0[1:0] 0x7Fh Himax internal use (not open)

Note 1: The default value of OTP memory bits are all “1”. Note 2: VALID_xxx bit decide the OTP reload Enable/Disable, the default value is “1”. If Valid_xxx correlation OTP_Mask bit is “0” and set OTP_PROG to “1”, the VALID_xxx bit will be changed to “0”. The OTP will automatically reload in next HW reset, SW reset or Sleep Out command.

For example: Condition 1: Programmed all index of 0x00h ~ 0x02h and 0x18h and 0x08h’s bit 7.




Condition 2: Programmed all index of 0x00h ~ 0x02h and 0x18h but not programmed

0x08h’s bit 7.

Note 3: There are some conditions that HX8368-A can reload OTP. 1. Hardware reset 2. Software reset command (R01h) 3. Sleep out command (R11h)

Note 4: VMF can be programed 3 times.

The value of Valid_VMF3~1 Status of index 0x03h ~ 0x05h Valid_VMF3~1=”111” Not program any VMF1~3[7:0] Valid_VMF3~1=”110” Only program VMF1[7:0] and reload VMF1[7:0] Valid_VMF3~1=”101” Only program VMF2[7:0] and reload VMF2[7:0] Valid_VMF3~1=”100” Already program VMF1~2[7:0] and reload VMF2[7:0] Valid_VMF3~1=”011” Only program VMF3[7:0] and reload VMF3[7:0] Valid_VMF3~1=”010” Already program VMF1[7:0], VMF3[7:0] and reload VMF3[7:0] Valid_VMF3~1=”001” Already program VMF2~3[7:0] and reload VMF3[7:0] Valid_VMF3~1=”000” Already program VMF1~3[7:0] and reload VMF3[7:0]




6.2 OTP programming flow

VMF1[7:0], VMF2[7:0], VMF3[7:0]

No

OTP Program Flow

Yes

VMF1[7:0], VMF2[7:0], VMF3[7:0]

Yes

No

END

OTP_PROG=1

VMF1[7:0], VMF2[7:0], VMF3[7:0]

:

Yes

No

OTP_KEY[7:0](8'h00) Description Note

AAh

55h

Other value

Enter OTP Program mode

Leave OTP Program mode

Invalid 1. If OTP is in OTP program mode, then keep OTP program mode.

2. If OTP is in non-OTP program mode, then keep

non-OTP program mode.

OTP_KEY[7:0] can be ignored when user want to

do OTP program.

Figure 6.1 OTP Programming Sequence




6.3 Programming sequence

Step Operation 1 Power on and reset the module 2 Connect external power 7.5V to VPP pin 3 Wait 100ms for VPP stable

4

Write optimized value to related register Command Register Description ID1 (RC3h) ID1[7:0] LCD module/driver version ID2 (RC3h) ID2[7:0] LCD module/driver version ID3 (RC3h) ID3[7:0] LCD module/driver version

VCOM Control 1 (RB6h) VMF[7:0],

VCOM offset voltage for normal mode, Idle mode and Partial Idle mode (High level voltage of VCOM)

VCOM Control 2 (RB6h)

VMH[7:0] VCOMH voltage for normal mode, Idle mode and Partial Idle mode (High level voltage of VCOM)

VCOM Control 3 (RB6h)

VML[7:0] VCOML voltage for normal mode, Idle mode and Partial Idle mode (Low level voltage of VCOM)

Set Panel (RCCh) BGR_PANEL, SM_PANEL, SS_PANEL, GS_PANEL,

REV_PANEL, Set Panel characteristics

ID4 (RC3h) ID4[7:0] LCD module/driver version GAMMA(RE0h) Gamma value Set gamma parameter

5 Set OTP_KEY[7:0] (RE9h)=0xAAh to enter OTP program mode.

6

Specify OTP_index (note 1, 2 ) OTP_index

(Write – For Program) OTP_index

(Read – For get OTP value) Parameter

0x00h 0x00h ID1[7:0] 0x01h 0x01h ID2[7:0] 0x02h 0x02h ID3[7:0] 0x03h 0x03h VMF1[7:0], 0x04h 0x04h VMF2[7:0] 0x05h 0x05h VMF37:0] 0x06h 0x06h VMH[7:0] 0x07h 0x07h VML[7:0] 0x08h 0x08h Vaild_ID, Valid_VML, Valid_VMH,

Valid_VMF3, Valid_VMF2, Valid_VMF1 0x09h 0x09h Valid_panel, DDVDH_TRI, BGR_PANEL,

SM_PANEL, SS_PANEL, GS_PANEL, REV_PANEL

0x18h 0x18h ID4[7:0] 0x23h ~ 0x7Eh 0x23h ~ 0x7Eh Gamma value

7 Set OTP_Mask=0x00h, programming the entire bit of one parameter. 8 Set OTP_PROG=1, Internal register begin write to OTP according to OTP_index. 9 Wait 1 ms

10 Complete programming one parameter to OTP. If continue to programming other parameter, return to step (5). Otherwise, set OTP_KEY[7:0]=0x55h to leave OTP program mode and power off the module and remove the external power on PVSS pin.

Note 1: When do the OTP program on OTP index 0x08h and 0x09h, please mask the bit D6 (Himax internal use (not open)). If other bits are not used or want to keep the original value, please mask them, too.

Note 2: When program the DDVDH_TRI on OTP index 0x09h, please program the bits D[4:0] at the same time, because it will re-load by the Valid_panel bit.

Note 3: Set OTP_KEY[7:0] can be ignored when user want to do OTP program.

Table 6.1 OTP Programming sequence




6.4 OTP Programming Circuitry

Figure 6.2 OTP Programming Circuitry




7. Revision History

Version Date Description of Changes 2009/07/08 New setup 01

Documents

HX8368-A AN v01 090727read.pudn.com/downloads228/doc/comm/1074215/HX8368-A_AN_v… · HX8368-A PAD Assignment Figure 2.1 HX8368-A PAD Assignment. Himax Confidential -P.6- This information