How to realize many-input AND gates a 0 d c b X ab abc X 0 acd abc X 0 cd We need just one row to create all three-input ANDs

How to realize many-input AND gates

a

0

dcb

XX

ab abcX

0

acd abc X

0

cd

We need just one row to

create all three-input

ANDs

3-input AND gate realizable with one ancilla bit that can be reused by other AND gates

a

0

cb

XX

ab abcX

0

abc

XX abcX

An example

=

ab

cd

e

f

g abc

(g abc)de f

g

(g abc)de f deg = abcde f

(g abc) abc=g

Conclusions: 1. Every function of type abcde f is realizable with n+1 bits.

2. Every ESOP with n bits and one output is realizable in n+1 bits.

g

Warning fWarning for Maslovor Maslov=

ab

cd

e

fg

Each of these gates costs 3

Toffoli.

Toffoli gate for 5 inputs in

product requires in last slide 4 of these

gates.

So, Toffoli gate for 5 inputs in

product requires 3*4 =

12 gates.

Concluding. When Maslov tells cost 1 it

may be cost 12.

Main Problems in cascade design1. Portland Quantum Logic Group, since 2001. Concept of cascades.

Search from inputs, outputs, bidirectional. A* Search, GA. Many types of restricted gates. Exhaustive search. Multi-valued reversible logic.

2. Maslov, Dueck, Miller – University of New Brunswick, since 2002. Simple heuristic allowed to find good results for unlimited gate model. Because they use unlimited gate model, they do not worry about Markov’s theorem.

3. Shende, Markov, Hayes, University o0f Michigan, since 2002. Important theorem about odd and even functions. This theorem explains lack of success of our early approach for some functions.

4. Niraj Jha and Abhinav Agarwal. Princeton University, since 2004. Best results so far (for unlimited model?)

Previous research in cascades.1. (Perkowski, Mishchenko, Khlopotine, Kerntopf, 2001-2002) If I

improve the Hamming Distance (HD) with every gate selected then finally the HD becomes 0, function becomes an identity and I have a solution.

2. Goal – select the best gate – greedy algorithm.

• Drawback. In some situations there is no gate to select, all gates worsen the HD.

• We are in the local point in search space from which all selections worsen the HD

solution

We are here and we are stuck. Every gate selection

worsens HD

Previous research in cascades.

1. Example. abcd.

2. I need to flip only two bits but I cannot do this since I could do this only with products that have three literals.

Maslov, Dueck and Miller

• 1. Every function is realizable with DMM algorithm.• Drawback. They assume gates like abcde which require internal constants.

• It can be shown that the minimum of these constants is one. A simpler circuit uses more constants.

• Therefore their method of counting costs of gates is not fair.

• However, this assumption causes that algorithm is always convergent.

• Drawback. It is convergent with often very non-minimal costs and then they need another algorithm to improve the result by local optimizations.

Markov

If function is even, then it is realizable in n levels.If the function is odd (as abcd) then it requires one more ancilla bit. So n+1 bits are needed for EVERY function of n variables.

For n=3 every function is realizable with Toffoli, NOT and Feynman.

He considers only functions Toffoli with 3 inputs, Feynman and NOT. He does not use Toffoli with n inputs, as Maslov uses.

Main Markov Theorem

Conclusion

For n>4 we assume all Toffoli with 3 inputs but on all wires, NOT on all wires and all Feynman with 2 inputs on any two wires. This is the same as Markov (but we also assume other gates), different than Maslov.

Using Markov result, if the function is odd we need to add one more wire. (Maslov and Jha do not do this because they have unlimited gate model).

Our results take less literals and often also less gates

Conclusion

We are using all kinds of other gates, while their approaches still use only Toffoli, Feynman, NOT (just recently they add more).

Our method is potentially better if we solve the non-convergence problem for some functions.

Other method is to keep adding more ancilla bits.

Combine various search models

Kazuo Iwama†, Yahiko Kambayashi†

and Shigeru Yamashita‡

Quantum Computation and Information, ERATO, JST† Kyoto University, ‡NTT

Transformation Rules for Designing CNOT-based

Quantum Circuits

Quantum Computing (QC)

Computing paradigm based on quantum physics•Shor’s algorithm for prime factorization•Grover’s algorithm for database search

We need to design efficient “Quantum Circuit” for a Boolean function for the given problem

QC is still in experimental phase, but, the above algorithm’s time complexities are much better than “classical” counterparts

To perform quantum computing efficiently,

Quantum Circuit

qubit •Control NOT （ CNOT)If all the control bits are then target bit

x4x3x2x1

Control bit x2 x3

Target bit x4

quantum gates: operation to qubits

time

How a CNOT Gate works

Just add an exor term to the target bit

However, we cannot have a wire in QC

Conventional logic design cannot be utilized!!

NOT

x4x1x2

x4x3x2x1

x1x2 x2x3

x4x1x2x2x3

CNOT4

CNOT3Xx4x3x2x1Our

notation for

CNOT with

XOR in wire 4

Quantum Boolean Circuit (QBC)

xn

x2x1

Auxiliary bits

xn+20xn+30

xn

x2x1

xn+1 xn+1f (x1xn)

00

Can be used in a Quantum Algorithm

Why Local Transformation?

These are based on local transformation rules for Boolean formulas (AND/OR/NOT)

•Resolution Proof- prove a given CNF is 0 by transformations

•Automated Logic Design- optimize a given circuit by transformations

x1x2x3x1x’3x’1x’2x’3x’2x3x’1x2nil clause)

Motivation: Local Transformations for QBC?

Can we enjoy a similar concept (local transformation rules) for CNOT gates worlds?

In the quantum world, using AND/OR is not so good

CNOT gates (with many control bits)are better logical primitives

We start with “complete” local transformation rules for design methodology of CNOT based circuits

What we have done:

Quantum Boolean Circuits with CNOT Gates•Canonical Form•Local Transformation Rules•Transformation Procedure to Canonical Form

C1 S1 = S2 C2

If C1 and C2 are equivalent, we can transform C1 C2 systematically

Complete Local Transformation Rules for QBCs

Reduction to canonical form

C1 C2


S1 S2

noncanonical

canonical

Reduction to canonical form

C1 C2


S1

noncanonical

canonical

x1x2x3x4x5x6x7

x1x2x3x4x5x6x7

Transformations used for optimization and formal verification

•Transformation•Equivalence Check

Canonical Form

f(x) = x’1x’2 x’3 = 1x1x2x3 x1x2 x2x3 x1x3x1x2 x3

If we place CNOT gates lexicographically, we get the canonical form of the circuit

FACT

All Boolean Functions can be expressed byPPRM (Positive Polarity Reed-Muller) form uniquely

w f(x)w

x3x2x1

Canonical Form of QBC

xn

x2x1

Auxiliary bits

xn+20xn+30

xn

x2x1

xn+1 xn+1f (x1xn)

00

CNOTn+1 in PPRM form

Transformation to the Canonical Form

x4f(x)x4x3x2x1

x4f(x)x4x3x2x1

By swapping two adjacent gates, Move all CNOT4 to the left

Moving gates!

Transformation Procedure

will disappear

Only CNOTn+1 left Canonical Form

We gather CNOTs with the same target bit

CNOTn+1

xn

x2x1

xn+1f(x)

x2x1

Canonical Form

CNOTn

xn+20xn+30

xn+1xn

xn+20xn+30

x4x1x2x1x2 = x4

Transformation Rule 1

=

x4x3x2x1

Cancel repeated

terms

Move CNOT4 to the left

t1C2, t2C1condition

=

x4x3x2x1


Swap independent

terms ti = output of gate i

Ci = input of gate i

notation


t1C2, t2C1condition


=

x4x3x2x1

added

x3|x4>


t1C2, t2C1condition


=

x4x3x2x1

added

x4 x1 x2 x1 x3 x1(x1 x2 x3) = x1 x2 x1 x3


Case 1: t1C2, t2C1 Rule 2Case 2: t1C2, t2C1Rule 3 Case 3: t1C2, t2C1Rule 4 Case 4: t1C2, t2C1 Impossible

t1

t2

C2

C1

Transformation Rule 4 cont

Nontrivial case – case 4

We cannot swap by using just one local rule

We use auxiliary bits to swap gates in this case

x4x3x2x1

t1C2, t2C1


Auxiliary bit

0

y0y

y

Garbage, ancilla bitGarbage, ancilla bit

Example: How to Treat the Nontrivial Case

If we encounter case 4, x1

x4x3x2

x1

x3x2

x40

Rule 1 & Rule 2


x1

x3x2

x40

Rule 5

x1

x3x2

x40


We can delete these added

gates eventually

x1

x3x2

x40

Rule 2, 3, 4

x1

x3x2

x40

To the left To the right

What we discussed so far in this lecture?

•Quantum Boolean Circuit with CNOT gates•Canonical form•Transformation Rules for QBCs

•The notion of “minimum circuit” •How to get the minimum circuit

Future Work (it was a question asked in 2002)

Examples of applications of

transformations

Example　

Cost: 602 Cost: 188

Cost of CNOT gates

•Cost (1) = 1•Cost (2) = 14•Cost (3) = 56•Cost (4) = 140•Cost (m) = 112(m-3) (m > 4)

[BBC+95] shows constructions: •CNOT(2) gate by 14 basic gates•CNOT(3) gate by 4 CNOT(2) gate •CNOT(4) gate by 10 CNOT(2) gate•Cost (m) gate by 8(m-3) CNOT(2) gate (m > 4)

*should be much higher cost for many inputs

Motivation:Design

Methodology

Computer Design Methodology

Classical Quantum

For a given specification

Manually made libraries

Control Logic(Boolean functions)

Switch, Adder, MUX, …

Manually made libraries

Hadamard Transformation,Fourier Transformation, ..

Control Logic(Boolean functions)

Target for Automatic Design

Design Methodology for Boolean functions

Classical Quantum

For a given Boolean functions

Designing with AND/OR/NOT

Technology independent

Mapping to the library of available gates

Technology dependent

Mapping to the library of available gates

Designing with CNOT gates

Technology independent

Technology dependent

Design Methodology for Boolean functions

Classical Quantum

Standard Form (Sum-of-products forms)Transformation Rules

Good starting point for design

Why AND/OR/NOT ?

Good starting point for design

Why CNOT gates ?

Fundamental concept

We want to establish a similar concept

Motivation

Automatic Design

Why Only Boolean Function Parts?

The efficient construction of QBC is very important for the implementation of QA

Because only Boolean function parts vary depending on problems

•Boolean Oracles in Grover type algorithms

•Shor type algorithms

•Simulating classical calculations, etc.

*Boolean function part can be simulated by classical Boolean functions, but we cannot utilize (classical) design methodology

Shor type QA (find r s.t. gr = x mod p)

f (a1an, b1bn, )gA x--B mod p

Vary depending on problem

W-H

0

0

0

0W-H

0

0

QFTA

B

an

a1

bn

b1

More rules

Auxiliary bit

0


Transformation Example Shift(S, 2) is called.

Shift(S, 1) is called.

Step 1

x1x2

Change the n-th control bit of ci to an unused auxiliary bit by adding two gates ai and bi

=

c1 c2 c3x1x2

00

a1 b1

0a2 b2 a3 b3

We want to prove this simple fact

About Step 1

x1x2

x1x2

000

Rule 1

x1x2

000

Rule 2

Rule 5 to get the previous slide

Step 2

Move ai to the left (Rules 2 & 4)

x1x2

000

c1 c2

a1 b1a2 b2

x1x2

000

a2

a1

c3

a3 b3

a3

c1 c2

b1b2

c3

b3

added

Step 3

Move bi to the right (Rules 2 & 3)

x1x2

000

c1 c2 c3

b3

x1x2

000

a2

a1

a3

c1 c2

b1b2

c3

b3

b2

b1

added

Step 4

for (i = 2 to k) { Move ai to the right after a1 (Rule 2)

Change the control of ai to the ancilla bit 1 (Rule 5)}

x1x2

000

a2a1 a3

x2

000

a1

a’2a’3

x1

Step 5

for (each gi = CNOTn) { Move gi to the right after a1 (Rules 2, 3, 4)}

x2

000

a1

x1

g1 g2 g3 g4

x2

000

a1

x1

g1 g2 g3 g4

*Here, we omit some redundant pairs of gates

added

Step 6 (1/2)

Step 6 (a): Reorder CNOTn lexicographically (Rule 2) Step 6 (b): Delete redundant gates by Rule 6Step 6 (c): Delete redundant pairs of gates by Rule 1

x2

000

a1

x1

CNOTn

x2

000

a1

x1

CNOTn

Step 6 (b)Step 6 (c)

Step 6 (2/2)

Step 6 (a): Reorder CNOTn lexicographically (Rule 2) Step 6 (b): Delete redundant gates by Rule 6Step 6 (c): Delete redundant pairs of gates by Rule 1

x2

000

a1

Why disappear?

x1x2

000

a1

x1

About Step 6 (c)

disappear by Rule 6

Move the first gate to the right → We can move all CNOT2 to the left successfully

∵ if some gates remain in g1(x), the final state of x2 is x2 x2g1(x) g2(x) this cannot be x2 f(x)

x2g1(x)g2(x)x1x2

000

a1

Step 7

Move a1 to the right after all CNOTn (Rule 2)

x2

000

a1

x1

x2

000

a1x1

CNOTn

Then Shift(S, 1) is called

x2

000

x1

x2

0

x1

0000

Step 1

a2a1 b2b1

Shift(S, 1): Step 2

x2

0

x1

0000

x2

0

x1

0000

Step 2a2

a1 b2b1

b2b1a1 a2

Shift(S, 1): Step 3

Step 3

x2

0

x1

0000

b2b1a1 a2

x2

0

x1

0000

b2b1a1 a2

added

Shift(S, 1): Steps 4 & 5

Step 5

x2

0

x1

0000

a1 a’2

x2

0

x1

0000

a1 a’2added

Shift(S, 1): Steps 6 & 7

Step 6 & 7

x2

0

x1

0000 a1

x2

0

x1

0000 a1

After All Shift(S, i): Step A 1/2x1x2

00000

while (each gi such that gi has ancilla bits and the most left) {Move gi to the left (Rule 2, 4)Delete gi (Rule 6)

}

After All Shift(S, i): Step A 2/2

while (each gi such that gi has ancilla bits and the most left) {Move gi to the left (Rule 2, 4)Delete gi (Rule 6)

}

*Here, we omit some redundant pair of gates

x1x2

00000

After All Shift(S, i): Step B

x1x2

00000

Reorder gates (except for CNOTn) lexicographically (Rule 2)Delete redundant pairs of gates by Rule 1

x1x2

00000

• This was a very complex proof of a fact that could be easily proven from swap gate properties.

• Our goal was however to show the application of all the introduced transformation techniques.

Complex Rules &

Minimizing Example

Complex Transformation

C C1

A

CC1

A

xi

xj

A

CC1

xi

xj

C1

We want to prove this by transformations

A

C

xi

xj

A

C

xi

xj

C1C1

A

Complex Transformation (1)

C1

A

By TR (1)


Move them by TRs (2) & (3)

A

C

xi

xj

C1C1

A A

CC1

xi

xj

C1C1

A

added

cancel


A

CC1

A

xi

xj

A

CC1

xi

xj

C1

Thus we proved what we wanted to prove

C C

i

A

CC1

A

C2

A

Ck

A A

C

Ck C1

k |A| > Σ|Ck|

Our Strategy of using such transformation in more complex circuits

Find the portion where the following transformation can be applied

Ck C1

x1

x2

x3

x4

x5

x6

x7

a b c d e f g

Best Combination: (a, d ), (b, e), (c, f )

x1x2x3x4x5x6x7

g

(a, d ) (b, e) (c, f )

h i j k l a b c

Applying the transformation we get:

Now we can remove two pairs of columns

x1x2x3x4x5x6x7

ga b c l

To get solution with 6 gates

x1x2x3x4x5x6x7

ga b c m n l

By TR (1)

We insert a pair of columns

x1x2x3x4x5x6x7

ga b c m n l

Best Combination: (a, m ), (b, g), (c, n)

x1x2x3x4x5x6x7

a b c l

Best Combination: (a, m ), (b, g), (c, n)

(a, m ) (b, g ) (c, n )

Again we remove two pairs of columns

x1x2x3x4x5x6x7

a b co p q l

Best Combination: (o, p), (b, c), (q, l)

x1x2x3x4x5x6x7

(o, p)

a bp

(b, c) (q, l )

q

Final result

Other Stuff

auxiliary bits

x50x60

x2x1

x4x3

x2x1

x3

x50x60

G1

p

G2 G’2 G’1

x4F

g1 g2

Simulating CNF Formulas

F = (x1 x3) ( x1x2 x3)

x4x3x2x1

x4x1x3

x4x3x2x1

x4x1x3

Feynman’s Notation

2 U

U

Toffoli Gate

x =0

1

1

0

Basic Gates in Quantum Circuits

[BBC+95]All unitary matrices can be decomposed into a combination of the above gates

U

Controlled NOT

Basic Gates

1-bit unitary

Controlled U Gate

U =u00

u10

u01

u11

m (U)=

u00

u10

u01

u11

11

1

If all of x1 xm areapplyU to the |y

2m

dimension

Classical Reversible Gate (1)

C=1 → Swap I1 and I2 C=0 → no change

FT Gate

C CI1

I2

O1

O2

Universal

Classical Reversible Gate (2)

C1 = C2 → negate I

Toffoli Gate

I O

C2 C2

C1 C1

Universal

x4x3x2x1

Transformations from [BBC+95]

Barenco et all, very important paper.

An example

=

ab

cd

e

f

g abc

(g abc)de f

g

(g abc)de f deg = abcde f

(g abc) abc=g

g

Recall this example.

Lemma 6.1

Any 2x2 unitary matrix can be decomposed:

2 U

U=

V V† V

U=V2

Lemma 7.5

U=V2

x1

=

x2x3x4x5x6x7x8x9 U

Any 2x2 unitary matrix can be decomposed:

VV†V

Corollary 7.6 - Proof

Lenma 7.5

=

U

Any n*n unitary matrix can be decomposed:

VV†V

(n) (1)Cn-1 Cn-2

(Cor. 7.4)(Cor. 5.3)Cn-1 = Cn-1 + (n)

auxiliary bits

xa j

xa i

00

Gi

gi

x1

xk

Gjgj

(a)

xa xa

xa

xa xa

xa

x1

xk

0

j

i 0

Gi

(b)

0i1

0ik

0j1

0jk

g’i

Gj

g’j

l1

l2

r1

r2

x1

xk

xa 0xa

j

i 0

Gi

(c)

0xa i1

0xa ik

0xa j1

0xa jk

g’i

Gj

g’j

l1

l2

l3

r1

r2

r3

auxiliary bits

xa

j

xa

i

0

0

Gi

gi

x1

xk

Gj

gj

(a)

xa

xa

xa

xa

xa

xa

x1

xk

0

j

i

0

Gi

(b)

0

i1

0

ik

0

j1

0

jk

g’i

l1

l2

r1

r2

Documents

How to realize many-input AND gates a 0 d c b X ab abc X 0 acd abc X 0 cd We need just one row to create all three-input ANDs