hkcl.co.inhkcl.co.in/.../2019/01/MTEC_ECE-VLSI-Design_2018.docx · Web viewThe Dissertation (Phase-I) involving literature survey and problem formulation along with data collection

SCHEME

&

SYLLABUS

M.Tech. in Electronics & Communication Engineering

(VLSI Design)

Effective from 2018-19

Department of Electronics & Communication EngineeringDeenbandhu Chhotu Ram University of Science & TechnologyMurthal (Sonipat), Haryana, 131039

Mission

To facilitate and promote studies and research in emerging areas of Electronics and Communication Engineering with focus on new frontiers of upcoming technologies evolution of enlightened technocrats, innovators and entrepreneurs who will contribute to national growth in particular and to the international community as a whole.

Vision

To achieve excellence in education and research in main & related areas of Electronics and communication technologies, Sustainable growth of the students not only locally but globally and to occupy a place of pride amongst the most eminent organizations of the world.

1. Core Competence:

1. Post Graduating engineers should understand the basic concepts of Electronics and Communication engineering fundamentals required to solve engineering problems and also to pursue higher studies & Research.

1. Preparations:

1. To prepare students for various competitive exams like NET, GRE, the entrance exam for research organisations like DRDO, ISRO etc, for the purpose of higher studies and research and getting better placements in PSU, MNC’s along with research organisations.

1. Application and Synthesis:

1. To give more emphasis on application and synthesis in courses related to Design of Electronic Circuits and their Simulation along with optimization. It helps in developing practical skills to design experimentation and develop confidence for tackling a problem and initiating its solution.

1. To train students with good scientific and engineering knowledge, so as to comprehend, analyse, design, and create novel products and solutions for the real life problems/systems.

1. Professionalism:

1. To inculcate in students professional and ethical attitude, effective communication skills teamwork skills, multidisciplinary approach, social engineering, and an ability to relate engineering issues to broader social context.

1. Learning Environment:

Programme Educational Objectives:

1. To provide students with and academic environment aware of excellence, leadership, written ethical codes and guidelines, and the lifelong learning needed for a successful career.

Following are the programme outcomes:

0. an ability to apply knowledge of mathematics, science, and engineering,

0. an ability to design and conduct experiments, as well as to analyze and interpret data,

0. an ability to design a system, component, or process to meet desired needs within realistic constraints such as economic, environmental, social, political, ethical, health and safety, manufacturability, and sustainability,

0. an ability to function on multidisciplinary teams,

0. an ability to identify, formulate, and solve engineering problems,

0. an understanding of professional and ethical responsibility,

0. an ability to communicate effectively,

0. the broad education necessary to understand the impact of engineering solutions in a global, economic, environmental, and societal context. To indulge in Research and development activities that will be helpful to further technological development.

0. a recognition of the need for, and an ability to engage in life-long learning,

0. a knowledge of contemporary issues.

0. an ability to use the techniques, skills, and modern engineering tools necessary for engineering practice.

Programme Outcomes:

DEENBANDHU CHHOTU RAM UNIVERSITY OF SCIENCE & TECHNOLOGY, MURTHAL (SONEPAT)

SCHEME OF STUDIES & EXAMINATIONS

MASTER OF TECHNOLOGY IN ELECTRONICS & COMMUNICATION ENGINEERING (VLSI DESIGN)

(Choice Based Credit System w.e.f 2018-19)

SEMESTER I

SN

Course No.

Course Title

Teaching Schedule

Marks of Class Work

Examination Marks

Total Marks

Credit

Duration of Exam.

L

P

Theory

Practical

1

MTVLSI501C

Core 1

RTL Simulation and Synthesis with PLDs

3

-

25

75

-

100

3

3

2

MTVLSI503C

Core 2

Analog and Digital CMOS VLSI Design

3

-

25

75

-

100

3

3

3

PE I

ELECTIVE I

3

-

25

75

-

100

3

3

4

PE II

Elective II

3

-

25

75

-

100

3

3

5

MTVLSI551C

Lab 1

RTL Simulation and Synthesis with PLDs Lab

-

4

25

-

75

100

2

3

6

MTVLSI553C

Lab 2

Analog and Digital CMOS VLSI Design Lab

-

4

25

-

75

100

2

3

7

MTEC557C

Research Methodology and IPR

2

-

25

75

-

100

2

3

8

Aud 1

Audit course 1

2

-

25

75

-

100

0

3

Total

16

08

200

450

150

800

18

-

List of Program Specific Elective I

List of Program Specific Elective II

Audit course 1& 2

MTVLSI511C

Digital Signal and Image Processing

MTVLSI521C

Parallel Processing

AUD531C

English for Research Paper Writing

MTVLSI513C

Programming Languages for Embedded Software

MTVLSI523C

System Design with Embedded Linux

AUD533C

Disaster Management

AUD535C

Sanskrit for Technical

Knowledge

AUD537C

Value Education

MTVLSI515C

VLSI Signal Processing

MTVLSI525C

CAD of Digital System

AUD539C

Constitution of India

AUD541C

Pedagogical Studies

MTVLSI517C

IC Fabrication Technology

MTVLSI527C

Introduction to MEMS

AUD543C

Stress Management by Yoga

MTVLSI519C

Semiconductor device modeling

MTVLSI529C

Advanced Computer Architecture

AUD545C

Personality Development through Life Enlightenment Skills.

Note: 1. Student can opt any two subjects for electives I & II from given list respectively and one audit course from given list of audit course 1&2.

2.The choice of students for any elective shall not be binding on the department to offer, if the department does not have expertise. The minimum strength of the students opting for the particular subject shall not be less than 8.

3. The students will be allowed to use non-Programmable Scientific Calculator. However, sharing/exchange of calculator is prohibited in the examination.




(Choice based Credit System w.e.f. 2018-19)

SEMESTER II

S. No.

Course No.

Course Title

Teaching Schedule

Marks of Class Work

Examination Marks

Total Marks

Credit

Duration of Exam.

L

P

Theory

Practical

1

MTVLSI502C

Core 3

Microcontrollers and Programmable Digital Signal Processors

3

-

25

75

-

100

3

3

2

MTVLSI504C

Core 4

VLSI Design Verification and Testing

3

-

25

75

-

100

3

3

3

PE III

ELECTIVE III

3

-

25

75

-

100

3

3

4

PE IV

Elective IV

3

-

25

75

-

100

3

3

5

MTVLSI552C

Lab 1

Microcontrollers and Programmable Digital Signal Processors Lab

-

4

25

-

75

100

2

3

6

MTVLSI554C

Lab 2

VLSI Design Verification and Testing Lab

-

4

25

-

75

100

2

3

7

MTVLSI556C

Mini Project

4

25

75

100

2

8

Aud 2

Audit course 2

2

-

25

75

-

100

0

3

Total

14

8

200

375

225

800

18

-

List of Program Specific Elective I

List of Program Specific Elective II

Audit course 1 & 2

MTVLSI510C

Memory Technologies

MTVLSI520 C

Communication Buses and Interfaces

AUD531C

English for Research Paper Writing

AUD533C

Disaster Management

MTVLSI512C

SoC Design

MTVLSI522 C

Network Security and Cryptography

AUD535C

Sanskrit for Technical

Knowledge

MTVLSI514C

Low Power VLSI Design

MTVLSI524 C

Physical design automation

AUD537C

Value Education

AUD539C

Constitution of India

AUD541C

Pedagogical Studies

MTVLSI516C

Computational Intelligent Techniques for VLSI Design

MTVLSI526 C

Hardware Software Co-Design

AUD543C

Stress Management by Yoga

AUD545C

Personality Development through Life Enlightenment Skills.

MTVLSI518C

VLSI for Optical Interconnect

MTVLSI528 C

Optimization for VLSI Design

Note:

1. Student can opt any two subjects for electives III & IV from given list respectively and one audit course from given list of audit course 1&2.

1. The choice of students for any elective shall not be binding on the department to offer, if the department does not have expertise. The minimum strength of the students opting for the particular subject shall not be less than 8.






SEMESTER III

S. No.

Course No.

Course Title

Teaching Schedule

Marks of Class Work

Examination Marks

Total Marks

Credit

Duration of Exam.

L

P

Theory

Practical

1

PE V

ELECTIVE V

3

-

25

75

-

100

3

3

2

OE

OPEN ELECTIVE

3

-

25

75

-

100

3

3

3

MTVLSI651C

Dissertation

(1st phase)

-

20

50

-

100

150

10

3

Total

6

20

100

150

100

350

16

-

List of Program Specific Elective V (PE V)

List of Open Elective

MTVLSI611C

Communication network

MTOE651C

Business Analytics

MTVLSI613C

Selected Topics in Mathematics

MTOE653C

Industrial Safety

MTVLSI615C

Nano materials and Nanotechnology

MTOE655C

Operations Research

MTVLSI617C

CMOS RF IC Design

MTOE657C

Cost Management of Engineering Projects

MTVLSI619C

Mixed Signal IC Design

MTOE659C

Composite Materials

MTOE661C

Waste to Energy

Note:

1. Student can opt any one subject for electives (V) and one subject for open elective from given list.

1. The choice of students for any elective shall not be binding on the department to offer, if the department does not have expertise. The minimum strength of the students opting for the particular subject shall not be less than 8.


1. Dissertation coordinator will be assigned the load of 1 hour per week excluding his/her own guiding load. However, the dissertation guiding teacher will be assigned a load of one hour per candidate per week.





SEMESTER IV

S. No.

Course No.

Course Title

Teaching Schedule

Marks of Class Work

Examination Marks

Total Marks

Credit

Duration of Exam.

L

P

Theory

Practical

1

MTVLSI652C

Dissertation

(II phase)

-

32

100

-

200

300

16

-

Total

-

32

100

-

200

300

16

-

Note:

Dissertation coordinator will be assigned the load of 1 hour per week excluding his/her own guiding load. However, the dissertation guiding teacher will be assigned a load of one hour per candidate per week.

MTVLSI501c RTL SIMULATION AND SYNTHESIS WITH PLDS

M.Tech. Electronics and Comm. Engg. (VLSI Design)

Semester – I

L T P Credits Class Work : 25 Marks

3 - - 3 Theory : 75 Marks

Total : 100 Marks

Duration of Exam. : 3 Hrs.

Course Objective: The objectives of this course are as under:

1. Familiarity of Finite State Machines, RTL design using reconfigurable logic.

1. Design and develop IP cores and Prototypes with performance guarantees

1. Use EDA tools like Cadence, Mentor Graphics and Xilinx.

UNIT I

Top down approach to design, Design of FSMs (Synchronous and asynchronous), Static Timing analysis, Meta-stability, Clock issues, Need and design strategies for multi-clock domain designs. Design entry by Verilog/ VHDL/ FSM, Verilog AMS.

UNIT II

Programmable Logic Devices, Introduction to ASIC Design Flow, FPGA, SoC, Floor planning, Placement, Clock tree synthesis, Routing, Physical verification, Power analysis, ESD protection.

UNIT III

Design for performance, Low power VLSI design techniques. Design for testability.

UNIT IV

IP and Prototyping: IP in various forms: RTL Source code, Encrypted Source code, Soft IP, Netlist, Physical IP, Use of external hard IP during prototyping, Case studies and Speed issues.

Course Outcomes: At the end of the course, students will be able to:

1. Familiarity of Finite State Machines, RTL design using reconfigurable logic.

1. Design and develop IP cores and Prototypes with performance guarantees.


References Book:

1. Richard S. Sandige, “Modern Digital Design”, MGH, International Editions.

1. Donald D Givone, “Digital principles and Design”, TMH

1. Charles Roth, Jr. and Lizy K John, “Digital System Design using VHDL”, Cengage Model Curriculum of Engineering & Technology PG Courses [Volume -II]

1. Samir Palnitkar, “Verilog HDL, a guide to digital design and synthesis”, Prentice Hall.

1. Doug Amos, Austin Lesea, Rene Richter, “FPGA based prototyping methodology manual”, Xilinx

1. Bob Zeidman, “Designing with FPGAs & CPLDs”, CMP Books.

Note:

1. In the Semester examination, the examiner will set 08 questions in all selecting two from each unit. The candidates will be required to attempt five questions in all, atleast one from each unit. All questions carry equal marks.

1. The use of programmable devices such as programmable claculators, phones, etc. and sharing of materials during the examination is not allowed.

1. A specific note shall be inserted in relevant question paper where ever the use of graph-papers, semi-log papers, steam-tables, etc. shall be allowed during the examination.

MTVLSI503C ANALOG AND DIGITAL CMOS VLSI DESIGN

M.Tech Electronics and Comm. Engg. (VLSI Design)

Semester – I



Total : 100 Marks



1. To analyze, design, optimize and simulate analog and digital circuits using CMOS constrained by the design metrics.

1. To connect the individual gates to form the building blocks of a system.

1. To use EDA tools like Cadence, Mentor Graphics and other open source software tools like Ngspice.

Unit 1

Review: Technology Scaling and Road map, Scaling issues, Basic MOS structure and its static behavior, Quality metrics of a digital design: Cost, Functionality, Robustness, Power, and Delay, Stick diagram and Layout, Wire delay models.

Inverter: Static CMOS inverter, Switching threshold and noise margin concepts and their evaluation, Dynamic behavior, Power consumption

.

Unit II

Combinational logic: Static CMOS design, Logic effort, Ratioed logic, Pass transistor logic, Dynamic logic, Speed and power dissipation in dynamic logic, Cascading dynamic gates, CMOS transmission gate logic.

Sequential logic: Static latches and registers, Bi-stability principle, MUX based latches, Static SR flip-flops, Master-slave edge-triggered register, Dynamic latches and registers.

Unit III

Single Stage Amplifier: CS stage with resistance load, Divide connected load, Current source load, Triode load, CS stage with source degeneration, Source follower, Common gate stage, Cascade stage, Choice of device models. Differential Amplifiers: Basic difference pair, Common mode response, Differential pair with MOS loads, Gilbert cell.

Unit IV

Passive and active current mirrors: Basic current mirrors, Cascade mirrors, Active current mirrors. Frequency response of CS stage: Source follower, Common gate stage, Cascade stage and difference pair, Noise

Operational amplifiers: One stage OPAMP, Two stages OPAMP, Gain boosting, Common mode feedback, Slew rate, PSRR, Compensation of 2 stage OPAMP, Other compensation techniques.

Course Outcomes: At the end of this course, students will be able to

1. Analyze, design, optimize and simulate analog and digital circuits using CMOS constrained by the design metrics.

2. Connect the individual gates to form the building blocks of a system.

3. Use EDA tools like Cadence, Mentor Graphics and other open source software tools like Ngspice.

References:

1. Sedra, Adel S., and Kenneth Carless Smith. Microelectronic circuits. Vol. 1. New York: Oxford University Press, 1998.

1. J P Rabaey, A P Chandrakasan, B Nikolic, “Digital Integrated circuits: A design perspective”, Prentice Hall electronics and VLSI series, 2nd Edition.

1. BehzadRazavi , “Design of Analog CMOS Integrated Circuits”, TMH, 2007.

1. R J Baker, “CMOS circuit Design, Layout and Simulation”, IEEE Inc., 2008.

1. Kang, S. and Leblebici, Y., “CMOS Digital Integrated Circuits, Analysis and Design”, TMH, 3rdEdition.

NOTE:

1.In the Semester examination, the examiner will set 08 questions in all selecting two from each unit. The candidates will be required to attempt five questions in all, atleast one from each unit. All questions carry equal marks.

2.The use of programmable devices such as programmable claculators, phones, etc. and sharing of materials during the examination is not allowed.


MTVLSI551C RTL SIMULATION AND SYNTHESIS WITH PLDS LAB


Semester – I


- - 4 2 Theory : 75 Marks

Total : 100 Marks

Duration of Exam. : 3 Hrs


1. Educate students with knowledge to Identify, formulate, solve and implement problems in signal processing, communication systems etc using RTL design tools.

1. To learn about different EDA Tools.

LIST OF EXPERIMENTS:

1. Verilog implementation of 8:1 Mux/Demux, Full Adder, 8-bit Magnitude comparator, Encoder/decoder, Priority encoder, D-FF, 4-bit Shift registers (SISO, SIPO, PISO, bidirectional), 3-bit Synchronous Counters, Binary to Gray converter, Parity generator.

1. Sequence generator/detectors, Synchronous FSM – Mealy and Moore machines.

1. Vending machines - Traffic Light controller, ATM, elevator control.

1. PCI Bus & arbiter and downloading on FPGA.

1. UART/ USART implementation in Verilog.

1. Realization of single port SRAM in Verilog.

1. Verilog implementation of Arithmetic circuits like serial adder/ subtractor, parallel adder/subtractor, serial/parallel multiplier.

1. Discrete Fourier transform/Fast Fourier Transform algorithm in Verilog.

Course Outcome: At the end of this course, students should be able to:

1. Identify, formulate, solve and implement problems in signal processing, communication systems etc using RTL design tools.


NOTE:

1. Each Laboratory Class/Section shall not be of more than about 20 students.

1. To allow fair opportunity of practical hands-on experience to each student, each experiment may either be done by each student individually or in a group of not more than 3-4 students. Larger groups be strictly discouraged / disallowed.

1. Pre-experimental & post experimental quiz / questions may be offered for each Lab experiment to reinforce & aid comprehension of the experiment.

MTVLSI553C ANALOG AND DIGITAL CMOS VLSI DESIGN LAB


Semester – I


- - 4 2 Theory : 75 Marks

Total : 100 Marks


Course Objective: The objectives of this course laboratory as are under:

1. To Design digital and analog Circuit using CMOS technology

1. To use EDA tools like Cadence, Mentor Graphics and other open source software tools like microwind, ngspice.

List of Experiments:

1. Use VDD=1.8V for 0.18um CMOS process, VDD=1.3V for 0.13um CMOS Process and VDD=1V for 0.09um CMOS Process.

1. Plot ID vs. VGS at different drain voltages for NMOS, PMOS.

1. Plot ID vs. VGS at particular drain voltage (low) for NMOS, PMOS and determine Vt.

1. Plot log ID vs. VGS at particular gate voltage (high) for NMOS, PMOS and determine IOFF and sub-threshold slope.

1. Plot ID vs. VDS at different gate voltages for NMOS, PMOS and determine Channel length modulation factor.

1. Extract Vth of NMOS/PMOS transistors (short channel and long channel). Use VDS =30mV

To extract Vth use the following procedure.

1. Plot gm vs VGS using NGSPICE and obtain peak gm point.

1. Plot ID vs. VDS at different drain voltages for NMOS, PMOS, plot DC load line and calculate gm, gds, gm/gds, and unity gain frequency.

Tabulate your result according to technologies and comment on it.

1. Use VDD=1.8V for 0.18um CMOS process, VDD=1.2V for 0.13um CMOS Process and VDD=1V for 0.09um CMOS Process.

1. Perform the following.

1. Plot VTC curve for CMOS inverter and thereon plot dVout vs. dVin and determine transition voltage and gain gm. Calculate VIL, VIH, NMH, NML for the inverter.

1. Plot VTC for CMOS inverter with varying VDD.

1. Plot VTC for CMOS inverter with varying device ratio.

1. Perform transient analysis of CMOS inverter with no load and with load and determine tpHL, tpLH, 20%-to-80% tr and 80%-to-20% tf. (use VPULSE = 2V, Cload = 50fF).

1. Perform AC analysis of CMOS inverter with fanout 0 and fanout 1. (Use Cin= 0.012pF,Cload = 4pF, Rload = k)

1. Build a three stage and five stage ring oscillator circuit in 0.18um and 0.13um technology and compare its frequencies and time period.

1. Perform the following:

1. Draw small signal voltage gain of the minimum-size inverter in 0.18um and 0.13um technology as a function of input DC voltage. Determine the small signal voltage gain at the switching point and compare the values for 0.18um and 0.13um process.

1. Consider a simple CS amplifier with active load, as explained in the lecture, with NMOS transistor MN as driver and PMOS transistor MP as load, in 0.18um technology. (W/L)MN=5, (W/L)MP=10 and L=0.5um for both transistors.

1. Establish a test bench, as explained in the lecture, to achieve VDSQ=VDD/2.

1. Calculate input bias voltage if bias current=50uA.

1. Obtain the bias current. Compare its value with 50uA.

1. Determine small signal voltage gain, -3dB BW and GBW of the amplifier using small signal analysis (consider 30fF load capacitance).

1. Plot step response of the amplifier for input pulse amplitude of 0.1V. Derive time constant of the output and compare it with the time constant resulted from -3dB BW.

1. To determine input voltage range of the amplifier

1. Two stage OPAMP Vdd=1.8V Vss=0V Note: Adjust accuracy options of the simulator (setup->options in GUI). Use proper values of resistors to get a Two stage OPAMP with differential-mode voltage gain=10.

Consider voltage gain=2 for the first stage and voltage gain=5 for the second stage.

1. Draw the schematic of op-amp macro model.

1. Determine parameters of the op-amp macro model such that

1. Low-frequency voltage gain ,

1. Unity gain BW ,

1. CMRR

1. Draw schematic diagram of CMRR simulation setup.

1. Technology: UMC 0.18um, VDD=1.8V. Use MAGIC or Microwind.

1. Draw layout of a minimum size inverter in UMC 0.18um technology using MAGIC Station layout editor. Use that inverter as a cell and lay out three cascaded minimum-sized inverters. Use M1 as interconnect line between inverters.

1. Run DRC, LVS and RC extraction. Make sure there is no DRC error. Extract the netlist.

1. Use extracted netlist and obtain tPHL & tPLH for the middle inverter.

1. Values of delay times with corresponding values obtained in part ‘c’.

Course Outcomes: At the end of the laboratory work, students will be able to:

1. Design digital and analog Circuit using CMOS.

2. Use EDA tools like Cadence, Mentor Graphics and other open source software tools like microwind, ngspice.

NOTE:

1. Each Laboratory Class/Section shall not be of more than about 20 students.

2. To allow fair opportunity of practical hands-on experience to each student, each experiment may either be done by each student individually or in a group of not more than 3-4 students. Larger groups be strictly discouraged / disallowed.

3. Pre-experimental & post experimental quiz / questions may be offered for each Lab experiment to reinforce & aid comprehension of the experiment.

MTEC557C RESEARCH METHODOLOGY AND IPR

M.Tech. Electronics and Comm. Engg. (VLSI Design)

Semester – I



Total : 100 Marks



1. To understand research problem formulation.

1. To analyze research related information

1. To follow research ethics

1. To understand that today’s world is controlled by Computer, Information Technology, but tomorrow world will be ruled by ideas, concept, and creativity.

1. To understanding that when IPR would take such important place in growth of individuals & nation, it is needless to emphasis the need of information about Intellectual Property Right to be promoted among students in general & engineering in particular.

1. To understand that IPR protection provides an incentive to inventors for further research work and investment in R & D, which leads to creation of new and better products, and in turn brings about, economic growth and social benefits.

UNIT I

Meaning of research problem, Sources of research problem, Criteria Characteristics of a good research problem, Errors in selecting a research problem, Scope and objectives of research problem. Approaches of investigation of solutions for research problem, data collection, analysis, interpretation, Necessary instrumentations.

.

UNIT II

Effective literature studies approaches, analysis, Plagiarism, Research ethics, Effective technical writing, how to write report, Paper Developing a Research Proposal, Format of research proposal, a presentation and assessment by a review committee

UNIT III

Nature of Intellectual Property: Patents, Designs, Trade and Copyright. Process of Patenting and Development: technological research, innovation, patenting, development.

International Scenario: International cooperation on Intellectual Property. Procedure for grants f patents, Patenting under PCT.

UNIT IV

Patent Rights: Scope of Patent Rights. Licensing and transfer of technology. Patent information and databases. Geographical Indications.

New Developments in IPR: Administration of Patent System. New developments in IPR; IPR of Biological Systems, Computer Software etc. Traditional knowledge Case Studies, IPR and IITs.


1. Understand research problem formulation.

1. Analyze research related information

1. Follow research ethics

1. Understand that today’s world is controlled by Computer, Information Technology, but tomorrow world will be ruled by ideas, concept, and creativity.

1. Understanding that when IPR would take such important place in growth of individuals & nation, it is needless to emphasis the need of information about Intellectual Property Right to be promoted among students in general & engineering in particular.

1. Understand that IPR protection provides an incentive to inventors for further research work and investment in R & D, which leads to creation of new and better products, and in turn brings about, economic growth and social benefits.

References:

1. Stuart Melville and Wayne Goddard, “Research methodology: an introduction for science & engineering students’”

1. Wayne Goddard and Stuart Melville, “Research Methodology: An Introduction”

1. Ranjit Kumar, 2nd Edition , “Research Methodology: A Step by Step Guide for beginners”

1. Halbert, “Resisting Intellectual Property”, Taylor & Francis Ltd ,2007.

1. Mayall , “Industrial Design”, McGraw Hill, 1992.

1. Niebel , “Product Design”, McGraw Hill, 1974.

1. Asimov , “Introduction to Design”, Prentice Hall, 1962.

1. Robert P. Merges, Peter S. Menell, Mark A. Lemley, “ Intellectual Property in New Technological Age”, 2016.

1. T. Ramappa, “Intellectual Property Rights Under WTO”, S. Chand, 2008.

NOTE:




MTVLSI511C DIGITAL SIGNAL AND IMAGE PROCESSING


Semester – I



Total : 100 Marks



1. To analyze and characterize discrete-time signals and systems in various domains.

1. To design and implement FIR & IIR filters.

1. To compare algorithmic and computational complexities in processing and coding digital images.

UNIT I

Review of Discrete Time signals and systems, Characterization in time and Z and Fourier domain, Fast Fourier Transform algorithms – In-place computations, Butterfly computations, bit reversal’s.

UNIT II

Digital Filter design: FIR - Windowing and Frequency Sampling, IIR – Impulse invariance, bilinear Transformation. Fixed point implementation of filters – challenges and techniques.

UNIT III

Digital Image Acquisition, Enhancement, Restoration. Digital Image Coding and Compression – JPEG and JPEG 2000.

UNIT IV

Color Image processing – Handling multiple planes, computational challenges. VLSI architectures for implementation of Image Processing algorithms, Pipelining.

Course Outcomes: At the end of this course, students will be able to:

1. Analyze discrete-time signals and systems in various domains.

1. Design and implement filters using fixed point arithmetic targeted for embedded platforms.

1. Compare algorithmic and computational complexities in processing and coding digital images.

References:

1. J.G. Proakis, Manolakis “Digital Signal Processing”, Pearson, 4th Edition

1. Gonzalez and Woods, “Digital Image Processing”, PHI, 3rd Edition

1. S. K. Mitra. “Digital Signal Processing – A Computer based Approach”, TMH, 3rd Edition, 2006

1. A. K. Jain, “Fundamentals of Digital Image Processing”, Prentice Hall

1. KeshabParhi, “VLSI Digital Signal Processing Systems – Design and Implementation”, Wiley India

Note:




MTVSI 513C PROGRAMMING LANGUAGES FOR EMBEDDED SOFTWARE


Semester – I



Total : 100 Marks


Course Objective : The objectives of this course are as under:

1. To write an embedded C application of moderate complexity.

1. To develop and analyze algorithms in C++.

1. To differentiate interpreted languages from compiled languages.

UNIT I

Embedded ‘C’ Programming: Bitwise operations, Dynamic memory allocation, OS services, linked stack and queue, Sparse matrices, Binary tree, Interrupt handling in C, Code optimization issues, Writing LCD drives, LED drivers, Drivers for serial port communication, Embedded Software Development Cycle and Methods (Waterfall, Agile).

UNIT II

Object Oriented Programming: Introduction to procedural, modular, object-oriented and generic programming techniques, Limitations of procedural programming, objects, classes, data members, methods, data encapsulation, data abstraction and information hiding, inheritance, polymorphism.

UNIT III

CPP Programming: ‘cin’, ‘cout’, formatting and I/O manipulators, new and delete operators, Defining a class, data members and methods, ‘this’ pointer, constructors, destructors, friend function, dynamic memory allocation

Overloading and Inheritance: Need of operator overloading, overloading the assignment, overloading using friends, type conversions, single inheritance, base and derived classes, friend classes, types of inheritance, hybrid inheritance, multiple inheritance, virtual base class, polymorphism, virtual functions.

UNIT III

Templates: Function template and class template, member function templates and template arguments, Exception Handling: syntax for exception handling code: try-catch- throw, Multiple Exceptions.

Scripting Languages Overview of Scripting Languages – PERL, CGI, VB Script, Java Script. PERL: Operators, Statements Pattern Matching etc. Data Structures, Modules, Objects, Tied Variables, Inter process Communication Threads, Compilation & Line Interfacing.


1. Write an embedded C application of moderate complexity.

1. Develop and analyze algorithms in C++.

1. Differentiate interpreted languages from compiled languages.

References:

1. Michael J. Pont , “Embedded C”, Pearson Education, 2nd Edition, 2008

1. Randal L. Schwartz, “Learning Perl”, O’Reilly Publications, 6th Edition 2011

1. A. Michael Berman, “Data structures via C++”, Oxford University Press, 2002

1. Robert Sedgewick, “Algorithms in C++”, Addison Wesley Publishing Company, 1999

1. Abraham Silberschatz, Peter B, Greg Gagne, “Operating System Concepts”, John Willey & Sons, 2005

Note:




.

MTVLSI515C VLSI SIGNAL PROCESSING


Semester – I



Total : 100 Marks



1. To acquire knowledge about DSP algorithms, pipelining and parallel processing approaches.

1. To acquire knowledge about retiming techniques, folding and register minimization path problems.

1. To familiarize with algorithmic strength reduction techniques and parallel processing of digital filters.

1. To acquire knowledge about finite word-length effects and round off noise computation in DSP systems.

UNIT I

Introduction to DSP systems, Pipelined and parallel processing, Iteration Bound, Retiming, unfolding, algorithmic strength reduction in filters and Transforms. Systolic architecture design, fast convolution, pipelined and parallel recursive and adaptive filters, Scaling and round off noise.

UNIT II

Digital lattice filter structures, bit level arithmetic, architecture, redundant arithmetic. Numerical strength reduction, synchronous, wave and asynchronous pipe lines, low power design.

UNIT III

Programmable DSP (P-DSP) Processors: Harvard architecture, Multi port memory, architectural structure of P-DSP- MAC unit, Barrel shifters, Introduction to TI DSP processor family.

VLIW architecture and TMS320C6000 series, architecture study, data paths, cross paths, Introduction to Instruction level architecture of C6000 family, Assembly Instructions memory addressing, for arithmetic, logical operations

UNIT IV

Code Composer Studio for application development for digital signal processing, On chip peripheral , Processor benchmarking.

Course Outcomes: At the end of this course, students will be able to:

1. Acquire knowledge about DSP algorithms, its DFG representation, pipelining and parallel processing approaches.

1. Acquire knowledge about retiming techniques, folding and register minimization path problems.

1. Have knowledge about algorithmic strength reduction techniques and parallel processing of FIR and IIR digital filters.

1. Acquire knowledge about finite word-length effects and round off noise computation in DSP systems.

References:

1. Keshab K. Parthi, VLSI Digital signal processing systems, design and implementation , Wiley, Inter Science, 1999.

1. Mohammad Isamail and Terri Fiez, Analog VLSI signal and information processing, McGraw Hill, 1994

1. S.Y. Kung, H.J. White House, T. Kailath, VLSI and Modern Signal Processing, Prentice Hall, 1985.

Note:




MTVLSI517C IC Fabrication Technology


Semester – I



Total : 100 Marks



1. To understand the manufacturing methods and their underlying scientific principles in the context of technologies used in VLSI chip fabrication.

1. To introduce the fundamentals of IC fabrication technology, IC chip size and circuit complexity etc.

1. To provide a strong foundation on Linear Circuits.

1. To familiarize students with applications of various IC’s.

UNIT I

Cleanroom technology: Clean room concept – Growth of single crystal Si. Processing considerations for single crystal growth: Chemical cleaning, getting the thermal Stress factors etc

Epitaxy: Molecular beam epitaxy, Vapour phase epitaxy, Liqid phase epitaxy, Basic Transport processes & reaction kinetics, doping & auto doping, equipments, & safety considerations, buried layers, epitaxial defects, Evaluation of epitaxial layers.

UNIT II

Oxidation: Growth mechanism & kinetics, Silicon oxidation model, interface considerations, orientation dependence of oxidation rates thin oxides. Dry & Wet oxidation. Masking properties of SiO2

Diffusion: Diffusion Mechanisms, The diffusion equation, Diffusion in a concentration gradient, Associated issues, Macroscopic and Microscopic view of diffusion, Fick’s Law, Extrinsic and Intrinsic diffusion, Diffusion Systems

UNIT III

Lithography: Types of photo resists, Electron beam lithography system, Optical Lithography system. Electron optics: roster scans & vector scans, variable beam shape. X-ray lithography: resists & printing, X ray sources & masks.

Etching: Wet chemical etching, Dry physical etching, Dry chemical etching, Reactive ion etching, Reactive plasma etching, Wet etching vs. Plasma etching, Physical vs. Chemical etching, AC & DC plasma excitation, plasma properties.

Ion Implantation: Penetration range, Implantation damage, Annealing, Implantation systems, High energy implants, Process Considerations.

UNIT IV

Metallization: Different types of metallization, uses & desired properties

Differential Metal gate transistor: Transport in Nano MOSFET, velocity saturation, ballistic transport, injection velocity, velocity overshoot, Single electron transistors, coulomb blockade effects in ultra-small metallic tunnel junctions.

Course Outcome: At the end of this course, students will be able to:

1. Understand the manufacturing methods and their underlying scientific principles in the context of technologies used in VLSI chip fabrication.

1. Introduce the fundamentals of IC fabrication technology, IC chip size and circuit complexity etc.

1. Provide a strong foundation on Linear Circuits.

1. Familiarize students with applications of various IC’s.

References:

1. S.M. Sze, “VLSI Technology”, John Wiley & Sons, 2000.

1. S.M.Sze, “High Speed Semiconductor Devices”, Wiley, New York.

1. Sorab K.Ghandhi, “VLSI Fabrication Principles”, John Wiley & Sons

1. S.M. Sze, “Modern Semiconductor Device Physics”, Wiley, New York

1. C.Y. Chang and S.M. Sze, “ULSI Devices”, Wiley New York

Note:




MTVLSI519CSEMICONDUCTOR DEVICE Modeling


Semester – I



Total : 100 Marks

Duration of Exam : 3 Hrs.


1. To study about solid state electronic device modelling.

1. To study of basic and advanced MOSFET models and passive device modelling.

1. To study of advanced MOSFET structures.

1. To study of process variation modelling and device mismatch.

UNIT I

MOSFET Device Physics: MOS capacitor, Basic operation, Basic modelling, Comparison of basic MOSFET models, Advanced MOSFET modeling, RF modeling of MOS transistors, Equivalent circuit representation of MOS transistor, High frequency behavior of MOS transistor and A.C small signal modelling.

UNIT II

Noise Modeling: Noise sources in MOSFET, Flicker noise modeling, Thermal noise modeling, model for accurate distortion analysis, nonlinearities in CMOS devices and modeling, calculation of distortion in analog CMOS circuits.

UNIT III

Advanced MOSFET Structures and Models: SOI MOSFET, FDSOI and PDSOI, Multigate transistors: double gate MOSFET and FINFET, Charge based models and surface potential models : ACM, EKV, BSIM5, HiSIM, MOS Model 11 and SP Model.

UNIT IV

BJT and Passive Device Modelling: Modelling passive BJT, Modelling resistors, capacitors and inductors.

Modeling of Process Variation and Device Mismatch: Influence of process variation, modeling of device mismatch for Analog/RF Applications, Benchmark circuits for quality assurance.

Course Outcome: At the end of this course, student will be able to

1. Utilize the various MOSFET device models available in various CAD tools.

1. Model basic and advanced MOSFET structures and passive devices.

1. Contribute to development and study of newer models for existing and emerging newer versions of MOSFET devices.

1. Build the process variation and device mismatch models.

Reference Books:

1. Trond Ytterdal, Yuhua Cheng and Tor A. Fjeldly, “Device Modeling for Analog and RF”.

1. Ben G. Streetman, “Solid State Electronic Devices”, Prentice Hall.

1. Trond Ytterdal, Tor A. Fjeldly and Michael S. Shur, “Introduction To Device Modelling and Circuit Simulation”.

1. Narain Arora, “MOSFET modelling for VLSI Simulation”.

1. Richard S. Muller, Theodore I. Kamins, “Device Electronics for integrated circuits”, Wiley, 3rd Edition 2002.

Note:




MTVLSI521C PARALLEL PROCESSING


Semester – I



Total : 100 Marks



1. To identify limitations of architectures of computers and understand the principle of Parallel Processing and Pipelining.

1. To analyze the performance of different computer architectures.

1. To understand principles of multithreading and investigate issues related to computer architectures..

Unit I

Overview of Parallel Processing and Pipelining, Performance analysis, Scalability. Principles and implementation of Pipelining, Classification of pipelining processors, Advanced pipelining techniques, Software pipelining.

Unit II

VLIW processors Case study: Superscalar Architecture- Pentium, Intel Itanium Processor, Ultra SPARC, MIPS on FPGA, Vector and Array Processor, FFT Multiprocessor Architecture.

Unit III

Multithreaded Architecture, Multithreaded processors, Latency hiding techniques. Principles of multithreading, Issues and solutions.

Unit IV

Parallel Programming Techniques: Message passing program development, Synchronous and asynchronous message passing, Shared Memory Programming, Data Parallel Programming, Parallel Software Issues, Operating systems for multiprocessors systems, Customizing applications on parallel processing platforms.


1. Identify limitations of different architectures of computer

1. Analysis quantitatively the performance parameters for different architectures

1. Investigate issues related to compilers and instruction set based on type of architectures.

References:

1. Kai Hwang, Faye A. Briggs, “Computer Architecture and Parallel Processing”, MGH, International Edition

1. Kai Hwang, “Advanced Computer Architecture”, TMH

1. V. Rajaraman, L. Sivaram Murthy, “Parallel Computers”, PHI.

1. William Stallings, “Computer Organization and Architecture, Designing for performance” Prentice Hall, Sixth edition

1. Kai Hwang, Zhiwei Xu, “Scalable Parallel Computing”, MGH

1. David Harris and Sarah Harris, “Digital Design and Computer Architecture”, Morgan Kaufmann.

Note:




MTVLSI523 C SYSTEM DESIGN WITH EMBEDDED LINUX


Semester – I



Total : 100 Marks



1. To understand embedded Linux development model

1. To understand Embedded Linux drivers and Real time Linux.

1. To understand Linux BSP for a hardware platform.

UNIT I

Embedded Linux Vs Desktop Linux, Embedded Linux Distributions, Embedded Linux Architecture, Kernel Architecture – HAL, Memory manager, Scheduler, File System, I/O and Networking subsystem, IPC, User space, Start-up sequence.

UNIT II

Board Support Package, Embedded Storage: MTD, Architecture, Drivers, Embedded File System, Embedded Drivers: Serial, Ethernet, I2C, USB, Timer, Kernel Modules.

UNIT III

Porting Applications, Real-Time Linux: Linux and Real time, Programming, Hard Real-time Linux.

UNIT IV

Building and Debugging: Kernel, Root file system, Embedded Graphics, Case study of uClinux.


1. Familiarity of the embedded Linux development model.

1. Write, debug, and profile applications and drivers in embedded Linux.

1. Understand and create Linux BSP for a hardware platform

References:

1. Karim Yaghmour, “Building Embededd Linux Systems”, O'Reilly & Associates

1. P Raghvan, Amol Lad, SriramNeelakandan, “Embedded Linux System Design and Development”, Auerbach Publications

1. Christopher Hallinan, “Embedded Linux Primer: A Practical Real World Approach”, Prentice Hall, 2nd Edition, 2010.

1. Derek Molloy, “Exploring BeagleBone: Tools and Techniques for Building with Embedded Linux”, Wiley, 1st Edition, 2014.

Note:




MTVLSI525C CAD OF DIGITAL SYSTEM


Semester – I



Total : 100 Marks



1. Fundamentals of CAD tools for modelling, design, test and verification of VLSI systems.

1. To Study of various phases of CAD, including simulation, physical design, test and verification.

1. To demonstrate knowledge of computational algorithms and tools for CAD.

UNIT I

VLSI Design Methodologies: Introduction to VLSI Methodologies – Design and Fabrication of VLSI Devices, Fabrication Process and its impact on Design. Review of VLSI Design automation tools - Algorithmic Graph Theory and Computational Complexity - Tractable and Intractable problems - general purpose methods for combinatorial optimization.

UNIT II

Modeling: Modeling techniques, Types of CAD tools and Introduction to logic simulation Verilog: Syntax, Hierarchical modeling and Delay modeling, Verilog constructs, Memory modeling.

Synthesis: synthesis - Synthesizable and Non Synthesizable constructs, Logic Optimization, Resource Sharing, Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis.

UNIT III

Logic and layout synthesis: Technology mapping, ASIC design methodology, FPGA based system design and prototyping, layout synthesis: the physical design, timing analysis, graph algorithms and their application in IC design.

High level SYNTHESIS: High level Synthesis - Hardware models - Internal representation - Allocation - assignment and scheduling - Simple scheduling algorithm - Assignment problem - High level transformations.

UNIT IV

Simulation: Gate-level modeling and simulation, Switch-level modeling and simulation, MCMS-VHDL Verilog implementation of simple circuits using VHDL

Course Outcomes:

At the end of this course, students will be able to:

1. Fundamentals of CAD tools for modelling, design, test and verification of VLSI systems.

1. Study of various phases of CAD, including simulation, physical design, test and verification.

1. Demonstrate knowledge of computational algorithms and tools for CAD.

References:

1. N.A. Sherwani, “Algorithms for VLSI Physical Design Automation”.

1. S.H. Gerez, “Algorithms for VLSI Design Automation.

1. M. Sarrafzadeh and C.K. Wong, An Introduction to VLSI Physical Design, McGraw Hill, 1996

1. D.D Gajski et al., High Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, 1992

1. Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, Tata McGraw Hill, 1994

NOTE:




MTVLSI527CIntroduction to MEMS


Semester – I



Total : 100 Marks



1. To introduce MEMS and micro fabrication.

1. To study various etching techniques.

1. To know various fabrication and machining process of MEMS.

1. To know about the polymer and optical MEMS.

UNIT I

Historical Background: MicroElectroMechanicalSystems.: Introduction,evolution, applications, MEMS system-level design methodology.

Scaling laws in Miniaturized Designs: Scaling in electrostatic forces, electromagnetic forces, Scaling in electricity, fluid mechanics and heat transfer

UNIT II

Physical Microsensors: Classification of physical sensors, Integrated, Intelligent, or Smart sensors, Sensor Principles and Examples: Thermal sensors, Electrical Sensors, Mechanical Sensors, Chemical and Biosensors,Pressure Sensor,Accelerometer.

Microactuators: Electromagnetic and Thermal microactuation, Microactuator examples,microgrippers, microvalves, micropumps, micromotors-Microactuator systems : Ink-Jet printer heads, Micro-mirror TV Projector.

UNIT III

Microfabrication and Micromachining: Integrated Circuit Processes ,Micromachining Introduction , Bulk Micromachining: Isotropic Etching and Anisotropic Etching, Wafer Bonding, High Aspect-Ratio Processes (LIGA).

Surface Micromachining: One or two sacrificial layer processes, Surface micromachining requirements, Polysilicon surface micromachining, Other compatible materials, Silicon Dioxide, Silicon Nitride, Piezoelectric materials.

UNIT IV

Application Areas: All-mechanical miniature devices, RF/Electronics devices, Optical/Photonic devices, Medical devices e.g. DNA-chip, micro-arrays.

Micropackaging: Microsystem Packaging, Interfaces in Microsystem Packaging, Packaging Technologies, Three dimensional packaging, Microsystems assembly, Selection of Packaging Materials.

Course Outcome: After completion of the course, students will be able to

1. Design, analysis and testing of MEMS.

1. Report on various wet etching techniques and describe their principles and possible usage.

1. Qualitatively describe surface micromachining and stress properties associated with various deposition techniques.

1. Describe fundamental principles and processes for packaging of microsystems.

Text Books:

1. Stephen D. Senturia, "Microsystem Design" by, Kluwer Academic Publishers, 2001.

1. Tai-Ran Hsu, “MEMS & MICROSYSTEMS Design and Manufacture”, Mc Graw Hill Pub.,2016.

Reference Books:

1. Fundamentals of Microfabrication by, CRC Press, 1997.Gregory Kovacs, Micromachined Transducers Sourcebook WCB McGraw-Hill, Boston, 1998.

1. M.-H. Bao, Micromechanical Transducers: Pressure sensors, accelrometers, and gyroscopes by Elsevier, New York, 2000.

Note:




MTVLSI529CAdvanced Computer Architecture


Semester – I



Total : 100 Marks

Duration of Exam.:3 Hrs.


1. To describe modern architectures such as RISC, Super Scalar, VLIW, multi-core and multi-CPU systems.

1. To understand the various techniques to enhance a processors ability to exploit Instruction-level parallelism (ILP), and its challenges.

1. To improve performance of different CPU architectures and develop applications for high performance computing systems.

UNIT I

Parallel computer models: The state of computing, Classification of parallel computers, Multiprocessors and multicomputer, Multivector and SIMD computers.

Program and network properties: Conditions of parallelism, Data and resource Dependences, Hardware and software Parallelism, Program partitioning and scheduling, Grain Size and latency, Program flow mechanisms, Control flow versus data flow, Data flow Architecture, Demand driven mechanisms, Comparisons of flow mechanisms.

UNIT II

System Interconnect Architectures:

Network properties and routing, Static interconnection Networks, Dynamic interconnection Networks, Multiprocessor system Interconnects, Hierarchical bus systems, Crossbar switch and multiport memory, Multistage and combining network.

Advanced processors: Advanced processor technology, Instruction-set Architectures, CISC Scalar Processors, RISC Scalar Processors, Superscalar Processors, VLIW Architectures, Vector and Symbolic processors.

UNIT III

Pipelining: Linear pipeline processor, nonlinear pipeline processor, Instruction pipeline Design, Mechanisms for instruction pipelining, Dynamic instruction scheduling, Branch Handling techniques, branch prediction, Arithmetic Pipeline Design, Computer arithmetic principles, Static Arithmetic pipeline, Multifunctional arithmetic pipelines.

Memory Hierarchy Design: Cache basics & cache performance, reducing miss rate and miss penalty, multilevel cache hierarchies, main memory organizations, design of memory hierarchies.

UNIT IV

Multiprocessor architectures: Symmetric shared memory architectures, distributed shared memory architectures, models of memory consistency, cache coherence protocols (MSI, MESI, MOESI), scalable cache coherence, overview of directory based approaches, design challenges of directory protocols, memory based directory protocols, cache based directory protocols, protocol design trade-offs, synchronization.

Scalable point – point interfaces: Alpha364 and HT protocols, high performance signaling layer.

Enterprise Memory subsystem Architecture: Enterprise RAS Feature set: Machine checks, hot add/remove, domain partitioning, memory mirroring/migration, patrol scrubbing, fault tolerant system.

Course Outcome: On successful completion of this course student will be able to:

1. Describe modern architectures such as RISC, Super Scalar, VLIW, multi-core and multi-CPU systems.

1. Understand the various techniques to enhance a processors ability to exploit Instruction-level parallelism (ILP), and its challenges.

1. Improve application performance for different CPU architectures and develop applications for high performance computing systems.

Reference Books:

1. Kai Hwang, “Advanced computer architecture”, TMH. 2000

1. D. A. Patterson and J. L. Hennessey, “Computer organization and design”, Morgan Kaufmann, 2nd Ed. 2002.

1. J. P. Hayes, “computer Architecture and organization”; MGH. 1998.

1. Harvey G. Cragon, “Memory System and Pipelined processors” Narosa Publication. 1998.

1. V. Rajaranam& C. S. R. Murthy, “Parallel computer”; PHI. 2002

1. R.K.Ghose, Rajan Moona&Phalguni Gupta, “Foundation of Parallel Processing”, Narosa Publications, 2003.

NOTE:




M.Tech. Programme (Audit Course)

AUD531C: ENGLISH FOR RESEARCH PAPER WRITING

M. Tech. Semester – I/II (Common to all Branches)

L

P

Credits

Class Work

:

25Marks

2

--

--

Examination

:

75 Marks

Total

:

100 Marks

Duration of Examination

:

3 Hours

Course Objectives: Students will be able to:

1. Understand that how to improve your writing skills and level of readability,

1. Learn about what to write in each section,

1. Understand the skills needed when writing a Title, and

1. Ensure the good quality of paper at very first-time submission

Course Outcomes:

The Students will become conscious citizens of India aware of their duties, rights and functions of various bodies of governance and welfare; thereby well equipped to contribute to India.

UNIT I: Basics of Writing Skills:

Subject Verb Agreements; Parallelism; Structuring Paragraphs and Sentences; Being Concise and Removing Redundancy; Avoiding Ambiguity and Vagueness; Dangling Modifiers

UNIT II: Reviewing and Citation:

Clarifying Who Did What; Highlighting Your Findings from Literature; Hedging and Critiquing; Paraphrasing; Avoiding Plagiarism; Formatting and Citation (Publication Manual of the American Psychological Association)

UNIT III: Sections of a Research Paper:

Writing Effective and Impressive Abstract; Writing Introduction; Review of Literature; Defining Objectives of the Study; Methodology Adopted; Results Obtained; Discussion and Conclusion; Editing and Proof Reading to Ensure Quality of paper

UNIT IV: Oral Presentation for Academic Purposes:

Oral Presentation for Seminars, Conferences and Symposiums; Poster Presentation; Choosing AppropriateMedium; Interaction and Persuasion

TEXT / REFERENCE BOOKS:

1. Goldbort R (2006) Writing for Science, Yale University Press (available on Google Books).

1. Day R (2006) How to Write and Publish a Scientific Paper, Cambridge University Press.

1. Highman N (1998), Handbook of Writing for the Mathematical Sciences, SIAM. Highman’sbook.

1. Adrian Wallwork, English for Writing Research Papers, Springer, New York Dordrecht Heidelberg London, 2011

1. Mc Murrey,David A. and Joanne Buckley. Handbook for Technical Writing. New Delhi: Cengage Learning, 2008.

NOTE:

1. In the semester examination, the examiner will set 08 questions in all selecting two from each unit. The candidates will be required to attempt five questions in all selecting at least one from each unit. All questions will carry equal marks.

1. The students will be allowed to use non-programmable scientific calculator. However, sharing/exchange of calculator is prohibited in the examination.

1. Electronics gadgets including Cellular phones are not allowed in the examination.

AUD533C: DISASTER MANAGEMENT

M. Tech. Semester – I/II (Common for all Branches)

L

P

Credits

Class Work

:

25Marks

2

--

--

Examination

:

75 Marks

Total

:

100 Marks


:

3 Hours

Course Objectives:

1. Learn to demonstrate a critical understanding of key concepts in disaster risk reduction and humanitarian response

1. Critically evaluate disaster risk reduction and humanitarian response policy and practice from multiple perspectives

1. Develop an understanding of standards of humanitarian response and practical relevance in specific types of disasters and conflict situations

1. Critically understand different aspects of disaster management

Course Outcomes: A student will be able to:

1. Know the significance of disaster management,

1. Study the occurrences, reasons and mechanism of various types of disaster

1. Learn the preventive measures as Civil Engineer with latest codal provisions

1. Apply the latest technology in mitigation of disasters

UNIT I: Introduction to Disaster Management: Definitions: Disaster, Emergency, Hazard, Mitigation, Disaster Prevention, Preparedness and Rehabilitation, Risk and Vulnerability, Classification of Disaster, Natural and Man made Disasters, Disaster Management Act 2005, Role of NDMA, NDRF, NIDM

Risk and Vulnerability to disaster mitigation and management options: Concept and Elements, Risk Assessment, Vulnerability, Warning and Forecasting.

UNIT II: Hydro-meteorological based disasters I: Tropical Cyclones, Floods, droughts, mechanism, Causes, role of Indian Metrological Department, Central Water Commission, structure and their impacts, classifications, vulnerability, Early Warning System, Forecasting, Flood Warning System, Drought Indicators, recurrence and declaration, Structural and Non-structural Measures.

Hydro-meteorological based disasters II: Desertification Zones, causes and impacts of desertification, Characteristics, Vulnerability to India and Steps taken to combat desertification, Prevention.

UNIT III: Geological based disasters: Earthquake, Reasons, Direct and Indirect Impact of Earthquake; Seismic Zones in India, Factors, Prevention and Preparedness for Earthquake, Tsunamis, Landslides and avalanches: Definition, causes and structure; past lesson learnt and measures taken; their Characteristic features, Impact and prevention, structural and non-structural measures.

UNIT IV: Manmade Disasters I: Chemical Industrial hazards; causes and factors, pre- and post disaster measures; control ; Indian Standard Guidelines and Compliance; Oil Slicks and Spills, Outbreak of Disease and Epidemics, Traffic accidents; classification and impact, War and Conflicts; Fire risk assessment; Escape routes; fire fighting equipment;

Use of remote sensing and GIS in disaster mitigation and management.


1. Thomas D. Schneid., Disaster Management and Preparedness, CRC Publication, USA, 2001

1. Patrick Leon Abbott, Natural Disasters, Amazon Publications, 2002

1. Ben Wisner., At Risk: Natural Hazards, People vulnerability and Disaster, Amazon Publications, 2001

1. Oosterom, Petervan, Zlatanova, Siyka, Fendel, Elfriede M., “Geo-information for Disaster Management”, Springer Publications, 2005

1. Savindra Singh and Jeetendra Singh, Disaster Management, Pravalika Publications, Allahabad

1. Nidhi GaubaDhawan and AmbrinaSardar Khan, Disaster Management and Preparedness, CBS Publishers & Distribution

1. Selected Resources Published by the National Disaster Management Institute of Home Affairs, Govt. of India, New Delhi.

NOTE:




AUD535C: SANSKRIT FOR TECHNICAL KNOWLEDGE

M. Tech. Semester – I/II (Common for all Branches Engineering)

L

P

Credits

Class Work

:

25Marks

2

--

--

Examination

:

75 Marks

Total

:

100 Marks


:

3 Hours

Course Objectives:

1. To get a working knowledge in illustrious Sanskrit, the scientific language in the world

1. Learning of Sanskrit to improve brain functioning

1. Learning of Sanskrit to develop the logic in Mathematics, Science & other subjects

1. Enhancing the memory power

Course Outcomes: Students will be able to

1. Understand basic Sanskrit language

1. Understand Ancient Sanskrit literature about science and technology

1. Get equipped with Sanskrit and explore the huge knowledge from ancient literature


1. “Abhyaspustakam” – Dr.Vishwas, Samskrita-Bharti Publication, New Delhi

1. “Teach Yourself Sanskrit” Prathama Deeksha-VempatiKutumbshastri, Rashtriya Sanskrit Sansthanam, New Delhi Publication

1. “India’s Glorious Scientific Tradition” Suresh Soni, Ocean books (P) Ltd., New Delhi.

NOTE:




AUD537C: VALUE EDUCATION


L

P

Credits

Class Work

:

25Marks

2

--

--

Examination

:

75 Marks

Total

:

100 Marks


:

3 Hours

Course Objectives: The students will be able to

1. Understand value of education and self- development

1. Imbibe good values in students

1. Let the should know about the importance of character

Course Outcomes: The students will be able to

1. Knowledge of self-development

2. Learn the importance of Human values

3. Developing the overall personality

4. Strengthen the “EQ”

Unit I: Hierarchy and Classification of values,

Values and Belief Systems, Competence in professional ethics,

Value judgment based on cultural, tradition and interdependence.

Unit II: Need for value education

Sense of duty.Devotion, Self-reliance.

Honesty, Humanity, trust.Patriotism and national Unity.

Harmony in the nature and realization of coexistence

Vision of better India

Unit III: Understanding the meaning and realizing the effect of the following:

Aware of self- destructive habits, Knowledge, Acceptance, Love, Situations, happiness, Bliss, Peace,Power, Purity , Realization, Assertiveness, Regard, Respect, Sensitive, Divinity, emotions, Repentance, hurt, Ego, Attachment, worry, Resentment, Fear, Anxiety, Greed, Criticism, Tension, Frustration, Expectation, Irritation, Anger, Guilt, Jealous, Pear Pressure, True Friendship, Cooperation -Coordination- competition.

Enhancing self esteem and personality.

Unit IV: Hinduism, Jainism, Buddhism, Christianity, Islam, Sikhism.

Self-management and Good health ( Role, Responsibility, Relation, Routine, Requirements, Resources)

My True self and Original qualities.Supreme-soul- source of values.

What Scientists say about super power?


1. Chakroborty, S.K. Values and Ethics for organizations Theory and practice. Oxford University Press, New Delhi.

1. R R Gaur, R Sangal, G P Singh.Human Values and Professional Ethics. Excell Books, New Delhi.

1. Value Education in Spirituality- Course-I, course -II by Brahma Kumaris Education Wing, RajyogaEducation & Research Foundation, Mount Abu, Rajasthan.

1. True Management: I K International Publication 2018.

NOTE:




AUD539C: CONSTITUTION OF INDIA


L

P

Credits

Class Work

:

25Marks

2

--

--

Examination

:

75 Marks

Total

:

100 Marks


:

3 Hours

Course Objectives: Students will be able to:

1. Understand the premises informing the twin themes of liberty and freedom from a civil rights perspective.

1. To address the growth of Indian opinion regarding modern Indian intellectuals’ constitutional role and entitlement to civil and economic rights as well as the emergence of nationhood in the early years of Indian nationalism.

1. To address the role of socialism in India after the commencement of the Bolshevik Revolution in 1917 and its impact on the initial drafting of the Indian Constitution.

Course Outcomes:

The Students will become conscious citizens of India aware of their duties, rights and functions of various bodies of governance and welfare; thereby well equipped to contribute to India.

Unit I: Making of the Indian Constitution and its Philosophy

Sources of Indian Constitution, its Preamble and Salient Features.

Unit II: Constitutional Rights & Duties

Fundamental Rights: Right to Equality, Right to Freedom, Right against Exploitation, Right to Freedom of Religion, Cultural and Educational Rights, Right to Constitutional Remedies

Fundamental Duties

Unit III: Organs of Governance

Legislature: Parliament and its Composition; Qualifications and Disqualifications of Its members

Executive: President, Governor and Council of Ministers

Judiciary: Appointments, Qualifications, Powers and Functions of judges

Unit IV: Local Administration and institutes for welfare

District Administration Head: Role and Importance; Municipalities: Introduction, Mayor and role of Elected Representative

Panchayati Raj Institutions: Introduction, Gram Panchayat, Panchayat Samiti and Zila Panchayat

Institutes and Bodies for the welfare of SC/ST/OBC and women


1. The Constitution of India, 1950 (Bare Act), Government Publication.

1. Dr. S. N. Busi, Dr. B. R. Ambedkar. Framing of Indian Constitution, 1st Edition, 2015.

1. M. P. Jain, Indian Constitution Law, 7th Ed., Lexis Nexis, 2014

NOTE:




AUD541C: PEDAGOGICAL STUDIES


L

P

Credits

Class Work

:

25Marks

2

--

--

Examination

:

75 Marks

Total

:

100 Marks


:

3 Hours

Course Objectives: The course will enable the student teachers:

1. To understand the concept of pedagogy and conceptual framework.

1. To gain insight on the meaning and nature of different pedagogies.

1. To determine aims and strategies of teaching- learning.

1. To understand the principals, maxims of successful teaching and the different methods of teaching.

1. Comprehend the need and importance of various devices of teaching and learning and their relationship between the two.

1. Point out and illustrate the difference between teaching and learning and their relationship between the two.

1. To appreciate that science/ engineering is a dynamic and expanding body of knowledge.

Course Outcomes: Students will be able to understand:

1. It will improve teaching effectiveness of prospective teachers.

1. A prospective teacher will be able to design curriculum and assess the curriculum of their discipline in an effective way by understating the needs of the learners.

1. How can teacher education, school curriculum and guidance support effective pedagogy?

1. It will be functional for professional development among teachers.

Unit I: Introduction and Methodology

1. Aims and Rationale, Conceptual Framework, Terminology related to Pedagogy

1. Contexts, Research Questions

1. Theories of Learning, Curriculum, Scope of Pedagogy

Unit II: Teaching

1. Meaning and importance of Behavioral Objectives

1. Writing of Objectives in Behavioral Terms

1. Phases and Variables of Teaching

1. Principles, levels and maxims off teaching

1. Relationship between Teaching and Learning

Unit III: Methods of Teaching

1. Methods: Inductive, Deductive, Project, Analytic, Synthetic, Brain Storming, Case Discussion

1. Concept and Significance of Individualized and Cooperative Teaching-Language Laboratory, Tutorials, Keller’s Plan (PSI), Computer Supporting Collaborative Learning

1. Mastery Learning: Concept, Basic Elements, Components and Types of Mastery Learning Strategies

Unit IV: Evaluation Strategies

1. Evaluation in Teaching: Concept of Evaluation, Relationship between Teaching and Evaluation, Types of Evaluation (Formative and Summative)

1. Methods of Evaluation through Essay Type. Objective Type and Oral Method, Comparative merits and demerits of evaluation methods

1. Latest Trends in Evaluation


1. Ackers J, Hardman F (2001) Classroom interaction in Kenyan primary schools, Compare, 31 (2): 245-261.

1. Agrawal M (2004) Curricular reform in schools: The importance of evaluation, Journal of

Curriculum Studies, 36 (3): 361-379.

1. Akyeampong K (2003) Teacher training in Ghana - does it count? Multi-site teacher education research project (MUSTER) country report 1. London: DFID.

1. Akyeampong K, Lussier K, Pryor J, Westbrook J (2013) Improving teaching and learning of basic maths and reading in Africa: Does teacher preparation count? International Journal Educational Development, 33 (3): 272–282.

1. Alexander RJ (2001) Culture and pedagogy: International comparisons in primary education. Oxford and Boston: Blackwell.

1. Chavan M (2003) Read India: A mass scale, rapid, ‘learning to read’ campaign.

1. www.pratham.org/images/resource%20working%20paper%202.pdf.

1. Dyer C (2008) Early years literacy in Indian urban schools: Structural, social and pedagogical issues, Language and Education, 22 (5): 237-253.

1. Sharma N (2013) An exploration of teachers’ beliefs and understanding of their pedagogy, MPhil thesis, Mumbai: TATA Institute of Social Sciences.

1. Zeichner K, Liston D (1987) Teaching student teachers to reflect, Harvard Educational Review, 56 (1): 23-48.

1. Watkins C, Mortimore P (1999) Pedagogy: What do we know? In Mortimore P (ed.) Understanding pedagogy and its impact on learning. London: Paul Chapman Publishing.

1. Tyler R (1949) Basic principles of curriculum and instruction. Chicago: Chicago University Press.

1. Arends, R.1. ( 1 994) Learning to Teach, New York: McGraw-Hill.

1. Lunenberg M, Korthagen F, Swennen A (2007) The teacher educator as a role model, Teaching and Teacher Education, 23: 586-601.

1. Meena . Wilberforce E. Curriculum Innovation in Teacher Education: Exploring Conceptions among Tanzanian Teacher Educators. ÅBO AKADEMI UNIVERSITY PRESS, 2009.

1. Cooley, W. W., and Lohnes, P. R. (1976). Evaluation research in education. New York: Irvington.

1. Hassard, Jack, 2004, The Art of Teaching Science, Oxford Univesity Press.

1. Joyce, B., Weil, M., Calhoun, E. : (2000). Models of teaching, 6th edition, Allyn & Bacon.

1. Kyriacou, C. (2007) Effective teaching in schools – theory and practice. Cheltenham: Nelson Thornes.

1. Nye, B., Konstantopoulos, S. & Hedges, L.V. (2004) ‘How large are teacher effects?’ Educational evaluation and policy analysis, 26(3), 237-257.

1. National Staff Development Council. (2001). NSDC’s standards for staff development. Oxford, OH: Author.

1. Serpell, Z. & Bozeman, L. (1999). Beginning teacher induction: A report on beginning teacher effectiveness and retention. Washington, DC: National Partnership for Excellence and Accountability in Teaching.

NOTE:


1. The students will be allowed to use non-progra

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hkcl.co.inhkcl.co.in/.../2019/01/MTEC_ECE-VLSI-Design_2018.docx · Web viewThe Dissertation (Phase-I) involving literature survey and problem formulation along with data collection