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High-Speed Serial InterfaceCircuits and Systems
Design Exercise4 –
Charge Pump
High-Speed Circuits and Systems Lab., Yonsei University
Charge Pump PLL
High-Speed Circuits and Systems Lab., Yonsei University2
– Converts PFD phase error pulse (digital) to charge (analog).
– Charge is proportional to PFD pulse widths.
• Qcp = Iup * tup – Idown * tdown
– Qcp is filtered and integrated in low-pass filter.
PFD CP LF VCO
Divider
ɸref
ɸdiv
ɸout
up
down
Review of Charge Pump PLL
High-Speed Circuits and Systems Lab., Yonsei University3
Basic Charge Pump
High-Speed Circuits and Systems Lab., Yonsei University4
Pbias
DOWN
Nbias
Vdd
Vcont
M2
UPM4
M3
M1
– Charge pump circuit consists of 2 current sources and 2 switches.
Vcont
Vdd
Current Mismatch
High-Speed Circuits and Systems Lab., Yonsei University5
– Up & down current should be same.
– Current mismatch results in static phase offset, which results in
periodic ripple on the control voltage.
A
Pbias
DOWN
Nbias
Vdd
Vcont
PFD
M2
B
UP UPM4
M3
M1
UP
DOWN
IM3
IM4
Net
Current
Vcont
t
Current Mismatch
High-Speed Circuits and Systems Lab., Yonsei University6
Drain
Source
Gate
nbias
Gate
Pbias
Source
Drain
ID
VDS
Channel length
modulation
ID
VDS
Channel length
modulation
ID
VDSVdd/2
200uA
Available region
Pbias
DOWN
Nbias
Vdd
Vcont
M2
UPM4
M3
M1
– Vcont is changed according to locking voltage.
– Current mismatch is caused by channel length modulation.
– Equal nmos and pmos current over entire Vcont range.
• Reduce phase error.
Basic CP Simulation
High-Speed Circuits and Systems Lab., Yonsei University7
– PMOS size (2개동일)
• Length : 180 nm
• Width : 5.2 um
– NMOS size (2개동일)
• Length : 800 nm
• Width : 5.1 um
– Nbias
• Voltage : 0.9 V
– Pbias
• Voltage : 0.9 V
– Target charge pump current
• Current : 200 uA
CurrentMonitor
Simulation Condition
• Simulation condition setting
– Choose analysis
– Analysis : DC
– Design variable : cont
– Sweep range : 0 ~ 1.8
• Sweep type : Linear
• Step size : 0.1
– Enabled check
– OK
High-Speed Circuits and Systems Lab., Yonsei University8
Simulation Results
• Plot simulation results (Current)
– Results → Direct Plot → Main Form
– Function : current
– Select : terminal
– Add to outputs check
– Schematic node choice
• DC symbol (+) node click
– OK
High-Speed Circuits and Systems Lab., Yonsei University9
NMOS Current
Pbias
DOWN
Nbias
Vdd
Vcont
M2
UPM4
M3
M1
1.8V
(OFF)
1.8V
(ON)
Vcont (0.9V)
: 199.94uA
Vcont (1.8V)
: 200.94uA
∆ ID: 1.09uA
Vcont
ID
High-Speed Circuits and Systems Lab., Yonsei University10
PMOS Current
Vcont (0.9V)
: 199.45uA
Vcont (0V)
: 204.30uA
Pbias
DOWN
Nbias
Vdd
Vcont
M2
UPM4
M3
M1
0V
(ON)
0V
(OFF)
∆ ID: 5.38uA
Vcont
ID
High-Speed Circuits and Systems Lab., Yonsei University11
NMOS & PMOS Current
Vcont
ID
Vcont : 0.9V
∆ ID: 0.5uA
Vcont : 0.5V
∆ ID: 15uA
Vcont : 1.3V
∆ ID: 23uA
NMOS currentPMOS currentPbias
DOWN
Nbias
Vdd
Vcont
M2
UPM4
M3
M1
0V
(ON)
1.8V
(ON)
High-Speed Circuits and Systems Lab., Yonsei University12
PMOS – NMOS Current
Vcont
Vcont : 0.9V
Icont: 0.5uA
Vcont : 0.5V
Icont: 15uA
Vcont : 1.3V
Icont: 23uA
Pbias
DOWN
Nbias
Vdd
Vcont
M2
UPM4
M3
M1
0V
(ON)
1.8V
(ON)
Icont
PMOS
current ↑
NMOS
current ↑
High-Speed Circuits and Systems Lab., Yonsei University13
Leakage Current
Vcont
Vcont : 0.9V
Icont: 3.8pA
Vcont : 0.5V
Icont: 11.5pA
Vcont : 1.3V
Icont: -2.2pA
PMOS
leakage ↑
NMOS
leakage ↑
Pbias
DOWN
Nbias
Vdd
Vcont
M2
UPM4
M3
M1
1.8V
(OFF)
0V
(OFF)
Icont
High-Speed Circuits and Systems Lab., Yonsei University14
Reducing Mismatch using Replica
AM
P+ -
UP
Pbias
DOWN
Nbias
Vdd
Vss
Vss
Vdd
Cont
Mp1
Mp2
Mn1
Mn2
Mp1
Mp2
Mn1
Mn2
Replica Circuit
High-Speed Circuits and Systems Lab., Yonsei University15
Design Example
✓ Charge pump circuit
- Supply voltage: 1.8V
- Current of charge pump: 200uA ± 10uA
- Current mismatch: <150nA with range of Vcont larger than 0.8V
High-Speed Circuits and Systems Lab., Yonsei University16
Simulation Schematic– VCVS (OpAmp)
• Voltage gain : 1000
• Maximum output
voltage :1.8V
• Minimum output voltage : 0V
– RC Filter of OpAmp
• Resistor : 1Kohm
• Capacitance : 1nF
– Replica circuit
• Charge pump size same
– Load
• Capacitance : 200pF
– Nbias
• Voltage : 0.9V
High-Speed Circuits and Systems Lab., Yonsei University17
NMOS Current
Vcont
ID
AM
P+ -
UP
Pbias
DOWN
Nbias
Vdd
Vss
Vss
Vdd
Cont
Mp1
Mp2
Mn1
Mn2
Mp1
Mp2
Mn1
Mn2
1.8V
(OFF)
1.8V
(ON)
High-Speed Circuits and Systems Lab., Yonsei University18
PMOS Current
Vcont
ID
– Change PMOS current though the feedback.
With FBWithout FB
AM
P+ -
UP
Pbias
DOWN
Nbias
Vdd
Vss
Vss
Vdd
Cont
Mp1
Mp2
Mn1
Mn2
Mp1
Mp2
Mn1
Mn2
0V
(ON)
0V
(OFF)
High-Speed Circuits and Systems Lab., Yonsei University19
NMOS & PMOS Current
Vcont
ID
Vcont : 0.9V
∆ ID: 0.03uA
Vcont : 0.5V
∆ ID: 0.09uA
Vcont : 1.3V
∆ ID: 0.12uA
NMOS currentPMOS current
– NMOS and PMOS currents are equalized through the feedback system.
AM
P+ -
UP
Pbias
DOWN
Nbias
Vdd
Vss
Vss
Vdd
Cont
Mp1
Mp2
Mn1
Mn2
Mp1
Mp2
Mn1
Mn2
0V
(ON)
1.8V
(ON)
High-Speed Circuits and Systems Lab., Yonsei University20
NMOS – PMOS Current
Vcont
Vcont : 0.9V
Icont: 0.03uA
Vcont : 0.5V
Icont: 0.08uA
Vcont : 1.3V
Icont: 0.12uA
Icont
With FB
Without FB
– NMOS and PMOS currents are equalized through the feedback system.
AM
P+ -
UP
Pbias
DOWN
Nbias
Vdd
Vss
Vss
Vdd
Cont
Mp1
Mp2
Mn1
Mn2
Mp1
Mp2
Mn1
Mn2
0V
(ON)
1.8V
(ON)
High-Speed Circuits and Systems Lab., Yonsei University21
✓ Design 500uA (±20uA) charge pump with replica circuit.
✓ Without replica circuit, verify and plot pmos and nmos current waveforms with
respect to cont voltage.
– Current mismatch : less than 60uA (cont voltage range : 0.5V ~ 1.3V)
✓ With replica circuit, verify and plot pmos and nmos current waveforms with
respect to cont voltage.
– Current mismatch : less than 400nA (cont voltage range : 0.5V ~ 1.3V)
✓ Charge pump specification
– VDD supply voltage : 1.8V
– Nbias voltage : 0.9V
– Charge pump current : 500uA (±20uA) at nbias voltage 0.9V
✓ Due: Next design class (Hardcopy)
High-Speed Circuits and Systems Lab., Yonsei University22
Homework
