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FUSE Demonstrator Document

Application Experiment 25886

Bournemouth University & Parker Hannifin plc, Digiplan

High Speed Data Bus for Motion Control :

ASIC extends high speed bus capability across product range

AE Abstract

High speed serial data bus for Motion Control

Digiplan, formed in 1969 as Digiplan Ltd. and later acquired by Parker Hannifin plc, has over 100 staff employedat Poole, England, in the design and manufacture of motion control products for the industrial automation markete.g. factory automation, pick and place, textile and handling machines. These products are sold direct to OEMsand via specialist distributors. Products include : low power stepper and servo drives, servo motors, motioncontrollers, PC software and power supplies. A typical system might consist of a controller together with one ormore drives and motors that would control the operation of a automatic lathe. Design of products usinganalogue, power, digital, micro-electronics and software is handled by a team of 9 electronic engineers. TheProdcom sector, Industrial Process Control, is 3330 in the classification widely used in the EU.In 1998 Digiplan had total sales of £7 million (10 million €).

The main objective of the AE was to broaden the range of products that could be networked using the existingHEDA protocol by removing the reliance of HEDA on the Motorola 56xxx family of digital signal processorsand doing this in a cost effective manner. Prior to the AE the only products that could, cost effectively, utilisethe HEDA bus were those which already included the Motorola DSP devices - and this precluded the steppermotor drives. The availability of the HEDA interface would result in a stepper motor product with a greatlyenhanced functionality, sales of which will result in an increase in company turnover. The product chosen at theoutset of the AE was the PDX packaged stepper Motor Drive. However, because of the development of a newrange of drives the first samples will actually be installed in this new product (known as Paragon).

Modern automation systems rely heavily on bus systems, like the HEDA bus, in order to control the variouselements within the system. However the stepper motor drives which form the core of Digiplan's product rangecould not easily or cost effectively be linked into such a system. This situation was affecting the sales of Digiplan'sstepper motor drives, but it was determined that if a cost effective method of including the bus could be found,then the result would be a significant increase in sales.

By developing an ASIC that could be configured to work on its own or with a DSP or a microprocessor, the AEopened up opportunities for HEDA to be applied to other automation components, such as digital and analogueI/O modules and simple Man-Machine Interfaces (MMIs).

The payback period is 14 months and assuming the ASIC has a life of 3 years or more, the ROI is 1334%. Thesecalculations are based on using the ASIC in stepper and servo drives only.

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The FUSE programme funded prototype cost s of 95k€ and Digiplan has invested a further 19,000€ in moreadvanced VHDL design tools. The total budget of 114K€ was used for the payback and ROI calculations,together with the cost of industrialisation. The project lasted 24 months (elapsed time).

Significant additional benefits arising from the new VHDL skills acquired from the AE, have enabled Digiplan todevelop the electronics for a range of new, compact, base and intelligent stepper drives in record time. With theaddition of the HEDA ASIC to the base drives, Digiplan will have a formidable stepper product range which willpenetrate markets previously only open to low power servo applications.

Keywords Motion Control, Digital ASIC, FPGA, FPGA Conversion, VHDL, Synthesis, communication, processcontrol.Signature 4 0410 555 0410 1 3330 2 33 UK

1. Company Name and Address

Parker Hannifin plc,Electro-mechanical division,Digiplan,21 Balena Close,Poole.Dorset. BH17 7DX. U.K.

1.1 Logo

θρσ1.2 Contact

Paul Brookes, Group Leader Microelectronics and Software.Tel 01202 506200Fax 01202 695750Web: www.parker-emd.comEmail : p.brookes@parker-emd.com

2. Company Size

The company is part of the Parker Hannifin group since 1987 and employs just over 100 people at the Digiplansite in Poole where it occupies 3 factory units : a design and development facility, manufacturing facility and anadministrative unit. In 1998 the Electromechanical division had sales of 39 million €. This included machine salesfrom the Offenburg location. Digiplan’s turnover was 10 million €. The Parker Hannifin Group operate on alarge number of industrial sectors such as automation, pneumatics and hydraulics,

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3. Company business description

The company designs, manufactures and markets components for industrial automation, (PRODCOM 3330Industrial Process Control Equipment) specifically :

• Servo motors• Servo drives• Stepper drives• Controller products• Electro-thrust cylinders (sales only)• Precision tables (sales only)

Products are sold direct to original equipment manufacturers (key accounts) or via Applied Technology Centres(ATCs) who are specialist distributors.

Parker Hannifin is a large multi-national company with engineering companies in several key industrial segments -for example automation, hydraulics, climate and industrial controls, aerospace, filtration and fluid connectors. TheElectro-Mechanical Division (EMD) is part of the Automation group of companies. This group consists of small/ medium sized businesses who operate autonomously with key targets set by the parent company. Technologytransfer between Parker companies is encouraged and throughout the HEDA project Digiplan has promoted thisnew technology within Parker.

At the Poole site, Digiplan operates a self contained operation in that design, manufacturing, sales, manufacturingas well as technical support are all based there. In addition some products from other companies within theDivision are also sold and supported by Digiplan enabling them to offer a complete motion control service. Alsowithin the Group are Hauser (in Germany) who specialise in large systems using, predominately brushless,Compumotor (in the USA) who specialise in the controllers for brushless DC drives

4. Company markets and competitive position at the start of the AE

Digiplan’s main motion control products are servo and stepper motor drives which are offered with or withoutcontrollers. Approximately half the business is in Europe, including the UK market, with the remainder beingmainly in the USA. Recently, Digiplan is finding more opportunities in Germany, a market where fieldbus isfrequently a requirement. All of Digiplan's drive products have the potential to use the HEDA interface, but it hasnot, until now, been an economically viable proposition to do so. Digiplan's original product portfolio consistedtotally of stepper motor drives but because of the power limitations within this class of motor they enlarged theportfolio to include brushless and brush DC servo drives. The market however for stepper motor drives stillexist because of the lower costs (although this is constantly under attack from the servo manufacturers), the easeof control and their ability to operate open loop (i.e. they do not require any position or speed feedback).

Digiplan's 1998 sales in the different drive classifications were 77% of sales of drives were stepper motors and23% for servo motors. However it should be noted that a number of the sales in the servo market would in factbe for "special" drives and therefore not appropriate for the HEDA interface. It can therefore be seen that theinability to incorporate HEDA into a stepper drive was a serious limitation on the potential market for theinterface.

4.1 Classification of stepper drives

There are two classifications of stepper drives that must be considered when comparing the stepper drive market.

Type ACheap and very low power stepper drives usually a made as single semiconductor device or power module. Mainlydeveloped and manufactured for very special applications within the high volume OEM market (inkjet printers,scanners etc).

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These will be manufactured by the equipment builder or end user themselves.

Type BStepper drives of higher power levels, better current control, often with a higher level functionality such asintegrated trajectory generation, program sequencing (PLC function), communication via RS232/RS485, fieldbus(CAN, Profibus), registration, synchronisation via HEDA. These may be rack card based or packaged. The higherfunctionality products are typically packaged and often used in single axis applications. The rack based productsare generally drive only devices with industry standard Step and Direction inputs. These are often used as part of amulti-axis solution perhaps with a single central controller (PC card based).

Recently, Digiplan has invented a new form factor that offers the low cost of rack based drives but without therack. The drives plug into a docking station which canbe mounted on a standard DIN rail. All of theconnections are made from the front i.e. unlike a rackbased system, there is no need for access from the rear.The system is easily expanded by connecting a newdocking station to the existing one(s). This is whereHEDA is ideal because with HEDA the serial busconnections between drives have been incorporatedinto the docking stations. This reduces the amount ofwiring that the customer needs to deal with as well asoffering great opportunities for synchronised control ofstepper motors.HEDA is therefore an integral part of the aggressivesales plan that Digiplan has for the new Paragon family.

4.2 Markets

The addressable market areas for Digiplan stepper drives (type B) are:• Handling• Robotics• Process automation• Packaging• Food processing• Printing and paper converting

For Parker Hannifin, Digiplan, the addressable European market for stepper drives is estimated to be 102M€ in1999.

Within this segment ( type B drives only ), this is how the competitors rank:

Company M€ Share#1 SIG Positec 29 28%#2 Phytron 8 8%#3 Warner 7 7%#4 Parker Hannifin 5 5%#5 RTA 5 5%#6 PacSi 4 4%#7 Crouzet 3 3%#8 Oriental Motors 3 3%#9 Zebotronics 2 2%#10 Stegmann 1 1%

Other 35 34%

The total turnover for drives in the addressable market (102M€) represents 260.000 axes within the low cost area(products such as Digiplan’s CD, SD and PARAGON drives) and 51.000 axes in the area of “convenient” drives(packaged drives as such as Digiplan’s PDX, PDFX). A typical price for a packaged drive is in the region of £650whilst that of an SD drive would be £250 per axis.

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4.3 European stepper drive manufacturersThe stepper drive manufacturers in Europe are summarised below:

Company Motors Drives CommentsACAL RackADILOG Systemtechnik M. Seiz Rack, OEM version, PC cardAEROTECH RackAPI PORTESCAP RackArsape S.A. RackASTROASSMANN Rack, multiple axesAxing AG Rack, packagedBAUR Rack, customisedBAUTZ Packaged, OEM versionBENDRICH Rack, 5-Phase, FBBODINECNC d.o.o. Rack, PC cardCROUZET RackDeltron AG Rack, packagedEC MOTION Rack + DIN rail, 5-PhaseELBAG PackagedEVER Rack, packaged, IP industrial motorsEW HOF PackagedFAULHABERForstner electronics RackHERZEL Rack, packaged, DIN rail, PC cardIME RackINFRATRON RackISEL Rack, OEM version, mechanicalI.V.B. PackagedKSE Kontakt-Systeme RackMACCON Rack, packaged, ATCMICROSTEP OEM versionMIDDEX Rack, STEBON distr.Minimotor SA Rack, OEM versionMOTRON Packaged, FBMS Mecatronic System AG Rack, packaged, mechanicalMSW PackagedNANOTEC RackNECKAR MOTORENNMB RackNovitronic AGORIENTAL MOTOR Rack, packaged, OEM version, 5-PhasePacific Scientific Rack, packaged, OEM version, FB, 2-, 3-. 5-

PhasenPARKER HANNIFIN Rack, packaged, DIN rail, FB, OEM version,

mechanicalPHYSIK INSTRUMENTE RackPHYTRON ELEKTRONIK Rack, packagedPOWERTRONICREGELTRONREGULACE-AUTOMATIZACE BORs.r.o.

Rack, packaged, OEM version

RMB RackRubran Electronics AG Rack, OEM version, packagedRTA SANYO Denki HändlerSAIA BURGESSSCHULTESCT Rack, packaged, customisedSELECTRON Rack, OEM version, DIN rail, FB (SIG)

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SERVOTECHNIKSIG POSITEC Rack, packaged, OEM version, DIN rail, FB, IP

industrial motors, mechanicalSonceboz SA Rack, OEM version, packagedSTEGMANN RackSTOCKER Packaged, FBSUPERIOR ELECTRICWARNER ELECTRIC Rack, packaged, OEM version, FB, mechanicalZEBOTRONICS Rack, packaged

Table 4.3

This list is not complete. Manufacturers such as Alzanti, SGS Thomson, Infranor, IMS, MDP Electronics, Baldor,Allen Bradley and IMS are not listed because of their low volume in this sector of the stepper drives market (typeB drives).

4.4 Technology used by Digiplan and competitors

Many of our competitors employ either off the shelf stepper motor controller semiconductors, or use discretelogic to generate commutation information. This is particularly common in the low cost, card based drives.Digiplan drives of this type (CD, SD) use GALs or small FPGAs.

For the higher functionality drives with integrated motion controllers on board, the technology used by ourcompetitors is nearly always a combination of micro-controller and FPGA or ASIC. Some drives use a DigitalSignal Processor and control current digitally. This involves an expensive set of A to D and D to A converters.Some competitors have made a mixed signal ASIC to cope with this function. The price of these drives makestheir market potential very limited because they compete with low cost servo motor drives which can offersignificant advantages when offered at the same price as a stepper system.

Technology Cost Typical form factor FeaturesGAL lowest rack card, small case basic half steppingDiscrete logic low rack card basic half steppingFPGA low/medium rack or packaged mini- or micro-steppingMicro-controller/FPGA

medium Packaged mini- or micro-stepping with indexing & fieldbus options

DSP highest Packaged Micro-stepping with indexing and resonancecontrol (damping) Field bus options

Table 4.4

4.4.1 Weaknesses of competitor drives

Many competitors using GALs and discrete logic to offer low functionality drives are finding that the market forthese drives is under threat from other drives employing FPGAs as these drives cost little extra to manufacture yetoffer increased features. The FPGA based drives can also be offered in smaller packages and offer better currentcontrol, higher resolutions and quieter motion. None of these simple drives have fieldbus options as normallyfieldbus is only found on drives with microcontrollers in them. This means that multi-axis solutions require manysets of step and direction signals to be routed back to the system controller.

4.4.2 Strengths of competitor drives

Some of our competitors are able to sell their more basic products at lower prices than ours. Some competitorproducts have many options and this can help them in the marketing battle.Fieldbus options are becoming more popular for multi-axis applications due to the reduced demands oninstallation wiring and fault finding. Many competitors offer CAN bus or their own bus system on their micro-controller based products.Our response has been to look at the complete installed system cost for customers using rack based products andto come up with ways of reducing the overall system cost without reducing margins.

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4.4.3 Strengths of Digiplan’s HEDA/Paragon approach.

Digiplan’s solution is to use the HEDA ASIC with a small FPGA to provide a stepper drive that accepts positioncommands via the HEDA fieldbus and thus offer end users a much simplified and lower cost route to multi-axisstepper control. Coupling this with the Paragon docking station concept, complex stepper systems can beconstructed with minimum wiring costs, much lower than any of our competitors can currently manage.

4.5 3 year sales history

Year Sales % relative to 1996 packaged + rack Packaged sales as % of total1996 100 491997 101 391998 91 37

There was a slow down in the automation market last year. Some of the smaller machine builders who takepackaged products struggled to sell machines and hence sales of packaged drives fell.Overall we have noticed a slow down in the sales of rack based products and a narrowing of the price differentialbetween the lowest cost packaged products and the basic rack based products. Paragon is designed to offer thetechnological advantages that many packaged products have coupled with the economies of multi-axis rack basedproducts, but with an ease of installation that few if any competitors can offer.

5. Product or Process to be improved

5.1 Application area

For a few years now, there has been a strong trend towards distributed intelligence in industrial plants, machines,automobile and even consumer/multimedia products. The advantages of distributed systems can mainly be foundin the reduced cost, the greater flexibility and the reduced maintenance and repair times.A basic part of a distributed system is the link between the components or nodes. With all components linkedtogether, it is possible to pass information from one component to another. In this way, even some mechanicalparts of machines may be replaced by electronics (e.g. an electronic gear).

For motor drives, a bus system enables the co-ordination of multiple axes and the link to a supervisory controller.Another trend is the rapid growth of the market for sensors and actuators with an integrated bus interface. (e.g.CAN bus, Interbus)

Most of the existing bus solutions offer only low bandwidth and relatively low transmission speed. (CAN bus runsat up to 1MBaud but typically at 500KBaud and often adds less than 5€s of cost). Other solutions have enoughbandwidth but are more expensive (Profibus can run at 12MBaud). Another drawback of most bus systems is thelack of support for deterministic real-time transfers. Therefore, they cannot guarantee to deliver a data packet in afixed time (CAN is especially bad at this).

For the co-ordination of multiple synchronous drives it is a basic requirement to have a bus protocol whichsupports an efficient way of transferring cyclic real-time data, like position requests or speed.

During the last few years the High Efficiency Data Access bus for drives (HEDA) has been developed. This newstandard, within Parker EMD, offers high bandwidth at low cost and is specially designed to support cyclic real-time data. It is also media independent, i.e. it can be connected by wire or optical fibre. At the start of theexperiment, the fibre optic connection had not been developed.

HEDA is used mainly for multi-axis robot controls and special purpose machine tools, for cutting etc. Successfulapplications in both these areas have been in operation for some time and are based on servo, but not stepper,drives. With Paragon we intend to widen the application of steppers by integrating the HEDA ASIC into the newstepper drives. This will be at a power level lower than the current servo offering and will therefore enhance ourproduct range rather than steal sales from another sector.

There are no harsh environmental requirements or special radiation hardened requirements placed on any of theHEDA based products. However, inside the drives, temperatures can be quite high and industrial specification

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parts (70°C) are often used in areas likely to be heated by other components. Electrical noise and distance betweendrives and controller mean that in some cases a communications medium other than electrical could improve dataintegrity.

5.2 Hardware requirements of the original methodHEDA used the SSI (Synchronous Serial Interface) peripheral of the Motorola MC56002 DSP (fig. 5.2.1) found inthe COMPAX digital servo drive (Fig 5.2.2) . Software routines written in MC56002 DSP assembly language,execute the HEDA protocol. Additionally, a small PCB containing the 4 wire HEDA bus device drivers is pluggedinto the digital servo drive controller in order to interface the HEDA bus to the outside world.The original HEDA system approach uses RS 485 with twisted pair screened copper cable for the 4 wire bus.Fibre-optic cable is preferred for the future as this eliminates the disadvantages of copper cable, which are signaldistortion, cross-talk and lack of immunity to external interference.The original HEDA interface is efficient and cost-effective because the functionality required is largely providedby the servo drive DSP, and additional components are only required for the physical layer of the communication(layer 1 ISO/OSI). However, this solution cannot be used with existing stepper drives, as these drives do notincorporate a DSP and the inclusion of a DSP plus associated A to D circuits would carry an unacceptable costpenalty. See table 4.4

DSP Core

SSI Host

Timer/CounterModule

ProgramMemory

DataMemory

Servo DriveElectronics

DSP56002

HEDA FUNCTION REQUIREMENTS

Existing HEDA requires the Synchronous Serial Interface (SSI). The DSP runs the HEDA algorithm and controls the servo electronics.

4 Wire (RS485)HEDA bus device

drivers

Figure 5.2.1 : Existing HEDA Implementation Using Motorola 56002 DSP

Fig 5.2.2 Compax drive Modules (with motor in foreground)

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5.3 HEDA Parameters and characteristics

High Efficiency Data Access (HEDA) bus capable of operating at in excess of 10Mbaud and can be used for thereal time acquisition and distribution of data between a variety of controllers and peripherals (such as drives andposition feedback devices). It is used for the transmission of cyclic real time data (such as position requests) andacyclic parameters (such as the status of inputs and outputs). It may also be used for the synchronisation with themachine controller, thus ensuring that all units can take real time data simultaneously.The protocol supports 18 axes of highly synchronised motion with another 250+ devices able to be connectedand communicated with asynchronously (useful for input / output functions, man machine interfaces etc).

5.4 Reasons for innovation

With the existing methodology, the cost effective use of HEDA is restricted to units already incorporating a DSPdevice. As has already been mentioned, since stepper motor drives do not incorporate a DSP device, thisprecluded 77% of Digiplan's drive sales. This was a serious impediment to its acceptance in the market, especiallyin areas where a mixture of drives (stepper and servo) together with other peripherals was being used.

The objective of the experiment was therefore to develop a digital ASIC so that the HEDA bus capability can beextended cost-effectively into a product not containing the MC56002 DSP e.g. stepper drives specifically PDX(Fig 5.4.1). This same ASIC would then be able to be applied to the whole gamut of drives together with otherunits such as Man Machine Interfaces (MMI) and digital I/O modules. The proposed HEDA ASIC would alsoenhance the existing functionality of the DSP-based servo drives through its support for the fibre optic dataformat and allow other non-DSP servo drives to offer HEDA bus capability, strengthening Digiplan’s marketshare.

Fig 5.4.1 - A PDX Drive

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To meet the requirement for a highly synchronised, large robust bus system, that could be used on a wider rangeof products, the following modifications to the HEDA bus were required:

• improved transfer rate of 10Mbits/s• addition of bit-info cyclic request mechanism for acyclic data exchange• inclusion of a robust fibre-optic interface option

To meet the requirement for a low cost solution, the following were proposed :• DSP independence i.e. stand alone HEDA peripheral I.C. (FPGA or ASIC)• ability to operate with a microprocessor/DSP or in a stand alone mode

The stand alone HEDA peripheral I.C. should implement the HEDA protocol and provide:• Digital Input/Output (I/O) capability• Additional functionality e.g. counter input for encoder feedback to allow for passive HEDA controlled

devices such as I/O modules and encoder interface modules

6.0 Description of the technical improvements

6.1 OSI Layer 1, physical layer improvements

The original HEDA system approach used RS 485 with twisted pair screened copper cable. Fibre-optic cable waspreferred for the improved version of HEDA as this eliminates the disadvantages of copper cable, which aresignal distortion, cross-talk and lack of immunity to external interference. The low cost solution requireddemanded that the number of fibre optic connections, and therefore the number information channels (previouslyclock and data), were to be minimised. It was possible to compress the clock and data information into only onechannel by using suitable compression/de-compression algorithms in the transmitter and receiver.

6.1.1 Channel codingFirst of all we evaluated some of the different methods of implementing the channel coding, i.e. combining clockand data into one bitstream, especially their efficiency with respect to the bandwidth used:

Method Efficiency DC-component Run LengthNRZ 100% 50% ∞NRZI 100% 50% ∞Manchester 50% 0% 14B5B+NRZI 80% 10% 3

The efficiency is defined to be the data bit rate divided by the signal baud rate. The run length gives informationabout the length of the largest possible sequence without change (edges).

Manchester coding is very inefficient. This means that high bandwidth is required which may not be available onwired links. For HEDA the NRZI-4B5B coding was proposed.

6.1.2 NRZI-4B5B coding

The NRZI-4B5B coding is a wide spread technique identified by a relatively high efficiency and well defined edgeprobability. By introducing redundancy at the channel coding, the error detection is simplified. Additionally, thereare symbols which can never occur in the transmitted data. These control symbols can be used as frame delimitersor as special commands. A drawback of the redundancy is the need for a 25% higher transmission rate to achievethe same information throughput as with NRZ coding. On the other hand, with NRZI-4B5B coding ac-coupledtransmitters and receivers may be used, which are cheaper than dc-coupled transceivers needed by a pure NRZ-system.

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6.1.3 Other requirements

Parameter ValueTransmission speed 5 Mbits/sBit duration 200nsSlot duration 50µsBits per slot 250 BitMedia electrical / optical

• only a small delay may be introduced by repeaters in a ring configuration• master and slave must use the same hardware: hardware has to be configurable for master or slave operation• bus and ring topology needed (electrical/optical)• information transfer from one slave to another has to be done in 1ms or less• transmit and receive at the same time: duplex

6.2 Solution adopted

To achieve the above requirements using only software running on a microprocessor or DSP fitted with aSynchronous Serial Interface (SSI), as in the case of the original HEDA, would not have been possible.It was clear that the solution would involve hardware to combine the clock and data channels using the chosenNRZI 4B5B scheme and that to achieve minimal delays in the repeaters required by the ring networkconfiguration, this hardware would have to be quite high speed.Our experience with low cost design led us to believe that only ASIC or FPGA technologies would offer the rightbalance between speed and size. The cost argument could only be estimated until the gate size was known forcertain, but the initial volume predictions and gate count estimate favoured the ASIC approach. (See section 7 forrationale). Final gate count stands at 26000 gates, over double the original estimate.The ASIC is in fact implemented in a Thesys THA1008 Array which utilises a 0.8µm CMOS process with 2 layersof metal. The ASIC has a clock speed of 40MHz, which is four times the maximum proposed baud rate - thisallows the digital PLL to recover a 10MHz clock. The final ASIC used 27325 gates of the 27500 that wereavailable (e.g. 99.36%)All of the above requirements have been met and this gives HEDA a technical edge over rival fieldbus standards.Digiplan products will therefore have all the advantages of HEDA for about the same cost adder as for addingCAN bus, currently about the cheapest fieldbus on offer.

HE

DA

Por

t Bitinfo

ChannelCODEC

FrameController

Bus CycleController

MP

U In

terf

ace

& R

egis

ters

Par

alle

l Por

tS

SI

Clock

Rx

Tx

Sync

ModA,B,C,D

Xtal

EXtal

SFSyncSCLKSTDSRD

D[0..15]

A[0..4]IRQ\, ACKCS\Rd\, Wr\, BHEN

RCO

TCO

RESET

StatusLED

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Figure 6.21 Block diagram of HEDA ASIC

With the parallel asynchronous port, the HEDA ASIC can be connected to any standard microcontroller bus(Intel/Motorola). The data bus of this port is 16 bits wide but may also be configured to work with an 8 bit bus.The address bus is only five bits wide and has an additional chip select (CS) pin. Thus the ASIC has 32 registerswhich can be directly accessed by a CPU.

Additionally, a Synchronous Serial Interface (SSI) to a 56xxx family DSP has been provided. This co-operates withthe 563xx DMA to automatically transfer register contents to and from the CPU memory. This is a veryimportant point because it means that the ASIC can transfer data to the DSP via the SSI, without interrupting theDSP processing, thus maximising the available processing power for control applications.

When the ASIC is running in stand-alone mode, the pins d[0..15] are used as a parallel data port. These pins aremapped to the first word (A0) of an acyclic frame addressed to the node. The IRQ output may be used as a datastrobe. The transmitted word A1 (data direction) is valid for the next acyclic frame. For the first frame and afterreset, all pins are regarded as inputs.

The ASIC also has mode pins (Mod A, B, C D) to enable the various modes of operation to be selected.Specifically this enables the ASIC to operate in a ring or bus mode, to be a stand alone unit or to work with an 8bit or 16 bit processor, and for the processor type to be selected (8051, 56k, 21k, or 68k).

The Status signal has an 8mA driver instead of the normal 4mA capability and is used to drive an LED. Itindicates the status of the chip. If there is a communications error (CRC or Sync), the LED is switched off for atleast 128mS. For debugging of large networks, it is then easy to spot where errors are seen.

It was important to choose a technology offering fast gates to meet the requirements for bus timing of modernDSPs or controllers without the need for inserting wait states.

Figure 6.2.2 is a photograph of the prototype PCB, on which can clearly be seen the FPGA (the large chip in themiddle) which was used to emulate the ASIC and to prove its functionality. The board was created as a test unitand incorporated provision for several different fibre optic connectors in order to be able to evaluate differentmanufacturers products. The various fibre optic connectors are at the top right of the board, whilst the RS485connections are situated on the top left. To the right of the FPGA is the DSP device to enable the interfacebetween the two to be evaluated. The connector at the bottom of the assembly is to enable alternative processorsto be interfaced to the FPGA. The number of I/O pins available meant that for one application (e.g. the DSPinterface evaluation) the pins linked to the DSP could be used in the layout phase, and for another device the pinsconnected to the connector could be used.

Fig 6.2.2 Prototype evaluation board assembly

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6.3 Important advantages that the new ASIC offers.

Physical SizeThe small physical size will lead to smaller end products (TQFP64 package has a footprint of 144mm2).Alternative solutions would take up nearly 2000mm2.

Increased featuresThe ASIC has allowed us to provide an enhanced feature set and enhanced performance at an acceptable cost.This has opened up opportunities in new market areas that we didn’t previously have providing us with a distinctcompetitive edge compared with other stepper drive manufacturers. Specifically we can integrate HEDA intostepper drives without needing a micro and this is something our competitors cannot currently do with theirfieldbus solutions. This will give us a cheaper fieldbus offering.

Manufacturing CostsManufacturing placement machine time is reduced and hence manufacturing throughput is greater. On the otherhand, the fine pitch nature of the chosen package (a requirement stemming from the desire to reduce the size ofproducts) has meant that an expensive upgrade was required to the surface mount placement machine. If the onlyfine pitch (<0.65mm) part we used was the ASIC, the upgrade to the surface mount machine would not have beenviable. An assisted hand placement machine becomes a far more cost effective solution in this case, providingadequate throughput can be maintained.

Stock ControlStock control is simplified compared to the discrete alternative, because there is just one component to procureand stock instead of several. Magazine space on the surface mount machine is another issue as, in general, it ispreferential to use a rationalised range of surface mount components in order to minimise the set up time of themachine between different manufacturing runs. Having one component instead of several is a clear advantage inthis context and something Digiplan has successfully implemented for a number of years.

Cost of TestManufacturing test has fewer components to test and this narrows down the fault finding exercise, increasingthroughput because of the reduced number of nodes. On the other hand there are often high density areas of testpoints on PCBs containing ASICs and this complicates fixture manufacture. The fine pitch nature of the ASICalso required the use of TESTJET, a capacitive plate which has to be incorporated into the fixture lid so thatwhen a PCB is being tested, the fragile pin connections can be verified as even slight bowing of the PCB can leadto broken joints. Also many nodes that would be available to probe on discrete designs are simply not availableon ASICs without investing in scan path or JTAG test equipment, which at present is one step too many toimplement for one product range.

PCB DesignThe new designs using the ASIC benefit from using just one component instead of many. The hardware and PCBdesign is thus simplified. Design verification time is reduced as the ASIC becomes a proven component.

Power ConsumptionPower consumption of the ASIC is lower than the discrete alternative and whilst the difference is not great, beingin the order of 500mW, there is a useful saving made in an 8 axis system (4W). There will also be less of a heatingeffect within the drive enclosure, meaning that the power electronics can operate for longer before reaching theambient thermal performance limits.

7 Choices & rationale for the selected technologies, tools & methodologies.

In selecting the most appropriate technology, tool and methodology, Digiplan had to ensure that the decisionreached was an economically viable one both in terms of end unit cost and development cost. In order to do thiswe used both our own knowledge in terms of the market and product requirements, the experience of our TTN interms of the available technologies and tools, and the experience of potential suppliers. A requirementsspecification was first created and this was used to create an implementation specification that enabled thedecision making process to begin. The process was of course an iterative one in order to ascertain that theproposed solutions were acceptable and could be implemented by Digiplan.

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7.1 Technology optionsThe HEDA chip is a digital design with no particularly advanced performance requirements. The requiredfunctionality could, in principle, be met by implementing the design either in one or more FPGAs, or in a mask-programmed Gate Array, or in a semi-custom ASIC using a standard cell library. A low cost DSP could simply notperform the data manipulation or digital phase locked loop functions that is so easy with an FPGA or ASICsolution. Likewise, there were no suitable micro-controllers for this task.

A good choice of technology for HEDA may be defined, in order of importance, as one which:• leads to a low piece cost even at relatively low volumes (~5K)• recovers NRE costs in less than 3 years preferably less than 24 months• has a host product life span long enough to recover the NRE• is available in suitably small packaging• offers a relatively fast time to market• offers a second source for the IC

7.1.1 Gate Count

The anticipated size of the HEDA design was around 10K gates. Given this and the fact that the design tools usedsupported Xilinx, Lucent and Altera FPGAs, we considered the cost and timescale benefits of using FPGAs.It is important to note that this is a very critical estimation and if there are any doubts about the specification ofthe chip then estimate high! We did not do this and were lucky that our supplier still managed to come out withcompetitive prices for the final design (26,000 gates).

7.1.2 Possible FPGA solutions

FPGAs from Xilinx and Altera were considered suitable for the HEDA design, due to the design support offeredby the CAE tools used. Of these the Altera parts came out competitively priced and it was theEPF10K10ATC144-4 part that was chosen for the cost comparisons.

EPF10K10ATC144-4 5K 10K 25KPrice (€) 11.96 10.35 9.74

7.1.3 The ASIC Route

Multi-project route

The most competitive quote came from Thesys. The minimum order quantity was a very attractive 5000 pieces.Thesys’s quote for Multi Project Wafer (MPW) run and then conversion to production breaks down as follows:

Checking, Synthesis and MPW run with 10 samples 8250 ECUConversion to full production ASIC 12500 ECUScanpattern generation 2500 ECUTotal NRE costs for MPW, then production ASICs 23250 ECU

Piece cost based on Thesys THA8024 = 4.33 ECU @5K pieces or 3.38ECU @10K pieces.

Assuming a recovery period of 24 months, and an annual purchase of 5000 pieces, this means during the first 24months the effective piece cost of the ASIC is (23250/10000)+4.33 = 6.65€.

The conservative predicted usage figures suggest we would use only 7500 pieces over the first two years, but theterms of supply indicate we would purchase 10000.

Direct to ASIC route

Checking, Synthesis and ASIC production run with 10 samples 18000€Scanpattern generation 2500€Total NRE costs 20500€

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Piece cost based on Thesys THA8024 = 4.33€ @5K pieces or 3.38€ @10K pieces.

Assuming a recovery period of 24 months, and an annual purchase of 5000 pieces, this means during the first 24months the cost of the ASIC to us is (20500/10000)+4.33 = 6.38€.

The conservative predicted usage figures suggest we would use only 7500 pieces over the first two years, but theterms of supply indicate we would purchase 10000.

Breaking Even

The worst case NRE (MPW + conversion) is 23250€.

The point at which ASIC becomes cheaper than FPGA is given by the equation:23250 + 4.33N = 11.96N, where N = the break even quantity

Solving this, gives N=3047 pieces, which given usage chart 2 fig 7.1.4 (the expected usage) means an NRErecovery time frame of just under 1 year and two months. Even considering usage chart 1 (worst case) the time toreach the same point is 1 year 4 months.

Summary of quotation received from Thesys Advanced Electronics (prices converted from DM).

Target Technology 0.8 MicronGate Count 24360Usable Gates 9744Prototype Packaging CQFP64Production Packaging PQFP64NRE For MPW 8250€NRE For Production ASIC 15000€5000 Piece Cost 4.33€10000 Piece Cost 3.38€25000 Piece Cost 2.93€Prototype Leadtime 12 WeeksProduction Leadtime 13 Weeks

7.1.4 Predicted Usage Charts

Usage Chart 1 : Worst Case

0

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Usage Chart 2 : Expected Usage

010002000300040005000600070008000

FY99 FY2000 FY2001

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Figure 7.1.47.1.5 Breakeven Charts

The following charts represent a comparison of ASIC and FPGA pricing taking into account the appropriateNRE. The term “breakeven” in this context has no relation to revenue generated, as the argument is to justify thedecision to choose the ASIC as the preferred design methodology.

FPGA v ASIC Breakeven Based on Usage Chart 1

0

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Figure 7.1.5 a

For both cases (low usage and expected usage), the point at which the NRE costs of the ASIC are recoveredcompared the FPGA with zero NRE, is within the first 18 months of production. Both graphs assume that theminimum ASIC order quantity is purchased each time an order is required. In both cases, the predicated first yearusage is less than the minimum order quantity of the ASIC (5000 pieces) so the graphs of expenditure reflect thequantity purchased each fiscal year..

Note : The effect of having to buy more ASICs in the first year than are needed, is to move the point at whichNRE costs are recovered by approximately 3 months as indicated by the graph below, which shows the crossoverpoint at about 1 year and 5 months, which was still very acceptable for Digiplan. Some stock would be built upand this would need storage and adversely impact the working capital of the business. Companies with poor cashflow may not consider this option.

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FPGA v ASIC Breakeven Based on Usage Chart 2

0

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Figure 7.1.5b

7.1.4 Conclusions

The life span of modern electronic components is obviously a key factor in deciding how many years one canafford to recover NRE costs over.The anticipated life span of the HEDA ASIC is in excess of three years. However, it is Digiplan’s preference thatcosts are recovered within 2 years.Given the very competitive nature of the Stepper drive market, the lowest possible component cost adder is vitalwhen adding additional ICs to Stepper drives. Package size is another important consideration.

The FPGAs offer great flexibility in that they can be re-programmed if errors are discovered in the design once ithits volume production. However, at the relatively high prices charged for these FPGAs, the resulting Stepperdrives would not be competitive. The FPGA route for development looks useful as hardware test platforms canbe made without the need to wait for the ASIC.

The ASIC route is however, very attractive. The low cost for production parts coupled with the relatively lowNRE means that NRE recovery within 2 years leads to a piece price of 5.88€, under half the cost of the FPGAsolution and a considerable saving on the existing DSP based method.

Going straight to ASIC without an MPW run increases risk and only saves 0.27€ per part. However, the benefitsof having the parts sooner, may help raise the volumes, realising a further piece cost reduction.

7.1.5 The Choice

The chosen route was, however, MPW ASIC followed by production ASIC as this offered low risk in that theMPW run proves the design first . The cost must be acceptable to the Stepper drives and competitive to theexisting DSP approach in the Servo drives.

7.2 Design approach

In order to maintain control of what was inevitably going to be a large project, and facilitate the team approachthat Digiplan had effectively used for many years it was essential that the project could be partitioned intomanageable blocks and that these blocks could be implemented by different members of the team.

With the aid of the TTN it was therefore determined that the use of an HDL followed by synthesis wouldfacilitate this mode of design whereas the use of "traditional" schematic design would result in unwieldy problemswhen attempting to integrate modules designed by different personnel.

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7.2.1 VHDL designDigiplan’s design approach was to develop the design specification using VHDL in order to provide technology-independence, and then to use logic synthesis to target onto the selected technology. This permitted thefunctionality of the design hardware and communication algorithms to be verified and refined by implementingthe design initially in an FPGA.

The chosen tools were from VeriBest and included a VHDL editor, compiler and simulator.FPGA synthesis was handled by Synopsis FPGA Express. Veribest was chosen primarily because Parker werealready a user of Intergraph software and were able to use their purchasing power to obtain advantageous pricing.The decision was made after carefully examining the options (Viewlogic, Orcad as well as Veribest), but it was feltthat the use of an existing supplier together with a set of tools that had a similarity to existing software was anoverwhelming consideration in what is a market populated by suppliers of similar products.

A test board containing an Altera Flex 10K50 FPGA, Motorola 56300 DSP, various fibre-optic and RS422 drivercomponents was designed and made so that code could be tested out on the FPGA to verify the simulation andsynthesis process - see Figure 6.2.3.

7.2.2 Test methodsThis was an interesting area. The idea of boundary scan test circuits on the final ASIC was attractive because ofour desire to have reliably tested parts arriving at our factory. The amount of fault coverage is directly linked tohow much time is spent on considering testability. For a First User of this technology the testability issue wassecondary in our minds because of the all the other issues we were having to deal with. We therefore decided thatwe’d like to include scan path testing by replacing flip flops in the final design with scan enabled equivalents fromthe ASIC cell library. This would be a sub-contracted task and the costs were considered in the ASIC justification.

8 Expertise and experience of staff involved

8.1 General expertiseDigiplan has substantial experience of designing stepper, brushed servo and brushless servo drives, controllers,and brushless servo motors. The drives currently use a variety of GALs, PALs and FPGAs in their controlcircuits. There is also expertise in PCB design, microprocessors, software and PCB assembly using conventionaland surface mounted components.

Digiplan currently employs 9 electronic design engineers. At the Offenburg location there are 10 electronic designengineers. One engineer was made available to the Poole location for part of the development phase of theproject.

8.2 Microelectronics expertise

Digiplan did not have any development engineers with ASIC design experience at the start of the project but hadengineers with considerable experience in designing circuits with a variety of programmable logic device types,such as GALs, PALs, and more recently FPGAs.

8.2.1 Team members

Our Senior Power Electronics Design Engineer, has several years experience using ACTEL FPGAs designedusing schematic entry methods. His background is in analogue and power electronics. He has formal training in Cand is very PC literate. He also is used to project management.

The Design Manager for Microelectronics and Software, has over 9 years experience designing with FPGAs. Hewrites embedded software and has worked on various Motorola processors. He has some recent departmentalmanagement experience as well as project leader experience.

A graduate engineer working on an engineering exchange scheme within Parker Hannifin. His Universityexperience in fibre optic communications proved very useful. He had also had some exposure to VHDL duringhis degree course.

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Our Microprocessor Development Engineer has some limited ACTEL FPGA experience. He has worked onspecial systems based around a variety of microprocessors and specialises in writing embedded software in the ‘C’language. He also has project leader experience.

8.2.2 Summary of team experience

Microelectronic experience was not a problem as 2 team members had plenty of experience with interfacingmicroprocessors to large peripheral devices.

FPGA concepts and design tools presented no problems for the team. The only difference was that an AlteraSRAM based device had been chosen for the HEDA development test platform. This meant learning a newsoftware tool.

3 team members have experience with project management and all are used to team working.

Communications experience was more limited relying on the graduate engineer for his fibre optic knowledge and2 other team members for their protocol knowledge.

8.3 Training needs

From the above descriptions it is easy to notice that none of the engineers had had any practical experience ofusing VHDL. Only one had had any formal training. Therefore, we considered VHDL training as an essential pre-requisite.

ASIC project management was an area where the team felt that we were generally comfortable, but wanted to geta feel for the overall design flow particularly at the point where the design is transferred to the ASICsubcontractor. So a minor training need was identified here.

Testability issues were not something normally considered in our previous FPGA designs and therefore this wasanother area where there was a training need.

9.0 Workplan and rationale

The workplan was conceived with the assistance of the TTN, and additional input from the major subcontractorsin order to establish an acceptable timeframe and an acceptable division of roles and responsibilities. Havingalready determined that an FPGA emulation of the ASIC was the preferred route, the requirements of thesubcontractor could be integrated into the overall workplan. One pre-requisite that Digiplan had was the need tocarry out the design work in house, and to only use the sub-contractor for the conversion of the FPGA design toa gate array. This was because it was essential to be able to prove the functionality of the HEDA ASIC and to beable to provide samples to potential users and therefore be able to integrate both their needs and their feedbackinto the device prior to it being manufactured. This did increase the workload on the staff at Digiplan, butensured that the technology was thoroughly acquired (the effectiveness of this can be seen from the fact othersuccessful projects using the technology have already been completed) and that the resultant device fully meetsthat requirements of Digiplan and other potential users.

The workplan and in particular the training requirements were created taking into account the existing skills andexperience of the staff involved.

9.1 Original workplan

The development plan was divided into six task blocks plus a training programme. Extensive early testing of thecommunication protocols and the applied algorithms are a deliberate part of the project plan. This served toincrease confidence during the subsequent ASIC design and avoid time consuming re-design. i.e. this is riskreduction.

SpecificationsDetailed specifications of HEDA communications utilising optical transmission media were established. Detaileddetermination of the protocol had to include a concrete decision regarding coding, data rate, etc. as well as theevaluation of different concepts for the appropriate drivers (electronic, optical). This was a low risk activity, given

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Digiplan’s existing technical competencies since at this stage the specification is a requirements specification anddid not have any implementation specific attributes.

Who Planned effort Planned cost DeliverableDigiplan 12 man weeks 9.5K€ Specifications

System DesignThe protocol specified in the first task block was developed, then embedded in hardware by means of an FPGAand then tested. To this end a PCB, including all required components, was developed to communicate on the onehand with a control processor and on the other hand with the driver building blocks for electronic and opticaltransmission media. This task block was divided into three sub-tasks, program development, PCB developmentand FPGA generation. Training on project management, ASIC technology and VHDL implementation in months1 and 2 reduced the risk in this phase.

Who Planned effort Planned cost DeliverableSubcon 3 + Materials 2K€ PCBDigiplan 20 man weeks 16K€ Initial FPGA

Test of Communication ProtocolThe specified protocol was extensively tested with the help of the PCB and the programmed FPGAs. Thisrequired the assembly of at least three PCBs so that a test configuration (1 master / 2 slaves) can be generated. Asoftware program had to be developed that offered testing functionality for the individual test boards.If the tests revealed errors during the protocol run, they had to be identified and located. The error source couldbe eliminated quickly and easily by reprogramming the FPGAs, thus generating an optimised and reliablyfunctioning FPGA design and reducing the risk of failure.

Who Planned effort Planned cost DeliverableDigiplan 20 man weeks 16K€ Tested Protocol

Design of ASIC for Prototype UnitsIn this task block the tested design was converted from the FPGA basis to a digital ASIC. Besides implementationof the actual communication protocol, additional functions could now be designed around the core of theprotocol. These additional functions will give the HEDA ASIC a certain range of intelligence so that it may beutilised in a simple I/O bus device without the need for an additional microprocessor. Additional peripheralfunctions such as digital Inputs and Outputs, Up/down counters and an asynchronous/synchronous UARTInterface increase the device’s use in a range of products. The ASIC also has a flexible processor interface so that,as a peripheral building block, it will be capable of communication with as many different processors fromdifferent suppliers as possible.The design was simulated and linked to the library of the semiconductor supplier. The net list was then passed onto the semiconductor supplier for synthesis and ASIC production.

Who Planned effort Planned cost DeliverableSub 2 7.5K ASIC PrototypeDigiplan 28 man weeks 22.4K€ ASIC VHDL

Development of a HEDA-Interface BoardA printed circuit board was developed so that it could be used as a plug-in card for different automation products.This board includes a configurable processor interface as well as a plug for connection to the optical andelectronic bus. Central features of the board are the HEDA ASIC and the optical/electronic drivers. A HEDA kitalso features a basic collection of software drivers for easy connection of the HEDA-interface to differentprocessors and integration into existing products. The risk in this phase was low since the ASIC had been provenand Digiplan had well developed PCB design tools.

Who Planned effort Planned cost DeliverableSub 3 + Mat 2K€ PCBDigiplan 10 man weeks 8K€ Test PCB

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TrainingThe training appropriate for the programme is as follows:

Unit Title Duration Estimated Cost Actual Cost1 Project management (including the

management of ASIC projects)2 days 660€ 1 day

2 Introduction to ASIC technology 2 days 430€ notundertaken

3 Use of Viewlogic for ASICs 5 days 1075€ Part ofsoftware cost

4 VHDL training 10 days 2150€ 3623€5 Design for testability 5 days 1075€ 1087€6 Design support (during ASIC development) 7 days 1505€ included in

VHDLtraining

Total Training costs 6.9k ECUThe duration and cost of each course was confirmed by our TTN. It was Digiplan’s intention that more than 2engineers undertake the training, so that our knowledge-base is increased for future projects. In fact eightengineers attended the first two days of the course (Basic VHDL) and three of those engineers remained for thefinal three days. The time allowance for training is built into the work plan but the time spent by Digiplanengineers has not been charged.

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9.2 A comparison of expected and actual labour used

First User SubcontractorTaskExpectedman days

Actualman days

Plannedcost

ActualCost

Comments

Specifications 60 64.25 Additional features were added and amendments whilstdeveloping led to most of the extra workload.There were more amendments due to more additional functionsand this arose because of getting other parties interested inHEDA.

Training 31 34 6.9k€ 3.6k€System Design 100 119 This task was to produce the HEDA function in VHDL and target

this for an FPGA in order to get confidence in the VHDL model.Development of VHDL model 74 97 Despite being new to VHDL we found it very easy to design with.

The most difficult aspects are when synthesising the code for thetarget architecture. Some code that simulates fine, will just notsynthesise and this can bring long delays whilst learning how toadjust one’s coding style for the target architecture.

PCB development 21 14 This went better than planned which is unusual for PCBdevelopments!

FPGA Generation 5 8 We did the FPGA synthesis incrementally as we developed theVHDL, but the first time we had to actually target the FPGA withthe Altera tools, we had to spend extra time learning how tooptimally fit our design into the FPGA. This took us longer thanwe originally estimated.

Test of communicationsprotocol

100 135.5 We seriously underestimated this task. In actual fact we spentconsiderably longer than the time booked to the AE because weused some spare resource to assist with the big system tests (webuilt 6 test boards in total and connected them in differentconfigurations). If we had to plan this again we’d allow 40 manweeks of effort not 20.

Design of ASIC for prototypeunits

140 181 7.5k€ Not yetincurred

This stage included adding the additional functions beyond thepure HEDA communications protocol. Originally we estimatedthat we would have some simple AFs, but ended up with manymore because we persuaded other companies to use HEDA andthey needed small additional functions like and IIC bus forDAC/ADC connection and an encoder port for feedback devicesWe have the ASIC timing model currently and after checking thiswe found an error which we have corrected. The subcontractor isre -synthesising the new design.

Development of HEDAinterface PCB including ASICtesting

50 50 This PCB has not been completed at the time of writing but theoriginal estimate of 50 man days looks quite accurate.

Summary of tasks and labour

Below is a much simplified view of the different sections of the plan. The grey bars represent the planned workperiods and the black bars represent the actual work periods.The deliverables, the expected dates and actual dates are shown in the next section.

There was contingency in this plan to allow for the unexpected in that we had some extra test resource available touse if required. However, we did not have any extra design resource and felt more comfortable with reducing thepace of development than getting in design contractors should design resource become a problem (as it did).

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9.3 Actual workplan

Business needs change and between the submission of the FUSE proposal, subsequent re-working of the proposaland final acceptance around 9 months passed by.

Looking back at the performance of the market for industrial motion and control products over the last 2 years,one notices a marked slow down around the end of 1997. This coincided with the period where our applicationexperiment was getting started.

Poor specification is often a key cause of delays in projects. As we already had a HEDA specification, it was arelatively easy task to review this and specify the additional improvements. Hence the first part of our plan wentwell.

The training was made later than planned due to a postponed start date and availability of all concerned.

Good progress was made, however, on the system design phase, despite the lack of familiarity with the tools andVHDL.

Our project ran quite nicely to plan until a business decision was made to give engineering priority to thedevelopment of the base and indexer Paragon drives. This meant putting in the system level components ofHEDA ( allowing for the routing of the HEDA bus signals) but delaying the ASIC development until the driveswere designed.

We therefore ran past the original 12 month project deadline and had an approved extension of 3 months. By theend of this time we could have made the ASIC - the VHDL was complete and tested. However, the ASIC gatecount had grown from the estimated 10000 gates to just over 20000 gates and we needed to increase the volumeto keep the economics of the ASIC viable. This is why we looked to persuade other Parker companies to adoptHEDA as a standard fieldbus within other Parker products. This meant that we had to accommodate someadditional features in the ASIC which despite increasing the gate count, would actually reduce the cost of theASIC due to the significant additional volume.

For the record, here is the list of key deliverables from the original proposal and the date that each deliverable wasrecorded as complete.

Deliverable Name Due Date Date AchievedProject Started 15/09/97

D7 Deliver HEDA Function Block Specification 12/09/97 03/10/97D42 Deliver Specification of Additional Function Block 31/10/97 07/11/97D17 Deliver VHDL Source for HEDA Function Block 07/11/97 07/11/97D29 Deliver Approved Test Specifications 28/11/97 23/01/98D44 Deliver VHDL Source for Additional Function Block 05/12/97 26/01/98D25 Deliver System Test PCB 19/12/97 03/02/98D26 Deliver Untested VHDL Source for FPGA Proving 19/12/97 06/02/98D39 Deliver Tested VHDL Source to ASIC Supplier 06/03/98 June 1999D65 Deliver System Test PCB 22/05/98 Expect Oct’99D59 Prototype ASICs Delivered 12/06/98 Expect Nov’ 991D2 Experiment Flyer June 19981D5 Demonstrator Document June/July 1998 September 19991D3 Presentation TBA

From this it can be seen that we did the majority of the work in the planned timescale. The main delays were dueto business needs dictating that other developments should take priority. Also the additional functionality grewand led to additional work, additional delays and reduction in the funding available to claim because the projectover-ran the contracted period.

9.4 Role of subcontractors

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Subcontractors were required in two key areas - firstly for the initial training in VHDL and synthesis and then forthe actual production of the ASIC.

Subcontractor Name Role Estimated Cost Actual CostBournemouth University Training 6.9k€ 3.6k€Thesys ASIC Manufacture 7.5k€ Not yet incurred

9.5 Knowledge Transfer Process

The knowledge transfer process had two main strands to it -1) The initial training - both that which was received from Bournemouth University and the self training that was

undertaken. These enabled a positive start to be made to the design, and was assisted by the "team" operationin that the members were able to assist each other. A single engineer working on a new design methodology(e.g. VHDL and synthesis) can feel in total isolation, whereas the synergy that develops within a team canenable the individuals to make faster progress than if they were working as individuals.

2) The discussions with the ASIC manufacturer - a necessary pre-requisite for the manufacture of the ASIC was athorough understanding of the design and manufacturing process and a number of meetings were made withThesys in order to ensure that the design team were familiar with the requirements of the potential targetprocess. A number of such meetings took place, and although a personnel change occurred at thesubcontractor this has not had as detrimental an effect as it might have done. The large size of the ParkerHannifin Corporation makes them an attractive customer and this may well have influenced the relationship.At one point the subcontractor offered to synthesise the VHDL descriptions rather than carrying out a netlistconversion, and this was attractive because it would have enabled a comparison to be made between the twotechniques (net list conversion and VHDL description synthesis) and might have resulted in a smaller arraybeing required. However this offer was never repeated and in the end the complete netlist was sent to thesubcontractor for re-targeting who preferred this route.

9.6 Risk Analysis

In essence, the risk analysis identified the core areas for concern and in addition identified methodologies thatwould minimise and control those risks. It was realised at the outset that the creation of an ASIC is a "risky"project.

Areas for concern included the following major items :-1. Has the correct technology been chosen?2. Can the design be proven before the commitment to silicon is made?3. Can the design be partitioned such that the team can share the design effort?4. In the event that the design is partitioned, how can we be sure that the integration process will work?5. How can we control the subcontractors - particularly when they are some distance away?

In order to minimise the risks, Digiplan had extensive discussions with their TTN and the following strategy wasadopted:-1) The use of VHDL and simulation.

This had a number of benefits, firstly the target destination did not have to be decided until the design wascomplete. Thus this decision could take into account the final gate count, the necessary operating speed, theup to date estimate of the number of devices required, as well as the status of the potential suppliers at thattime. Secondly it enabled the operation of the device to be simulated and therefore verified at all stages of thedesign.

2) The use of synthesisThis also enabled the target device to be determined late in the design cycle and gave the option of trying anumber of different targets should this be felt to be necessary.

3) The use of an FPGA to emulate the designThis was an extremely powerful "tool" since it enabled the actual operation of the final ASIC to be emulatedin a manner that would be close to the final implementation. Thus the various modes of operation could beverified, and the additional features that had been added could also be verified. In addition sample devicescould be supplied to potential users within the division in order that they too could verify the operation and,

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in particular, verify the features that they had specifically requested. All this being carried out prior tocommitting to an ASIC.

4) The establishment of a rigid project management structure, that controlled the team operation whilstremaining flexible enough to be able to respond to the commercial demands of the company. Regular teammeetings were held in order to assess progress, and regular meetings were also held with the TTN in order togain the benefit of an external appraisal of progress.

5) Use of a proven subcontractor, and the utilisation of the FUSE network to assess other FUs confidence inand experiences of the subcontractor.

The aim of the risk analysis was to identify the risk and to determine a strategy to minimise the risks. Intrinsic inthis strategy was also a mechanism whereby, should a problem arise, the occurrence would be identified (via themanagement structure and review meetings) and a plan devised to overcome the problem.

10 Subcontractors

The selection process for the subcontractor required the identification of potential suppliers and then anevaluation of their suitability in order to identify the most appropriate organisation.

The following were identified as the main criteria in each case:-

Task CriteriaTraining • Ability to deliver appropriate material

• Experience in the relative disciplines• Ability to adapt material to meet Digiplan's specific needs

ASIC supply • Availability of appropriate technologies• Proven record of supply• Ability to communicate requirements to "first time users"• Flexibility to respond to Digiplan's needs• Acceptable cost structure• Confidentiality and respect for Digiplan's IPR

The following sub-contractors were deemed to meet the requirements and the resultant relationships have, todate, proved those decisions to be correct.

Sub-contractor 1 Training - Bournemouth University is both a TTN for the FUSE programme and aMicroelectronics in Business Centre in the UK, with extensive experience in the delivery of training for ASICprojects.

Sub-contractor 2 Silicon Foundry - Thesys, is a semiconductor manufacturer with experience of more than 2000ASIC projects in digital and mixed signal applications. They have supplied ASICs to a sister Parker Division in thepast. They have been chosen because they undertake to manufacture lower volumes of ASICs than many othersuppliers whilst still maintaining a competitive piece part cost. The agreement with the subcontractor ensured thatthe Intellectual Property Rights (IPR ) of Digiplan were protected. It also laid down the roles and responsibilitiesof the subcontractor and Parker and established a stage payment structure.

Sub-contractor 3 PCB supplier - Lantrax- Digiplan has many years’ experience in dealing with a number of suppliers of bare PCBs for prototype

and production quantities.During the project Lantrax unfortunately went into receivership. However, through Digiplan’s vendor assessmentprogramme, a drop in quality and late delivery from Lantrax had been spotted and a new vendor found ahead ofLantrax’s closure. Prototype PCBs are generally sub-contracted to specialist, low volume manufacturers who offerhigh quality, fast turn around boards.

This last sub-contractor is mentioned, not because they contributed to the knowledge transfer process but becauseof the lesson that can be learned from monitoring both quality of supply and delivery times. By doing this,Digiplan were able to avoid a potential problem.

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11 Barriers perceived by the company in the first use of the AE technology.

Prior to the AE the use of ASIC technology was considered. However, there were a number of reasons whyASICs had previously been ignored.

Quantity considerationsFinancial decisions are all relative and the amounts considered in looking at ASIC NREs were not deemed to be amajor risk to the future of the business. The primary considerations for Digiplan were the technical and marketingbenefits of using ASIC technology over the alternatives. We had considered converting some of our ACTELFPGA designs into ASICs but the cost difference was too marginal to justify the risks involved.

From a study of a couple of Parker companies that had used ASICs we were able to conclude, with our previousproduct lines (pre-HEDA), the following points :

• the use of FPGAs in our products was more economic than ASIC, given the volumes used (<5000 p.a.) andthe small gate counts (<2000)

• the nature of continuous product improvement means that we often revisited FPGA designs during a productlife span and with an ASIC approach at low volume this would have been too costly in terms of NRE, projectresource and time to market

• FPGA technology was reducing in cost and ASIC makers were concentrating more on larger devices drivenby the communications and PC markets

• The small geometries used to keep ASICs cost effective meant that a very large number of small devices couldbe fitted onto one wafer and hence minimum order quantities could be very big indeed

• Conversely, where minimum order quantities were lower, the technology used was probably older (largergeometry) and therefore the piece cost was higher

• Our products could be designed without the need for ASICs i.e. the size and costs would still meet marketrequirements.

The last part is important. Some products demand the use of ASICs due to their complexity, size, target costs andvolumes (e.g. mobile telephones).The use of ASICs in motor drives is not essential. Several companies have chosen to use ASICs (ACS, Yaskawa,Control Techniques) but they are not direct competitors of ours in our core market areas. Many stepper drivemanufacturers use custom chips that became adopted by IC manufacturers such as Allegro, Unitrode and ST. Thistends to be at the really basic end of the market where the relatively crude current control or low power offered bythese parts, is all that is needed.

AwarenessIt was perceived at Digiplan that we could not justify the use of an ASIC in any of our products. Our knowledgeof the available technologies was extremely limited and we were of the opinion that our production volumes didnot create an economic justification for the use of an ASIC.

We didn’t have the expertise in house to develop an ASIC even if we wanted to do so. We did have a reasonableunderstanding in what was involved though. There was a lack of awareness of an ASIC process that would meetour needs, and this prevented Digiplan from implementing an ASIC project. Thus it can be seen that the majorbarrier was an awareness one, and that although barriers such as lack of expertise did exist, they were not ofsufficient size to hinder the adoption of the technology should that have been required.

None of our individual products really fell into the category where an ASIC would have been the right decisionbased solely on economics. However the identification of a "cross product" requirement (one which could beapplied to a large percentage of products in the Digiplan portfolio), in this case the inclusion of the HEDAinterface meant that whilst no one single product might justify an ASIC, the overall requirements were more thansufficient.

12 Steps taken to overcome the barriers and arrive at an improved product

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As already defined, the principle barriers were identifying the requirement for an ASIC, and being aware of anappropriate ASIC technology.

ASIC RequirementFor many years, our technology requirements called for 2000 gates maximum. Unless we could find a high volumeproduct which would be stable for long enough to recover the NRE, we wouldn’t benefit from using ASICsinstead of FPGAs.

We didn’t find such a product. Instead we had a requirement for a feature that required either a DSP or a muchbigger FPGA. The FPGA solution meant that a wider range of products could have this new HEDA feature. TheASIC opportunity came about because we realised that the design met the following criteria:• the use of FPGAs to implement HEDA in our products was NOT more economic than ASIC approach,

given the volumes used (>5000 p.a.) and the gate count (>10000)• the HEDA technology was stable and in keeping with our commitment to continuous product improvement,

we were able to develop the old HEDA into a more feature packed version with increased application• FPGA technology was reducing in cost but at the 10K gate count the ASIC makers were still able to offer

some competitive pricing.• The proposed number of gates and ASIC technology choice meant that an acceptable minimum order

quantity and price were achievable• Our products could be designed without the need for ASICs, but the increased pressure on size reduction

coupled with the desire to expand the scope of HEDA beyond use in servo drives meant that the ASICapproach was viable.

We realised that to satisfy our new requirements that we really did need to use an ASIC and that other technologychoices were viable for prototyping but not for production where cost is an important consideration.

ASIC Process identificationAs we had no ASIC expertise we turned to the Department of Trade and Industry to find out what help wasavailable and after attending a microelectronics seminar, we were put in touch with our TTN in BournemouthUniversity who were also a Microelectronics in Business Support Centre. They were able to verify the feasibilityof the use of an ASIC, and also to identify a number of potential suppliers and assist with the selection of themost apposite source.It was after discussion with them that we realised that the help we needed could be found by doing a first userexperiment under the FUSE programme for which they were a Technology Transfer Node.

So the key steps we took were to:

• identify that an ASIC could be the right approach for us• contact the DTI and attend a microelectronics seminar (useful if you are not sure about the first step)• contact the TTN to discuss things in more detail• identify an appropriate process and supplier• submit a FUSE proposal in order to get the structured help and support available via the TTN network• identify and satisfy training requirements

13 Knowledge and experience acquired

13.1 trainingIn section 8.3 we discussed training needs. These were centred on:

• Learning VHDL• Learning about coding for synthesis as opposed to pure simulation• ASIC project management• Testability of ASICs• Learning the VeriBest VHDL tools• Learning how to use the Altera Max plus softwareThese needs were satisfied by a mixture of self learning (both before the project commencement and during theproject itself) and training provided by a subcontractor. What we did ahead of starting the FUSE project but after

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submitting the proposal, was to invest in a multi-media training package on VHDL. This cost around 150€s andwas supplied by VHDL specialist Doulos who are based in Ringwood in UK. The package was called Pacemakerand we found it to be an excellent introduction to VHDL terms, methodology and language. All of the designteam including those not directly involved with HEDA, were given the opportunity to use this training tool. Thisinsured a wide dispersion within the design team of the knowledge of the principles of VHDL

To supplement this, we planned a 5 day training course at the TTN. This involved both theoretical and practicalsessions. This training was the most critical element of the knowledge required. The breakdown of training was asfollows:• Basics of VHDL language• Coding in different styles• Tutorial exercises using a VHDL simulator• VHDL for synthesis• Advanced VHDL concepts• Tutorial exercises using simulation, synthesis and target hardware

2 months into the project we looked at testability issues and attended the following course at the TTN : “Designfor Testability”. This covered test methodologies for components, sub assemblies and systems as well as ASICs.We learnt about the usefulness of scan based test and also about the requirements for this and automatic testpattern generation (ATPG). We also realised that adding such circuitry can mean that the end design won’t fitinto the ASIC master that was originally quoted.

13.2 Choice of subcontractors

The most difficult decision was who to choose to make the ASIC. We were guided slightly by another Parkercompany who had chosen to use Thesys for an ASIC project they had worked on. However, we investigated othercompanies such as Chip Express.

A useful source of information here was the FUSE database that the TTN could access to get information on whohas been used by other AEs and what experiences had been encountered etc.

We, therefore, relied on our colleagues within Parker to guide us at this stage and supplemented this withinformation form the FUSE database. Other companies would be best advised to seek advice from the TTN asearly as possible in the application process.

Some silicon manufacturers deal through distribution agents. We managed to deal direct with Thesys but for Chipexpress we dealt with an agent. There may be benefit from dealing with an agent as many offer design help whichcould be very valuable and they are used to dealing with the silicon vendor.

We chose not to sub-contract design because we felt confident in our abilities to carry out the task and we alsowanted the knowledge and experience to do further ASICs in future.

Based on the quotations received we chose Thesys as the company who would manufacture our HEDA ASIC.

13.3 Summary of knowledge and experience acquired1) ASIC Technology Options2) Use of VHDL, simulation and synthesis3) FPGA conversion into and ASIC4) Design for testability5) Fibre Optic interface design and operation6) Communication protocol implementation7) Interfacing with ASIC suppliers

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14 Lessons learned

Initial FeasibilityA very difficult part of the feasibility stage was deciding how big the FPGA or ASIC would be in order todetermine the relative cost merits of using these technologies and obtain accurate quotations for the economicassessment. With very large volume applications, say >50K pieces per annum, this choice is aided by the fact thatASIC technology generally wins through at almost all gate counts. But when volumes of 5K pieces are considered,the NRE cost per piece is more significant.

Getting the quotations ready for the project justification is difficult, not least because at such an early stage of theproject it is very difficult to know how many gates will be required, how much testability is needed, who to use,when the data will be ready etc.Our experience was that this is where a great deal of assistance is required because the whole economics of theproject can rely on these quotations.

The TTN has to be a good source of help here and our advice is to use them as soon as possible. Sort out thedetailed specification for your project before commencement and once you’ve got an estimate of the gate count,arrange for different ASIC vendors to visit and discuss your requirements in detail.

Specification changesA common problem in any project is how to accommodate a change in the specification once the project isunderway. This is an ever increasing problem. As timescales tighten it is not always possible to wait for every lastpiece of information to be present before starting with design work and this inevitably leads to a change at somepoint. Our experiment was no exception. We started with a very good specification. We wanted to increase theplanned usage figures for the HEDA ASIC and we decide to look for other companies that could benefit fromHEDA.

We turned to other Divisions within Parker who manufactured complementary products such as sensors, frontpanels (man machine interfaces) and even complementary technologies such as pneumatic/hydraulic valvecontrollers. We were surprised at the level of interest. We arranged a meeting to bring together interested parties,so that we could get a feel for if HEDA was an appropriate choice for these companies and, if so, what otherfeatures may be required to maximise the potential of the ASIC. This led to some additions being made to thespecification, but because of the modular nature of VHDL it didn’t really impact on the work we had alreadydone, only added to what we needed to do.

So the lesson is to specify what you are sure of in a very detailed manner at the start of the design and treatadditions as non-essential things that may improve the success of the project. Try to be sure that what you arespecifying is realistic. The TTN(or their equivalent) will have a good idea of what is and isn’t possible. Go for theminimum specification that makes the project viable and don’t get too ambitious.

We decided that we needed to spread the use of HEDA beyond our Division in order to maximise not just usageof the ASIC, but also sales of our drives. If our drives can talk to valve islands on the same bus system, we canoffer some customers added value in that they don’t need to specify additional fieldbus options just so they caninterface drives to hydraulics/pneumatics.This saves our customers money making them more competitive and maximises sales to Parker Hannifin which,being money in the pockets of our parent company, helps us too.

Project planningA project spanning a year is always difficult to resource when the team members are part of a small engineeringdepartment and there is a need to develop other products at the same time.During the early stages of the project, there was a slow down in sales in our market sectors and this forced us torevise our product development plans and embark on the most ambitious development that the design team hasever worked on. The impact to the HEDA project was not immediate but was felt at around the time we hadplanned to be testing the FPGA version of the HEDA ASIC.We had to move resource away from HEDA and suddenly our plans for HEDA had to be put on hold. Weslowed the testing and further development of the VHDL code down and we took the opportunity to gainHEDA partners who requested additions to the specification. This work then took place at a slower than desiredpace due to the fact that we also had to do 2 other VHDL designs (FPGAs) for the new products we weredeveloping. Now these would not have been possible to do so quickly if we had not had the VHDL training, so as

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well as giving us the ASIC (eventually) this project has given us the skills to react to other business needs veryquickly using some of the skills that we have learnt.

Looking back we could not see this slow down in sales coming and could only have built some extra slack into ourHEDA plan. The original plan was based on a requirement to have ASICs by October 1998. This requirementchanged and therefore so did the plan.

Cost implicationsLow cost. This is an easy term to use when referring to ASICs, but one which may only be used if the ASICdesign is successful and used in economically viable volumes. A failed design may mean an additional set of NREcharges and without increased volume could seriously impact the success of the products on which the ASIC isbased.

ToolsThere is always a learning curve to climb up when using new tools for the first time. We found our choice ofVeriBest to be very intuitive and on reflection we made a good choice. However, there were problems with thesoftware crashing at first, but these were fixed by the maintenance releases. So a useful lesson is to put softwaremaintenance contracts in place because this ensures that the usefulness of the tool will develop and that technicalsupport and advice is available not only in the first year of ownership, but in years to come. The final version ofVeriBest VHDL workstation used in the project (VB99a) is very good and hardly any problems were encountered.Synthesis issues (VHDL coding styles) were something where we found the on line help very useful. Lesser toolsmay not offer the excellent level of on line help that FPGA Express offers.

15 Resulting product, its industrialisation and internal replication

The FPGA device has been successfully tested in a number of applications by as wide spectrum of potential usesas possible. This ensured that the maximum confidence level possible could be achieved with respect to the finalASIC. In addition the following proposed modifications to the HEDA bus have been achieved:

• improved transfer rate of 10Mbits/s• addition of bit-info cyclic request mechanism for acyclic data exchange• inclusion of a robust fibre-optic interface option as well as a simplified (2 wire) electrical interface• DSP independence i.e. stand alone HEDA peripheral ASIC• ability to operate with a microprocessor/DSP or in a stand alone mode• Digital Input/Output (I/O) capability 16 channels• Additional functionality : SPI interface for serial DACs and ADCs, quadrature encoder interface for motor

feedback devices, expandable I/O via provision of external latch enables (up to 32 channels)• acceptable cost (under 6€)• small physical size (64 pin TQFP package)

The resultant product now incorporates the ability to link with other units using the HEDA interface, and toeither control them (issue commands, monitor status etc.) or be controlled by them via a simple fibre optic link.Previously this would have only been possible via an external unit, but the resultant product is a cost effectivesolution to the needs of many of our customers and will substantially enhance the market status of Digiplan.

Plans to use the HEDA ASIC

When the production ASIC is delivered we will incorporate it into a modified version of the Paragon base drive.This will add around 7€s of material cost to the drive (ASIC + differential drivers). The required effort for thistask is low.

Task Effort in man daysCreate a schematic symbol for the HEDA ASIC 1.5Create a component footprint for the PCB CAD library 1 .5Modify the Paragon base drive schematics 3Modify the Paragon base drive PCB 5Review the design 2

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Manufacture the PCBs 7Build the drives 1.5Commissioning and system test 15EMC tests (possible change to radiated signature) 5LVD tests (little impact to existing product) 2HALT/HASS tests (accelerated life testing) 5Verification and Validation tests 10

Approximate cost for this is 16,000 € including external services (PCB manufacture, HALT testing and part of theEMC testing), and will be completed by the end of 1999. The total elapsed time will be approximately 6 months,following on from successful testing of the prototype ASIC.

ReplicationWe have been able to use the knowledge and expertise acquired during the project to design the key elements inan exciting new range of drives. The Paragon drives that we have recently been designed have been launched andare currently on sale. Some of these drives use a 2000 gate FPGA and some use a 7000 gate FPGA. The code forthese FPGAs was generated using the skills we learnt whilst doing the AE. We designed the FPGAs using VHDL,and we were able to re-use elements of the VHDL code that we had written for the HEDA chip, in the drivecontrol FPGAs. The experience from doing the AE helped us solve problems with the design in a much fastertime. This contributed to the rapid development time of Paragon - in fact it is true to say that without these skillsthe stringent times scales and the small package dimensions could never have been achieved.

We believe that the skills learnt and the experience gained from the ASIC design have already led to furtherinternal replication. During the AE Digiplan recommended that the Offenburg location of EMD purchase thesame VHDL design tools that we were using for the HEDA design. This would assist with development as someof our resource had been diverted but more importantly we felt that these tools would be used in future jointdevelopments and the VHDL modules we had written could be used in FPGA or ASIC designs that may be madein future at either location within Parker EMD. In addition staff from Digiplan gave a presentation to theircolleagues in the United States in order to share their experiences and convince them that the successfuldevelopment of complex products could best be achieved using VHDL and synthesis.

16 Economic impact and improvement in competitive position.

The full breakdown of the figures presented in this section is available in the confidential part of this report.Absolute values for the benefits are not given in this section in order to retain the commercial advantage that theHEDA ASIC will give Digiplan.

The economic impact is only achieved because of the benefits - or added value - to the customer. These arecentred around the improved functionality, and on the low cost overhead that is incurred as a result of thisadditional functionality. In addition to the drive cost (which is, to the customer a component cost) there areadditional benefits in the reduction of the system costs since the HEDA bus functionality enables the use of asingle fibre optic link between systems components.

16.1 Projected salesIncrease sales will result from the use of the HEDA ASIC because of the increased functionality that the customerwill benefit from. This functionality - that is the ability to interface between a number of axes either of stepper orservo drives - will be provided at a very low additional cost. In addition the servo drives will benefit from the factthat the DSP will no longer be carrying out the HEDA interface function and more of it's processing power willbe available for controlling the motor.

Projected sales of existing stepper products including the new Paragon and allowing for cannibalisation of existingproducts, for the next three years is:

Year Sales % relative to 1998 packaged + rack2000 101%2001 157%2002 185%

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The addition of HEDA to stepper drives will open up opportunities in CNC and machining applications.

The estimated sales including HEDA based drives is :

Year Sales % relative to 1998 packaged + rack2000 108.5%2001 190%2002 256%

The increases are based on additional drives with the HEDA function sold and a percentage of base drives that wewould pick up from getting the HEDA drives business (spin off).

The existing sales of Servo drives with HEDA for synchronised multi-axis systems are expected to grow at a moremodest rate (15% per year) as this market is already established. HEDA is currently supplied in about 20% ofCompax servo drives sold. This percentage is increasing and with the fibre optic connection possible using theHEDA ASIC, it still makes sense to add the HEDA ASIC to DSP based drives, as this frees up the DSP to addother functions such as more intelligent tuning or an even better current/position control loop.

Some applications of Compax use a Profi-bus or an Inter-bus module in each drive and these drives are on a bigfieldbus network. In future we plan to have only a gateway from Profi-bus (or Inter-bus) to HEDA and have ourown local HEDA network which is a much more cost effective method of implementing fieldbus on our drives.We expect that over the next 3 years, 70% of Compax axes sold will be fitted with HEDA.

16.2 Quotation for final ASIC

Note: This quotation differs from that presented in 7.1.3 because this is the actual quotation based on the finalgate count. The quotation was supplied by subcontractor 2 : Thesys.

Qty of ASICsTQFP64 package

THA8077cost €

2.000 8,405.000 5,8310.000 4,8020.000 4,2650.000 3,75

16.3 Revised Usage Figures

Based on the current projections for products using HEDA, the number of ASICs required each year for the nextthree years have been projected:

Year 2000 2001 2002HEDA ASIC volume 4015 10050 15869Purchased volume 5000 10000 15000

The ASIC volume is made up from stepper sales, servo (COMPAX) sales and sales to other Parker locations.In the year 2000 we will buy approximately 5000 ASICs at 5.83€ each and in 2001 we’ll buy 10000 ASICs at 4.80€each.

We wish to recover our costs over 2 years.

The average buy in cost of ASIC over the 2 years will be 77150€ /15000 pieces = 5.14€.

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16.4 Project cost (€)

Labour : 5355 (projected hours) x 21€ per hour = 112455ASIC NRE : 21218SCAN pattern generation : 4601FPGA to ASIC Netlist transfer : 7669Materials: 1670Over-spend on VHDL design software : 19000Total project costs = 166613€Total industrialisation cost = 16000€

16.5 Payback period

The increase in profitability will be from the profit gained from new HEDA business i.e. stepper only business.There will be some gains from servos but for this justification we shall only consider the margin contributed bythe sales of HEDA Paragon drives as if anything the improvement will be better. This allows us some room forerror since if the stepper sales are not met, the additional profit from the servos (Compax drive sales) shouldensure that the financial targets are still met.

For HEDA equipped Paragon drives the increased profit will amount to approximately 850K€ over two years.Assuming a linear relationship then the payback period will be:13.9 months based on AE costs only or 14.1 months including industrialisation costs.

16.6 ROI

The projected life of HEDA based drives is greater than 3 years.The increase in profitability over 3 years (the shortest life span) is 2.4M€Most of the profit arises in year 3. This is because of the fact that we are planning on increasing the percentage ofdrives that will use HEDA over each year and also the margin improves in year 3, because in years 1 and 2 we arerecovering a significant additional tooling cost (plastic drive case mouldings) for the Paragon drives.

ROI is 1463% excluding industrialisation cost or 1334% including the cost of industrialisation.

17 Summary of best practice and target audience

A number of very important lessons relating to best practice had been learned during the course of project:-Ø Undertake a thorough analysis of requirements before commencing projectØ Obtain external assistance e.g. a TTN, to assess project feasibility and to identify suitable technologiesØ Use networking to benefit from the experiences of others - either in other divisions, or through other network

(e.g. FUSE)Ø Establishing a core element for a range of projects can enable the benefits of ASICs to be realisedØ Use of VHDL and synthesis can enable a small team to produce a complex design and effectively integrate

their individual effortsØ Re-use of code can facilitate the development of future productsØ Monitoring of suppliers performance can enable early detection of potential problemsØ Ensure any supplier contract protects your IPRØ Analysis of market requirements before and during a project can enable the development of a project with

maximum market impact

The experiences from this project will be of interest to any company that designs products using digital circuitry,particularly in the process control, automation and instrumentation markets especially those who need to includehigh levels of functionality in a cost effective way. It will be of particular relevance to companies with a maturemarket and whose management are prepared to accept the challenge of new technology. The relevant Prodcomcodes 30, 32 and 33.