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Nano Res
1
High resolution scanning gate microscopy
measurements on inas/gasb nanowire Esaki diode
devices
James L. Webb1 (), Olof Persson1, Kimberly A. Dick2, Claes Thelander3, Rainer Timm1 and Anders
Mikkelsen1
Nano Res., Just Accepted Manuscript • DOI: 10.1007/s12274-014-0449-4
http://www.thenanoresearch.com on March 7, 2014
© Tsinghua University Press 2014
Just Accepted
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Nano Research DOI 10.1007/s12274‐014‐0449‐4
1
High Resolution Scanning Gate Microscopy
Measurements on InAs/GaSb Nanowire Esaki Diode
Devices
James L. Webba*, Olof Perssona, Kimberly A. Dickb, Claes Thelanderc, Rainer Timma and
Anders Mikkelsena
aDivision of Synchrotron Radiation Research, Lund University, Sweden,
bDivision of Solid State Physics, Lund University, Sweden,
cCenter for Analysis and Synthesis, Lund University, Sweden
e-mail: [email protected]
Keywords: Nanowire, Scanning gate microscopy, Esaki tunnel diode, InAs, GaSb, III-V,
heterostructure
Abstract
Gated transport measurements are the backbone of electrical characterization of nanoscale
electronic devices. Scanning gate microscopy (SGM) is one such gating technique that adds
crucial spatial information, accessing the localized properties of semiconductor devices.
Nanowires represent a central device concept due to the potential to combine very different
materials. However, SGM on semiconductor nanowires has been limited to a resolution in the
50-100nm range. Here, we present a study by SGM of newly developed III-V semiconductor
nanowire InAs/GaSb heterojunction Esaki tunnel diode devices under ultra-high vacuum. Sub
5nm resolution is demonstrated at room temperature via use of quartz resonator atomic force
microscopy sensors, with the capability to resolve InAs nanowire facets, the InAs/GaSb
*To whom correspondence should be addressed, e-mail: [email protected]
2
tunnel diode transition and nanoscale defects on the device. We demonstrate that such
measurements can rapidly give important insight into the device properties via use of a
simplified physical model, without the requirement for extensive calculation of the
electrostatics of the system. Interestingly, by precise spatial correlation of the device electrical
transport properties and surface structure we show the position and existence of a very abrupt
(<10nm) electrical transition across the InAs/GaSb junction despite the change in material
composition occurring only over 30-50nm. The direct and simultaneous link between
nanostructure composition and electrical properties helps set important limits for the precision
in structural control needed to achieve desired device performance.
Introduction
Semiconductor nanowires represent a highly active research field, for example with regard to
realizing advances in optoelectronic properties in applications such as solar cells[1][2] solid
state lighting[3] as well as electronic devices such as tunnel diodes[4] and nanowire field
effect transistors[5][6]. Nanowires are also used in research of more fundamental physics,
such as in recent studies of potential Majorana fermions[7][8] and exciton dynamics[9][10].
The antimonide compounds (InSb, GaSb) are of recent interest for a range of applications as
they form a broken bandstructure at the interface with InAs[11][12]. Such interfaces are of
relevance for a broad range of studies from high performance nanowire transistors[13][14] to
research on topological insulators[15].
Scanning probe microscopy (SPM) techniques offer an excellent means to characterize
semiconductor nanowires, with recent work on atomic force microscopy(AFM) and scanning
tunneling microscopy (STM) studies of electrically grounded individual nanowires deposited
on conducting surfaces[16-18]. However, semiconductor nanowires exhibit variability within
each growth set (of many thousands of wires). This makes it hard to identify an important
structural aspect specific to a single nanowire used for a device to the (general) properties of
3
other nanowires fabricated in the same growth set measured in parallel by complementary
techniques. These may include properties such as defects, doping and wire surface
composition alongside the effects on the wire of annealing, cleaning and processing
techniques and can have significant bearing on the behavior of the device. Imaging a single
device nanowire whilst measuring its electrical properties during device operation provides a
means to avoid this issue and directly link such specific nanowire properties to changes in the
device's electrical behavior and would be extremely useful in and identifying possible routes
for device improvement.
Scanning gate microscopy, by which the conductance of a semiconductor device can
be modified by the local gating effect produced by an STM or AFM tip close to the wire, is
one such method that nanowire devices may be characterized during operation. SGM is
especially useful due to the dependence of the gating on the (capacitive) coupling between
wire and tip, in turn dependent on the surface and bulk properties of a nanowire. This allows
both of these to be probed, providing information such as the local carrier type and a
qualitative indication of the carrier concentration in the nanowire under the tip. SGM is a
well-established technique, having been used previously to study III-V semiconductor
nanowire devices at low temperature[19], for InAs nanowires[20][21], for InN[22] and Si
nanowires[23],to study carbon nanotube devices[24] and work on low dimensional
systems[25][26]. Alternative complementary techniques have also been used to characterize
operational devices, including SPM methods such as Kelvin force microscopy[27][28] and by
other means such as focused laser excitation by scanning photocurrent microscopy[29].
Here, we focus on SGM measurements on the InAs/GaSb nanowire Esaki (tunnel)
diode, consisting of a single InAs-GaSb heterojunction (in a single nanowire) with excellent
tunnel diode properties[4]. The structure is also of relevance for complementary field effect
transistor structures[30][31]. Electrical and SPM measurements of such a device can be
performed in a lateral geometry, with the wire flat on an insulating (Si/SiO2) substrate surface
4
and contacted at 2 or more points by metallic electrodes patterned by conventional
lithographic techniques (see Figure 1). In this work we measure the gating effect on such
devices using a tip at positive or negative bias Vtip in either a fixed position over the nanowire,
or scanning in AFM mode across its width or along its length whilst measuring changes in
device conductance. By this method we can resolve nm-scale structural features of the wire
itself, particularly those difficult to observe by standard AFM such as localized defects, in
addition to investigating the physics of the device operation through reproducing trends in
device electrical transport behavior under gating using a simplified model of the device.
Results and discussion
A first verification of gating effect was performed by measuring Isd with the tip
stationary a) above (on top) and b) away from (off) the nanowire. Figure 2 shows the current
through the device Isd as a function of applied bias Vsd at different Vtip with the tip placed
directly above the InAs nanowire section or 5μm off the wire. In the latter case (and for
Vtip=0), we observed electrical behavior characteristic of Esaki diode operation with a
negative dI/dV region (with peak Isd in this region at around Vp=Vsd=0.62V) in forward bias
(Vsd>0). Off the wire, the conductance behavior of the device was unaltered by any bias
applied to the tip. With the tip placed on top of the InAs section (approximately 500nm from
the heterojunction) an increasingly negative Vtip was found to suppress overall device
conductance. This included the elimination of the negative dI/dV region, an effect we attribute
to electron carrier depletion in the InAs under the tip reducing those available for tunneling at
the junction, plus reduction of reverse bias current at negative Vsd .Over GaSb, no clear tip
gating effect was observed.
In the ungated case, we observe a peak-to-valley ratio for the negative dI/dV region of
1.3 with typical device resistance was in the 1-3MΩ range. Current densities of 0.98kA/cm2 at
reverse bias -0.3V were observed (assuming a 35nm InAs part diameter junction). These
5
figures are comparable to other axial nanowire tunnel junction devices[32] at room
temperature but less than the InAsSb/GaSb Esaki diodes reported by Ganjipour et al.[33]
specifically designed for high current operation. In this latter work, with a high-κ
lithographically patterned top gate over the entire nanowire, the same negative gate
suppression of conductance was observed, with the threshold for significant effect at V<-1.3V
and complete suppression of the negative dI/dV region at V<-2V. For the tip gate on InAs, we
require a higher tip gate bias to achieve the same effect, likely due to the more localized
nature of the gate and absence of the dielectric material.
Further measurements were performed on another device by setting a fixed Vtip and
measuring the change in Isd through the nanowire whilst scanning in AFM mode the tip across
the wire width (in x, Figure 3), simultaneously measuring the height profile beginning with an
overview scan encompassing a large section of the nanowire covering both InAs and GaSb
sections and part of the Ti/Au contacts. This can be seen in Figure 3. For Vsd>0 (forward bias)
and Vtip<0, conductance was suppressed over the n-type InAs wire section, a feature we again
attribute to the local depletion of carriers in the wire under the tip. The opposite enhancement
effect was observed for positive tip bias Vtip>0, behavior identical to that observed in the work
by Zhou et al. [34] for InAs-only nanowires. In contrast to their work, we observed strong,
homogeneous gating along the length of the InAs segment with minimal interference from the
metallic electrodes, which we attribute to low resistance nanowire-electrode contacts. Little
effect was observed on the GaSb, an aspect requiring further measurement detailed below.
The unexpected gating effect on the Au pad was an artifact produced by incomplete Ti/Au
coverage of the nanowire combined with the increasing unstable oscillation of the tip
scanning on the embedded wire causing it to move into closer proximity with the nanowire,
producing a strong gating effect.
A notable effect observed during measurement was the presence of a larger gating
effect with the tip at the edges of the nanowire rather than on the wire top at lower tip bias
6
(Figure 4,d). Based on Poisson equation simulations of the electrostatic potential, we attribute
this effect to the additional electric field and tip-wire coupling on the wire edge due to the
geometry of the tip and reduction in mean tip-wire distance when scanned across the
nanowire. At increasingly negative tip bias Vtip→-4V a strong gating effect could be observed
not only at the edges but on top of the wire itself.
Higher resolution scans were performed on the InAs part of the wire. At such high
resolutions, it became possible to observe the crystal facets of the InAs part of the nanowire
(Figure 4,c with structure shown schematically in Figure 4,a) due to the change in tip-wire
coupling and hence gating effect at the side facet edges. This demonstrated the extremely
good nm-scale resolution of the microscope and a direct link between surface topography of
the wire and the electrical transport properties of the device. We estimate the maximum
achievable resolution to be sub-5nm from the images and linescans over the wire step edge.
This high resolution represents a significant improvement over previous SGM studies of
nanowires devices, where only a broad effect at the approximate wire position was observed
with little detail on the wire itself, comparative examples of which include the work by Yang
et al. on Si nanowires[35], Liu et al. for InN nanowires[22] or Martin et al. for Si/NiSi2
nanowires[23].
We attribute the improved resolution as compared to earlier work to the different
design of our system, which utilizes high stiffness and high Q factor qPlus sensors based on a
resonant quartz tuning fork with an all-metallic tungsten tip, suitable for multi-mode
STM/AFM/SGM operation. Such AFM systems have previously been demonstrated to
achieve atomic scale resolution in standard AFM imaging mode[36][37]. The smaller
vibrational amplitudes associated with quartz sensors and scanning in a low-noise UHV
system designed for atomic resolution STM operation are extremely beneficial to high
resolution scanning. In addition all-metallic tungsten tips are more robust against degradation
than metal coated Si tips used in alternative cantilever systems[38]. We consider that this
7
setup offers considerable advantages over alternative laser-based AFM systems for
SGM[39][40].
In order to investigate gating in more detail across the heterojunction, we performed a
series of scans along the wire length with the tip directly above the center of the wire (x=0).
Despite the weaker observed gating effect, we considered this to be the best method to avoid
anomalous variation in gating strength due to identified enhanced gating effects arising from
scanning over the nanowire edge. We considered this to be due to the relatively flat nature
(<10nm roughness) on the top crystalline facet of the nanowire. This reduced the likelihood of
any anomalous change in gating strength during measurement arising from changes in
tip-nanowire distance through the reaction of the AFM feedback system, which could result
from a scan across the entire height of the nanowire. Such a method also ensured applying a
consistent shape of electric potential to the nanowire from the tip centered above it,
minimizing variation arising from inhomogeneity in tip or nanowire geometry that could
otherwise arise by scanning across the full nanowire width.
Figure 5 shows the change in Isd as a function of position y along the wire and as a
function of bias across the wire Vsd for Vtip=0 relative to -3V. A negligible drift was observed
during the 20-30min scan time, confirmed by simultaneous imaging, tip height monitoring
and by repeated scans to verify the data. We observe a transition at the interface from current
suppression in the InAs to weak current enhancement in the GaSb, the latter an aspect not
seen in detail for scans across the wire. The effect was localized in the Vsd region with
negative dI/dV, in the tunneling regime of operation. For this device, the bias at peak
tunneling current Vp was reduced slightly to 0.4V as compared to 0.6V for the device in
Figure 2, an effect we attribute to variability in series resistance to the nanowire produced
during the fabrication or measurement process.
To provide some explanation for these observations we consider a simplified
bandstructure model of the heterojunction, as shown schematically in Figure 6. In this form
8
we consider a simple broken bandstructure, neglecting bandbending at the interface, which we
consider to be abrupt at y=100nm. We model the tip gate to act as an effective potential
Veff ≤Vtip decaying exponentially in y along the wire and perturbing the energy of the
conductance and valence bands in each material - to higher energy for Vtip<0 and lower for
Vtip>0. For Vtip<0 and far from the junction, this effect can be considered as to introduce an
additional energy barrier acting as an additional resistance (with enhanced conductance for
Vtip>0) leading to the general trends in gating effect observed. At the junction, this effect can
reduce the potential required to align conduction states in InAs with empty valence states
available for tunneling on the GaSb side. In the tunneling regime, for Vtip<0 and tip on InAs,
this has the effect of shifting the position of peak tunnel current, with maximum alignment in
states, Vsd=Vp0 (without gating) to lower Vsd=Vp1 as detailed on the schematic in Figure 6.
Due to the size and geometry of the tip we consider the perturbation of the band
energy to act over a significant proportion of the wire, producing a weak effect at the junction
even when scanning several hundred nm away. This small effect at the junction has a
significant effect on Isd in the tunneling regime due to the low number of states available and
the minimal potential required to shift Vp, altering the position at which peak tunnel current
occurs, and reducing overlap between conduction and valence bands. For the tip over the
GaSb section, the same perturbation effect is produced but acting to increase Vp→Vp2.
We consider the idealized device current to take the form Isd=It + Id with tunnel current
given by the approximate form[41] pVVppt VVII 1e combined with the standard
expression for p-n diode current 1e0 thVVd II and where Isd is normalized to the zero
tip bias peak current Isd(Vsd=Vp0). Using these empirical formulas allows the qualitative
reproduction of tunnel diode current in the different regimes of operation without requiring
extensive calculation of the device electrostatics, permitting comparison to the experimental
data and giving some insight into the physics of the device.
9
By modeling device behavior using this model to derive Vp and evaluating the
empirical expressions for tunnel and conventional diode current in forward bias, the effect on
current can be qualitatively mapped as a function of tip position. Figure 7 shows the result for
Vtip=-1V close to the junction on InAs and GaSb as compared to Vtip=0, demonstrating the
resulting shift in device current ΔIsd in the tunneling regime. The changes in Vp act to reduce
Isd over InAs and increase it over GaSb, qualitatively replicating the effect measured by
experiment. At low bias, significant gate independent tunneling dominates and at high bias the
device operates as a conventional p-n diode, reproducing the absence of tip gate dependence
in these regimes that we also observed experimentally.
The dependence on tip position can be seen in Figure 8 showing the modeled shift in
Vp relative to the ungated state Vp0 as a function of position along the nanowire, as compared
to the experimentally derived position of Vp from the data shown in Figure 5 (dashed gray
line). For both modeled and experimental data, the size of the shift in Vp and hence strength of
gating effect increases as the tip moves towards the heterojunction, with a change in sign of
the effect moving from one material to the other. Although qualitatively matching the
observed behavior (with some quantitative agreement over InAs), the model overestimates the
strength of the effect in GaSb at the junction, predicting a maximum ΔVp=0.75. We attribute
this to the inadequacy of such a simplified model in calculating the complex effects produced
with the tip extremely close to or on the heterojunction combined with the fact that the
junction is not necessarily as abrupt as modeled, with a gradual shift in material composition
between each part, as shown in Figure 1. Considering a uniform strength of gating effect
between the two materials may also be invalid, due to this gradual change in composition and
due to the higher n-type doping concentration of the InAs section. Despite the gradual
material composition change of the wire, the junction remains abrupt with a shift in Vp
behavior over a range of 5-10nm, significantly less than the 30-50nm change from InAs to
GaSb as shown in Figure 1. Notably, this can be resolved using the SGM technique despite
10
the large scale effect of the tip gating. Using SGM, we can identify the precise position of the
tunnel junction within the wider material transition from GaSb to InAs. We find the junction
to be coincident with the initial increase in nanowire width, as can be seen by comparing to
the AFM height profile in Figure 8. This demonstrates the effectiveness of the technique in
correlating localized structural change to device function.
Identification of defects by scanning probe techniques in a device is an aspect of
considerable interest[27][42][43]. This is particularly the case for defects that cannot be easily
identified by ordinary AFM, such as those with little surface prominence. In order to test the
use of SGM in defect identification, artificial defects were induced in a InAs/GaSb device by
running the tip into the left hand side of the nanowire close to the heterojunction (on the InAs
side), removing a small section of the wire. Figure 9 shows the resulting SGM measurement
on that device for both positive and negative tip biases. The defect can be clearly observed by
the scanning gate technique, due to its effect on the local gating produced by the local
disruption of the surface, despite being near-invisible under AFM.
Conclusions
We have fabricated a series of InAs/GaSb Esaki diode devices consisting of a
semiconductor nanowire with lateral Ti/Au contacts, demonstrating good tunnel diode
behavior. Using scanning gate microscopy combined with non-contact AFM, we have
characterized the electrical transport properties of such devices whilst simultaneously
scanning and imaging using AFM. We observed a strong gating effect over the InAs wire part
with near complete suppression of Isd at a tip bias of Vtip→-4V and enhancement of
conductance at positive tip bias conforming to trends seen in previous studies[34]. As a
function of Vsd, this gating effect was greatest in the region with the device in the tunneling
regime of operation and thus most sensitive to changes produced by the local tip gate. A
simple model considering the effect of shifting the bias required to reach peak tunnel current
11
Vp and using standard empirical formulas for tunnel diode current was able to qualitatively
reproduce the trends in conductance behavior observed in the different regimes of device
operation, giving significant insight into the physics of the device operation that could not be
obtained from an electrically grounded single nanowire. A clear link between wire surface
structure and electrical transport was demonstrated by imaging the nanowire facets by SGM,
also highlighting the very high resolution possible using the technique. This allowed
observation of wire detail and gating measurements down to the sub-5nm scale, significantly
better than other SGM works performed at room temperature[22][34]. This also permitted
identification of defects introduced into the nanowire that could not be observed by AFM
alone. No aspect of the work was limited to III-V nanowire systems, with standard fabrication
and SPM techniques used throughout, permitting its potential application to the
characterization of a wide range of semiconductor devices.
Such measurements demonstrate the potential of our SGM setup for non-destructive
characterization, potentially during and after alteration of the device surface by deposition,
oxidation, passivation and other in situ processing under highly stable UHV conditions. This
can be performed whilst also working alongside complimentary methods such as TEM and
XPS to give high quality information about the behavior of a specific nanowire device. Such
data allows a simultaneous connection between device nanowire structural changes and
electrical properties, something which is not possible by separate SPM and transport studies
alone.
Methods
Nanowires were grown by low-pressure metal-organic vapor phase epitaxy
(LP-MOVPE, 10 kPa) in hydrogen carrier with a total flow of 6 L/min, using size-selected
gold aerosol particles with nominal diameter 30 nm, on InAs (111)B substrates. The InAs
nanowire section was grown at 450 C for 13 minutes using trimethylindium (molar flow
12
4.5x10-6) and arsine (1.9x10-4). Tetraethyltin (1.9x10-7) was added after 4 minutes of growth
to n-dope the InAs, and switched off 1 minute before the end of the InAs. The GaSb section
was grown at 500C for 20 minutes using trimethylgallium (3.4x10-5) and trimethylantimony
(3.5x10-5); diethylzinc with a molar flow of 1.9x10-5 was used to p-dope the GaSb. Further
details of the growth can be found in the work by Ek et al .[44]. Figure 1 shows a TEM image
through the nanowire heterojunction, showing the change in crystal growth and wire diameter
(50 nm for the GaSb, 35 nm for the InAs) and across the heterojunction. The composition of
the nanowire does not shift abruptly between InAs and GaSb - instead a gradual change over
50-100nm occurs, as can be seen from the energy-dispersive X-ray spectroscopy (XEDS)
measurements of the composition taken across the interface between the two materials.
Device fabrication was performed on n++ doped Si/SiO2 substrates with SiO2 oxide
thickness 200nm. Dry deposition of wires was performed onto pre-fabricated 80nm thickness
Ti/Au electrical contacts patterned by mask aligned UV photolithography, in addition to
markers for nanowire location patterned by electron beam lithography (EBL). Nanowire
position was identified by scanning electron microscopy (SEM) using a FEI Nova NanoLab
600 SEM to image a 100x100μm area containing the EBL pre-patterned alignment markers as
a position reference. Nanowire position was then identified from the marker grid to create a
contact electrode pattern to it, from 10μm width contacts to the initial photolithographic
electrodes down to two 250nm width contacts to opposite ends (one to GaSb, one to InAs) of
the nanowire. Deposition of these contacts was performed by vacuum thermal evaporation of
40nm of Ti and 80nm of Au at 5x10-7mbar base pressure. Prior to deposition, the wire was
exposed to oxygen plasma (at 5mTorr O2 pressure) for 45s and placed in 1:9 HCl:H2O
solution for 30s in order to remove any residual resist and to reduce native oxide thickness.
Measurements were performed at room temperature in an Omicron XT dual
AFM/STM at 10-11mbar ultra-high vacuum (UHV) using Omicron qPlus[45] sensors of a
damped quartz tuning fork resonator design, with an all-metallic tungsten combined
13
AFM/STM tip, capable of tip bias Vtip up to +/-10V relative to ground. All SGM
measurements were performed in non-contact AFM mode. 4 electrical contacts to a
custom-made sample plate were utilized, with the device chip adhered to the sample plate
using indium and Al wire bonded to the plate electrical connections via additional Au foil
pads. Due to the sensitivity of the devices to electrical shorting, external grounding was
provided by means of a break out box to each contact, permitting separate grounding of both
device and measurement equipment. Electrical measurement was performed using a Keithley
2401 sourcemeter to apply a bias Vsd across the nanowire device. A Stanford SR570 low noise
current preamplifier was used to measure current Isd through the device, such that Vsd>0
represented a positive bias applied to the p-type (GaSb) end of the nanowire (forward bias).
Acknowledgement
This work was performed within the Nanometer Structure Consortium at Lund
University (nmC@LU), and was supported by the Swedish Research Council (VR), the
Swedish Foundation for Strategic Research (SSF), the Crafoord Foundation, the Knut and
Alice Wallenberg Foundation, and the European Research Council under the European
Union's Seventh Framework Programme Grant Agreement 259141. One of the authors (R.T.)
acknowledges support from the European Commission under a Marie Curie Intra-European
Fellowship.
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Figures
Abstract Figure: Schematic of SGM on a InAS/GaSb device (SEM, below) with current
suppression (darker) and enhancement (lighter) shown alongside AFM profile.
20
Figure 1: (Left)SEM image example of InAs/GaSb nanowire lateral device on Si/SiO2,
contacted by Ti/Au electrodes. The wider section of the wire is the GaSb part, the narrower
the InAs part with the heterojunction (A) between materials indicated. Nanowire diameter is
50nm for the GaSb, 35nm for the InAs. (Center) TEM image across the heterojunction A
between the narrower InAs and wider GaSb parts of the wire (Right) Compositional analysis
of the nanowire heterojunction by XEDS showing the variation in nanowire composition
across the interface.
21
Figure 2: Isd through the nanowire device as a function of Vsd for Vtip=0→-4V both on and off
the InAs nanowire section (schematically indicated). The device showed Esaki diode
characteristics, with a negative dI/dV region, which was dependent on tip bias.
22
Figure 3: Overview SGM (top) and AFM (middle) scan of an entire nanowire device plus part
of the Ti/Au contacts, with electrical connections schematically shown (bottom) for low
forward bias Vsd=0.1V and Vtip=-2V. The conductance is shown in a normalized form in order
to highlight the nanowire position, with darker color reflecting a lower conductance.
Reduction in (normalized) conductance (Isd→0.5-0.6, darker) was observed for the tip over
the InAs wire part, with little effect observed on GaSb or off the wire (Isd→1).
23
Figure 4: a) Schematic (SC) diagram of hexagonal wire structure, b) AFM scan of the wire
(with overlaid line profile, black) and c) high resolution SGM on InAs part. The SGM
resolution is sufficient to image individual surface steps within the wire side facets due to the
change in gating effect as the tip crosses them, which cannot be observed by AFM alone. d)
Higher detail SGM on the wire across the InAs/GaSb junction, showing reduction (darker)
and enhancement (lighter) of conductance when scanning across the wire at negative and
positive tip bias respectively. The strongest effect was observed at the edges at low bias
(Vsd=0.1V), with additional strong gating with the tip on top of the wire at Vtip<-3V. For
Vtip=-4V, a tip change is observed as a shift in gating effect position, produced by the strong
electrostatic forces scanning at high tip bias close to the nanowire surface.
24
Figure 5: Difference in current through the wire between zero and positive tip bias
ΔI=Isd(Vtip=-3V) - Isd(Vtip=0V) as a function of bias across the wire Vsd and position y(in nm)
along the wire length, with the tip centered on top of the wire. The junction is located at
approximately y=450nm. Conductance is reduced on the InAs part (y<425nm) and weakly
enhanced on GaSb (y>475nm), with a transition region inbetween. This is also shown on the
local plots of current vs. Vsd (right) with their measurement position indicated by an arrow.
The peak absolute effect on ΔI averaged in 10nm intervals is indicated as guide by the grey
dashed line.
25
Figure 6: Model schematic of the InAs/GaSb heterojunction bandstructure. represents the
subtracted position dependent voltage drop across the junction and E energy, with E- in eV.
The perturbation in conduction band (CB) and valence band (VB) produced by a negative tip
(Veff=Vtip<0) on InAs (top) and GaSb (bottom) is shown. The (forward) bias needed to reach
peak tunnel current with maximum overlap of available states Vsd=Vp is indicated. The effect
of the tip bias is to decrease (increase) Vp on InAs (GaSb), producing a decrease (increase) in
device current Isd. Here, Vp1<Vp0<Vp2, where Vp0 is the peak tunnel current bias for Vtip =0, Vp1
the lower bias with the tip on InAs and Vp2 the higher bias on GaSb. Tip position is indicated
(blue arrow).
26
Figure 7: Plot of modeled device current Isd. The effect of the tip on InAs is to reduce
Vp0→Vp1, resulting in a reduction in current in the negative dI/dV tunneling regime as
observed for the device. The opposite effect is produced by the tip on GaSb where Vp0→Vp2
and a positive ΔI results. At high Vsd, It→0 and conventional diode behavior dominates.
27
Figure 8: (Left vertical axis) Change in peak tunnel current ΔVp =Vp-Vp0 as a function of
position y along the wire (at x=0) across the heterojunction (at y=100nm) for Veff=Vtip<0 and
uniform gating on both materials. A sign change in effect is produced between InAs and GaSb
- moving from current suppression to enhancement. Overlaid is the peak position data from
experiment, represented by the gray dashed line in Figure 5. (Right axis) AFM height profile,
showing the sharp structural change (increase in wire width) across the heterojunction.
28
Figure 9: Identification of defects. An artificial defect was produced in the device by a
standard AFM/STM tip, which can be clearly observed under SGM due to the enhancement of
the local gating effect around it due to changes in wire structure. In contrast, the defect cannot
be clearly seen under AFM.