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High-Performance Bulk MOSFETs: Optimization ofDevice Characteristics and Series Resistance

Zhixin Alice Ye, Graduate Student, UC Berkeley

Abstract—In the 20 nm gate length, device series resistancebecomes an increasing concern. Simulations were conducted on ahigh-performance bulk MOSFET to investigate how an optimizeddoping profile of a bulk device is able to impact series resistanceand device performance. It was found that the device overall wasable to meet the majority of ITRS requirements, though overallon current, Ion, was not met due to lack of strain implementation.Through optimization of the source drain extension profile, thetradeoffs between the tip resistance and spreading resistancethrough the LDD to the channel was investigated.

Index Terms—Bulk device, high performance MOSFET, 20nmgate length, high-k dielectric, metal gate, retrograde doping,series resistance.

I. INTRODUCTION

W ITH scaling down the size of transistors, it is increas-ingly important to consider series resistance in order

to optimize overall circuit performance. Parasitics includingseries resistance and overlap capacitance have a large impacton circuit delay; thus for overall improved circuit performance,devices should be optimized for both parasitics and seriesresistance. In this paper, a 20nm NMOS device was simulatedin Sentaurus and optimized to have good device characteristics.Then, the series resistance of the device was studied, andthe LDD doping profile concentration and junction abruptnesswere investigated to understand their impact on series resis-tance. Antimony was then used in processing simulations toattempt to simulate abrupt doping junctions and observe theseeffects on tip resistance.

Series resistance of a bulk MOSFET can be broken downinto several different components, as illustrated in Figure 1[1]:

• Contact resistance, Rco, which is defined as the resistanceof the top metal or silicide and the diffusion underneaththe leading edge of the contact. Rco can be calculatedusing the following equation:

Rco =

√ρ2ρc

W× coth(l

√ρ2ρc

)

Here, ρ2 is the resistivity of the n+ or p+ doped siliconunderneath the contact. ρc is the resistivity of the metalor silicide, l is the contact window length, and W is thewidth of the transistor.

• Diffusion sheet resistance , Rsh, which can be measuredthrough a number of methods. One methodology is toexpress Rsh as:

Z. Ye was with the Department of Electrical Engineering and ComputerScience, University of California Berkeley, Berkeley, CA, 94720, USA. e-mail: alice.ye@berkeley.edu.

Rsh =ρS

WXj

where ρ is the average bulk resisitivity of the n+ or p+layer, Xj is the junction depth, S is the spacing betweencontact and next resistance component. For the case ofa shallow source drain extension, the sheet resistance ofthe deep source and drain must be calculated seperatelyfrom the extension.

• Tip resistance, which is broken down further into spread-ing resistance, Rsp, and accumlation layer resistance, Rac,which includes the overlap between the doping layerand the gate oxide [2]. These resistances are consideredtogether because the gradual change in resistivity inpractical devices would impact both the accumulationlayer and location of current spreading. Tip resistance isconsidered to be a strong function of the gradient of thedoping profile (α eKx), and is considered to be a largepercentage of the total series resistance.

Fig. 1. Major components of series resistance through the path of currentfrom contact to the channel [1].

Based on the above components, various options for min-imizing series resistance can be explored. In this paper, thearea of silicide in the contact was varied to examine impact oncontact resistance, the location of the source/drain was variedto examine sheet resistance, and the LDD profile gradient waschanged to study tip resistance. Overall series resistance canthen be improved by then reducing each of these factors.

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II. FABRICATION PROCESS

The process flow for the optimized device used a high-performance CMOS process without the implementation ofstrain, as shown in Fig 2. Ion implantation of indium on ap-type wafer at 35 keV and dose of 5.0e13 cm−2 was used tocreate a steep retrograde channel doping [4]. 2 nm of oxidewas deposited followed by 60 nm of polysilicon, which wasthen anisotropically etched in RIE to form a dummy gate.A lightly doped drain was formed using ion implantation ofarsenic at 2 keV and 2e14 cm−2 dose. Then, a 10 nm nitridespacer was used to implant the self-aligned source and drain,which used ion implantation at 3 keV and 1e17 cm−2 dose. Asecond gate-drain implant was used to suppress leakage pathsunderneath the source and drain, with an energy 36 keV anda dose of 1.3e14 cm−2. Activation of dopants was conductedthrough a 900C anneal for 1ms at the end, similar to laserannealing [5].s A 42 nm thick nickel silicide was then grownto minimize series resistance of the contact [3], and a layerof oxide was deposited and flattened with CMP. The dummygate and oxide was replaced with hafnium oxide with a K of12.5, and titanium nitride as the metal. Contacts were etchedand filled with aluminum.

Fig. 2. Final high performance device structure simulated in Sentaurus withhigh-k dielectric, metal gate, extension and source-drain implants. A singlespacer was used to separate the extension from the deep source-drain. Anindium substrate doping was used to achieve a steep retrograde doping tosuppress substrate leakage.

Strain was not implemented due to project constraints,and halo doping was not implemented in the end becausethe retrograde doping was found to be sufficient to suppresspunchthrough. Extensions were implanted in both the sourceand drain as opposed to just the drain to simplify fabricationimplementation, though at the expense of potential improve-ment in series resistance.

Overall, a summary of the most important metrics areprovided as listed in Table I, drawing primarily from ITRS2013 HP specifications.

TABLE ICOMPARISON BETWEEN OPTIMIZED BULK DEVICE AND ITRS

SPECIFICATIONS

Parameter Simulated Value Specified Value

Leffective 15.5 nm 16 nmLmetallurgical 20 nm 20 nm

tox 522 Angstroms 600 Angstromsxjextension 9.6 nm OptimizedXjdeepSD

18.7 um OptimizedIon 0.555 mA/um 1.366 mA/umIoff 186 nA/um 100 nA/um

VTlin0.405V 0.306 V

VTsat 0.389V 0.219VDIBL 154 mV/V 134 mV/V

SS 121 mV/dec Optimized

III. MEETING TARGET SPECIFICATIONS

A. Design Considerations

During the initial device optimization, various designchoices were investigated to understand their impact.

1) Source Drain Extension: Firstly, shallow source drainextensions were included to improve gate control of thechannel compared to a deep source drain. The implants wereoptimized to minimize gate overlap while still keeping a highdoping concentration to improve on current.

2) Spacer Size: In order to determine the length of thesource drain extension, a spacer was used to move the sourceand drain further away from the gate, preventing subsurfacepunch through. It was found that 0.010 nm was the optimallength for the spacer.

3) Deep Source Drain: The source and drain doping wasoptimized to keep a relatively small Xj for reduced charac-teristic length, but heavy doping concentration was used toimprove on current.

4) Halo Distribution: To prevent sub-surface punchthroughwhen the device is in saturation, pocket implants were used. Apeak concentration of around 6e1018 was used as per ITRS.Several different halo shapes were considered by optimizingthe angle implant, dosage, and energy; however in the enda retrograde doping profile was preferred because it servedto suppress punchthrough while simultaneously maintainingsubthreshold slope.

5) Retrograde Doping Profile: Indium was used as animplantation ion because its heavy mass allowed a sharperretrograde doping profile compared to boron and BF2. Thelighter channel doping allows for pinning of the width of thedepletion layer, thus preventing subthreshold slope degradationwhen the device is in saturation. One drawback to usingindium is that it reaches its solid solubility limit at a lowerconcentration than boron, so the maximum active doping isdecreased, as illustrated in Fig 3.

6) Metal Workfunction: The workfunction of the metal wasselected to be 4.15 eV to shift the threshold voltage of thedevice to 0.2V as per ITRS requirements.

7) Gate Oxide: A high k dieletric was used, HFO2, witha k of 12.5 (insert reference here!), which reduces gatecapacitance, since it allows for a thicker oxide.

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Fig. 3. Doping beneath the channel illustrating the difference between activeretrograde dopants and implanted dopants.

B. Electrical Characterization and Performance

The device characteristics were plotted for this optimizeddevice as shown in Figures 4-5. From the transfer charac-teristics, some leakage current is observed when the deviceis in saturation. This could potentially be due to tunnelingcurrent between the source and drain near the channel. Somesubthreshold slope degradation is observed as well betweenthe linear and saturation region, indicating that there may bepunchthrough through the device. This could be improved byoptimizing the halo implants or else improving the retrogradedoping profile. The DIBL was measured to be 154 mV/V andcould be improved by reducing the LDD or drain junction size.

Fig. 4. Transfer characteristics of the optimized device. It is observed thatthe device saturation current was 0.555 mA/um and the off current was 186nA/um.

The output characteristics illustrate a linear increase in drainsaturation current, indicating that we are indeed operating inthe short channel regime.

Fig. 5. Output characteristics of the device illustrate short channel effect.

IV. SERIES RESISTANCE ANALYSIS

Series resistance was measured by plotting the electricalpotential across the device from contact to channel, as shownin Figure 6. Resistance for each component was found by mea-suring the drop in potential across each resisitive component,and then dividing by the saturation current. A separate verticalcross section was taken of the device to calculate the contactresistance. In the initial device, the major resistance valueswere measured as shown in Table II.

Fig. 6. Electrostatic potential along a cross section of the S/D, extension,and channel of the device. Region 1 represents the spreading resistance fromthe S/D to the LDD, Region 2 is the LDD sheet resistance, and Region 3represents the spreading and tip resistance. Resistance of the deep sourcedrain was found to be negligible.

From Table II, it can be seen that the largest contribution ofseries resistance was the tip resistance. This can be consideredto be a combination of the contributions of both currentcrowding and also accumulation resistance from the LDDto the channel. To reduce this resistance, several methods

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TABLE IIMEASURED SERIES RESISTANCE VALUES FOR THE INITIAL DEVICE

Resistance Value (Ω− um)

Contact Resistance 54.05Deep Source Drain Diffusion < 1

Spreading from Source Drain to Extension 42.34Shallow Extension Diffusion 11.8

Tip Resistance 498.16

were tried, primarily modifying the LDD doping concentrationand LDD junction doping abruptness. The effect of dopingconcentration is shown in Fig 7, where it is generally seenthat a lower doping concentration in the LDD appears todecrease the difference in elecrostatic profile. For similarconditions of diffusion, a lower difference in doping profilewould effectively reduce junction capacitance and thus reducespreading resistance. On the other hand, the steeper dopingprofile of the highly-doped LDD would reduce the tip re-sistance of the device. Overall, however, it can be seen thatspreading resistance appears to be the greater contributor tothe difference in electrostatic potential.

Fig. 7. Electrostatic potential plots of similar devices from SentaurusStructure Editor with different maximum doping concetrations. For a highLDD doping (1e22), tip resistance between Y=0.005 to Y=0.008 is reduced,while the spreading resistance from Y=0.01 to Y=0.015 is increased. Sincespreading resistance appears to dominate, a higher doping concentration maybe preferred.

Analysis of the junction steepness on tip resistance wasalso directly analyzed by varying the slope of the gaussiandoping profile distribution via a Gaussian Spread Factor, asshown in Figure 8. A small spreading factor represents aGaussian distribution with a small variance or sigma. In thiscase, the slope in the LDD near the metallurgical junction islocated immediately below Y=0.01. Here it can be seen that asmall Gaussian Spread Factor will result in a less steep slope,again indicating that tip resistance is improved. However, againthe spreading resistance displays a tradeoff in overall seriesresistance.

V. PROCESS IMPLEMENTATION OF SERIES RESISTANCEIMPROVEMENTS

In order to reimplement the series resistance studies on thelightly doped drain into a process simulation, Antimony was

Fig. 8. Electrostatic potential plots of a Sentaurus Structure Editor device withdifferent doping junction abruptness. It is seen that the more abrupt junctionhas a reduced tip resistance and increased spreading resistance.

used as the ionized dopant in the LDD instead of Arsenic. Theheavier atomic number of antimony would theoretically reducethe diffusion coefficients and therefore produce a more abruptjunction. However, it was found that the diffusion of Antimonycould not reach as high net doping concentrations as Arsenic,resulting in minor degradation of device on current. Theimpact on series resistance can still be analyzed. Comparingthe doping profiles in Fig 9 to the electrostatic potential plot inFig 10, it can be seen that there is a relatively steep junction inthe Antimony LDD device between the drain and the extensionat approximately Y=-0.015 um. Here, it can be seen that whilethe tip resistance may have decreased, the overall electrostaticpotential drop for the antimony LDD is higher, indicating ahigher series resistance. This can be explained as a functionof spreading resistance, which would be increased due to thelimited amount of carriers that are available to conduct current,causing some crowding at the source-drain and LDD interface.

VI. DISCUSSION

Comparing the three devices produced between the originaloptimized device, the series-resistance optimized device, andthe re-implementation, we can see that the overall devicecharacteristics were not significantly different from each other.The Sentaurus Process devices both have some leakage insaturation, indicating that there are some potential leakagepaths that are not captured in the Sentaurus Device simu-lation. The Sentaurus Device simulation also has a poorersubthreshold slope and degraded on current; this may beimproved by further refining the simulation source drainextension and retrograde doping profile to match that of theSentaurus Process structures. The implementation of Arsenicin the structure was not found to be particularly effective,since device characteristics were slightly degraded and series

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Fig. 9. Doping concentration of Antimony-doped LDD vs an Arsenic-dopedLDD.

Fig. 10. Electrostatic potential plots comparing similar devices but usingAntimony for the LDD instead of Arsenic.

resistance was not particularly improved. Further methods ofimproving the series resistance can be explored in the future.

Due to time constraints a number of variations on seriesresistance were not studied and implemented. However, itwould be expected that making additional tuning to the xj,ext,doping abruptness, and doping concentration of the LDDwould be able to improve tip resistance. Compared to theoriginal optimized device, most of the changes made in thestudies of series resistance may also have an impact on deviceperformance, for example increasing the LDD junction steep-ness may improve tip resistance but also increase potentialhot carrier effects. Therefore careful optimization consideringseries resistance from the beginning of the design may result

Fig. 11. Comparison of device characteristics for: A) The original optimizedSentaurus Process device that aimed to meet ITRS specifications; B) TheSentaurus Structure device that was optimized to adjust the impact ofseries resistance; C) The re-implemented Sentaurus Process device using anantimony LDD that aimed to improve series resistance based on results fromdevice B.

in a better final device design.

VII. CONCLUSION

Through analysis of various devices, a deeper understandingof the tradeoffs between different components of series resis-tance and device performance were understood. Since overalltip and spreading resistance dominate in series resistance of adevice, it is crucial for device engineers to carefully considerthe tradeoffs between device performance and different formsof series resistance before developing device structures. Withcareful optimization, it is possible to develop devices thatboth perform well and minimize parasitics. Some examplesof future investigation can include studying the impact ofa one-sided LDD, raised source drain,or improved silicidedeposition on series resistance and device performance, as wellas implementing additional process steps to emulate studiesconducted on the series resistance.

REFERENCES

[1] K. Ng and W. Lynch. The Impact of Intrinsic Series Resistance onMOSFET Scaling, Transactions on Electron Devices. March 1987.

[2] K. Seong-Dong and C. M. Park, Advanced Model and Analysis of SeriesResistance for CMOS Scaling Into Nanometer Regime - Part I, IEEETransactions on Electron Devices. March 2002.

[3] J. Kedzierski et al, Complementary silicide source/drain thin-body MOS-FETs for the 20nm gate length regime, IEDM. 2000.

[4] S. Chang et al, High Performance and High Reliability 80nm LengthDTMOS with Indium Super Steep Retrograde Channel, IEDM. Dec2000.

[5] A. Gat et al, Physical and electrical properties of laser-annealed ion-implanted silicon, Applied Physics Letters. 1977.