7/29/2019 High-Performance ARM Processor Sub-System
Implementation
2/3
CS-PD-001
The Problem Statement
Customer wanted to improve the performance of the existing ARM
processor sub-system by40% which will create a product
differentiation and enable the customer to target the device
for
the high-end smart phone market from the current mid-level smart
phone market, thereby
extending the life span of the product.
The challenge was to meet the performance requirements using the
same process technology
node, maintain the same area, power grid and the pin-out for the
hard-macro as in the existing
SoC, for there are no other changes being made to the design.
The requirement was that the
performance enhanced processor core sub-system will have to be
an exact drop-in, to the
existing processor core sub-system in the SoC.How C2SiS
HelpedC2SiS team took complete ownership of the Silicon Engineering
of the processor core sub-system by thoroughly understanding the
performance requirements, different power modes ofoperation and any
specific restrictions in the timing optimization across all process
corners. Asthe area of the macro in the SoC context cannot be
changed, C2SiS team worked with thecustomer engineering team to
understand the changes that can be made to the design in orderto
remove features that are not being used, so as to maintain a
similar area after the 40%improvement in the performance of the
processor core.
C2SiS team worked on the following aspects as part of the
physical implementation and tape-out of the design:
Reviews of the architecture of the ARM processor sub-system and
the data flow
Removal of the software debugger block based on the initial
synthesis and congestionanalysis to maintain the area requirements
after the 40% performance improvement
Regressions for the modified RTL using the existing test
cases
Several synthesis trials 26 different synthesis optimizations
were tried with different Vtcell usage, PVT
(Process-Voltage-Temperature) corners along with uncertainty
margins
to nail down the final synthesis strategy
Extensively analyzed the usage of the library cells in the
design and worked with thecustomers library design team to
customize the cells for specific delay requirements
Several floorplan trials 22 different floorplan optimizations
were tried with differentmemory locations, placement of logic
clusters for better timing and least congestionalong with
uncertainty margins, appropriate placement blockages for routing
channels to nail down the final floorplan for the design
Placement through physical clustering and boundso Manual tweaks
to placement along with path based optimization
Clock-Tree-Synthesis with appropriate Vt cell usageo Appropriate
skewing techniques for better timing optimizationo De-cap wrappers
for minimizing the dynamic IR dropo Shield routing for the clock
networks to minimize the significant cross-talk impact
Routing and routing optimization across multiple modes and
corners
Power analysis and Power grid verification and repair Static and
Dynamic
Integration into the SoC
7/29/2019 High-Performance ARM Processor Sub-System
Implementation
3/3
CS-PD-001
Timing Closure both at the core level and in the context of the
SoC
Physical Verification and Tape-out
Business Impact
Meeting the Performance Specification: C2SiSs team completed the
physicalimplementation and tape-out of the processor by beating the
performance targets set forth forthe design. Beating the
performance specification of the design, enables the customer to
extendthe life-span of the product and look at alternate market
segments for the same device.
First Silicon Success: C2SiS teams flawless design execution by
working diligently inunderstanding the customers sign-off
requirements and thoroughly validating every step of theprocess
upfront, enabled the design closure without any bugs in first
silicon.
TAT Reduction: C2SiS teams extensive know-how of the ARM
processor core architectureand the experience in the process
technology node being used for the design, helped inmanaging and
successfully taping out the design, a week ahead of the customer
planned tape-out date.
For further information, please
contact:____________________________________________________________________________Concept2Silicon
SystemsVisit us athttp://www.concept2silicon.comCopyright 2011
Concept2Silicon Systems
All rights reserved.
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