High-Performance Analog-to-Digital Converters: Evolution ... · High-Performance Analog-to-Digital Converters: Evolution and Trends Pedro Figueiredo [email protected] Topical Workshop

High-Performance Analog-to-Digital Converters: Evolution and Trends

Pedro Figueiredo

[email protected]

Topical Workshop on Electronics for Particle Physics 2015

28th September 2015

ADC performance: Evolution

ADC architectures: Relationships, Speed, Performance

Technology Scaling: Difficulties and Opportunities

Synopsys digitally calibrated Pipeline and SAR ADCs

Outline

2

Translates an analog input signal into its binary coded representation (N bit), at a certain rate (fs)

The Analog-to-Digital Converter

3

Sampling

vI

t

Quantization

vIQ

t

Clock Signal (fs)

Quantization Step (VLSB)

Encoding

011011101010010101111000010000000000

vIS

t

TS = 1/fs

vI Energy Efficiency

Data from Prof. Murmann’s Survey [1]

Evolution of ADC performance

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

20 30 40 50 60 70 80 90 100 110 120

P/fs

[p

J]

SNDR [dB]

Conversion Energy vs SNDR

VLSI 1997-2004

ISSCC 1997-2004

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

20 30 40 50 60 70 80 90 100 110 120

P/fs

[p

J]

SNDR [dB]


VLSI 1997-2004

ISSCC 1997-2004

ISSCC 2005-2014

VLSI 2005-2013

~80x Energy Efficiency improves 2x [2]:- Low/Medium Resolution: every ~1.6 yrs- High Resolution: every ~5.4 yrs

4

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

20 30 40 50 60 70 80 90 100 110 120

P/fs

[p

J]

SNDR [dB]


VLSI 1997-2004

ISSCC 1997-2004

ISSCC 2005-2014

VLSI 2005-2013

FOMw=1 fJ/conv-step

FOMw=10 fJ/conv-step

Walden’s FOM=P/(2ENOB.fs)


Assumptions: 1 extra bit P increases 2Power scales linearly with fs

Range of applicability

Best FOM: 10/12b 40kS/s-4MS/s low VDD

6-8b >1 GSPS ADCsLower power efficiency

5

Power per conversion-step as a function of fs


1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11

P/2

^EN

OB

[W

/co

nve

rsio

n-s

tep

]

fs [Hz]

Power/Conversion-step vs fs

VLSI 1997-2004

ISSCC 1997-2004

FOMw=1 fJ/conv-step



FOMw=1 pJ/conv-step

7 pJ/conv.step

0.5 pJ/conv.step

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11

P/2

^EN

OB

[W

/co

nve

rsio

n-s

tep

]

fs [Hz]

Power/Conversion-step vs fs

VLSI 1997-2004

ISSCC 1997-2004

ISSCC 2005-2014

VLSI 2005-2013

FOMw=1 fJ/conv-step



FOMw=1 pJ/conv-step

100 fJ/conv.step

10 fJ/conv.step

1 fJ/conv.step

But still a significant number ofpublications in this

frequency range

Many more high frequency ADCs(though max reported fs increased only ~2x)

Record FOM values- Wireless Sensor Networks

- Internet of Things6

Some of Synopsys ADC implementations


0.01

0.1

1

25 30 35 40 45 50 55 60 65 70

Technology [nm]

FOM

/FO

MR

ef

AD

C

2.5x

1.7x

5x

Ref. ADC: 10 bit 80 MS/s Pipeline ADC

12 bit 200 MS/s Pipeline ADC with digital calibration

12 bit 80 MS/s SAR ADC with digital calibration

Estimate

7

ADC architectures typically presented as different and (somewhat) unrelated alternative solutions…

• … each with its own pros and cons …

• … each best suited to certain resolution and fs

Here we will focus on fundamental operations and how they are related [3]

ADC architectures

8

ADC fundamental operations: sampling and quantization

Single bit ADC:

Multi-bit ADC:

Single and Multi-bit ADCs

9

Conversion Process:Search the DAC output that

best approaches the sampled input...

... i.e. minimize the residue ...

... and then use bout=ddac

SAR ADC is the direct implementation of the elementary multi-bit architecture

Very efficient:• Re-uses same hardware in each cycle

• Necessary number of cycles grows linearly with resolution: N cycles for N bits

• Performance limited by DAC nonlinearity

SAR ADC

S/HvI

q

DACddac

bout

+-

VREF

Successive

Approximation

Register

Output

Registers

10

If DAC provides several outputs simultaneously: possible to search several codes in parallel

Different codes are searched by different paths Faster: N/NC cycles to complete a conversion Number of parallel paths: 2Nc

Differences between them degrade performance Examples: 2 and 3 bit per cycle SAR ADCs [4,5]

Speed Increase: Parallelization in the code-search process

11

S/HvI q

DACddac

bout

+-

VREF

Multi-bit quantizer

residue

NC bit quantizer

S/HvI

DAC

+ -

++ E

nc

od

ing

an

d C

on

tro

l

1

2Nc

-1

2Nc

bout

-

-

VREF

Multi-step Cyclic Subranging ADC

Taking this parallelization to the limit: NC=N

All codes are searched simultaneously

Flash ADC

Speed Increase: Parallelization in the code-search process

12

Another possibility is pipelining:

• Quantization process is divided in several steps that occur in a pipelined fashion:

o Typically, quantizers have low resolution low parallelization in the code search process

• At a given clock cycle, the ADC is quantizing several different samples

Speed Increase: Pipelining

13

Pipelined ADCs: Practical considerations lead to the structure shown below.

Each stage constituted by:

• Quantizer

• Residue calculator/amplifier block – MDAC

oResidue: error signal corresponding to what is left to quantize


MDAC

S/HvI

Quantizer 1

N1 bits

N1 Quantizer k

Nk bits

bout

Stage 1 Stage k

+-

Residue 1

VREF

S/H

Quantizer 2

N2 bits

N2

Stage 2

+-

Residue 2Residue

k-1

2N1-1 2

N2-1

S/H

MDAC

S/H S/H

DAC

N1 bits

DAC

N2 bits

14

Quantizer specifications are relaxed (low resolution)

MDAC non-idealities limit performance

• Gain error of S/H, DAC and residue amplifier limit overall linearity

• In practice this translates into stringent gainspecifications of the amplifier implementing the MDAC


15

Non-linearity of the DAC(s) limits performance Additionally:

• Use of Pipelining Residue Amplification Relaxed Quantizers

Performance limited by amplification blocks

• Use of Parallelization in the code search process Quantizer only ADCs Many parallel paths

Performance limited by differences between

parallel paths (offsets)

SAR ADCs use none of the above: limited only by DAC non-linearity

Speed Increase Technique Limitations

16

Another parallelization possibility is time-interleaving

Different samples processed by independent paths• Differences of offset, gain, sampling instants degrade

performance

Unit ADCs use the parallelization/pipelining techniques previously discussed

Nch ADCs fs increases Nch times

Parallelization: in time domain

17

Example: 6b 90GS/s ADC with64 unit SAR ADCs [6]

Technology Scaling – the bad• Reduction of gm/gds

• Headroom limitations caused by VDD reduction• Bad CMOS switches• Higher variability• Transistor properties and matching more and more

dependent on surroundings• Higher interconnect delays

… and the good• Faster devices• Digital processing is increasingly powerful, cheap and low

power - available to overcome limitations in the analog sub-blocks of ADCs

ADC implementations in advanced technologies

Digitally Assisted Analog

18

Typical 1.5b MDAC circuit• f1: Sampling f2: Residue Amplification

Negative feedback around a high-gain amplifier sets residue amplification gain very accurately

Increasingly difficult to attain high gain in nanoscale technologies

Class A amplifiers not power efficient

ADCs with residue calculation/amplification

CF=C

vI

-

+b×VREF

CR=C

f1

f1

f2

f2

f1'

f1: sampling phase

f2: amplification phase

vO

f1

A0

b={-1,0,+1} depending

of quantizer decision

CLp

f2

f2

Next stage

inext stage

19

Techniques to improve power efficiency:

• Opamp switching reduces power consumption during reset phase, but introduces speed or headroom limitations [7-9]

• Opamps can be shared between stages in order to ensure they are being used at all times [10-13]

• Class AB amplifiers [14] may be used, but are more complex and have limited effectiveness


20


• Use of low gain amplifiers and digital calibration

• Opamp substituted by comparator + current source[15,16].

oNo stability and gain-bandwidth product limitations

o Stops consuming when the desired voltage is reached


21


• Open loop amplifiers based on transconductances[17,18]:

oGain is parasitic and PVT dependent, and non-linearity is non-negligible. Complex digital calibration required

• Open loop amplifiers that are not based on transconductances:

– Parametric amplification [19,20]

– Bucket brigade circuits [21,22]

o Even larger non-linearity and dependence of parasitics/PVT

oDigital calibration complexity is further increased


22

Calibration of amplifier finite gain and capacitor mismatches

• Fast startup time and robustness against VDD/Temp variations

Stages with reduced output swing

Opamp switching technique with no speed or signal swing limitations

.

12b 200MS/s digitally calibrated pipeline ADC

1.5 bitCalibrated

Stage 1

1.5 bitCalibrated

Stage 2

1.5 bitCalibrated Stage 10

1.5 bitUncalibrated

Stage 1

1.5 bitUncalibrated

Stage 2

1.5 bitUncalibrated

Stage 3

Digital Calibration and Error Correction

2

b[2]

ts[2]

2

b[1]

ts[1]

2

b[10]

ts[10]

2

b[11]

2

b[12]

2

b[13]

3

bout

vI

12

3 bit Flashb[14]

23

Gain error of S/H, and residue amplifier, and mismatches of the DAC cause GEi and GEo1

Digital gain calibration: Multiply by 1/GEo

.


Ideal

MDAC

DAC

N1 bits

2N1-1+

-vI

Quantizer 1

N1 bits

N1

Stage 1

VREF

Nbck bit

Backend

ADC

bout,lsb+

Nbck

bout

N

bout,msb

vO1

2Nbck-1

S/H

S/H GEoGEi

1/GEo~

24

Determination of digital coefficients


Foreground(Fast Startup)

Background(Adapt coef. as

VDD/Temp varies)

25

U.S. Patent8 742 961

Capacitor CD:

• Injects the Pseudo-Random Binary Sequence on the central segment

• Shifts L/R segments in order to reduce signal swing

o Lower amplifier non-linearity

oRelaxed settling specifications


26U.S. Patent8 797 196

Amplifier:

• Single stage, high-swing A016dB only

• Switching of CB reduces power consumption in f1

oNo speed or signal swing limitations


IBIAS

vdiode vB

vBCMvBCM

fB

fA

S1

CB

vOPvON

vOP

vON

VCM

Common-Mode

Feeback Network

vIN vIP

fA

fB

f2

Amplification

Phase

vB

vdiode

VDD

VDD

0

U.S. Patent8 610 422

27

Measurement results:

Calibration off Calibration on


28

No need for highly linear or gain accurate blocks better adapted to nanometer technologies

Non-linearity of the DACs inside the quantizers:

• Caused by random deviations on its constitutive elements

• Matching improved by using devices with larger area

oResistive ladder DACs: increased parasitics

o Switched capacitor DACs: sets a minimum limit for the value of the capacitors (as does noise)

• May also be addressed by digital calibration

Quantizer-only ADCs

29

Performance of flash/subranging/time-interleaved SAR ADCs limited by comparator offsets

Add pre-amplifier with offset sampling

• Static consumption

• Non-negligible residual offset [23]

Quantizer-only ADCs

30

Offset calibration:• Programmable capacitor or current source arrays in

dynamic comparator [24,25]

• Auxiliary diff pair and switched capacitor integrator [23,26]o No speed reduction

o Marginal power increase

o High calibration-range/calibration-step

ratio

o (Almost) perfect offset removal

Quantizer-only ADCs

31

Averaging [23,27,28]

• Offset of comparators is a weighted sum of several amplifiers

• Offsets become correlated

• Lower area devices may be used

Quantizer-only ADCs

R0 R0 R0 R0 R0 R0R1

R1

R1

R1

R1

R1

VDD

ISS ISS ISS

-VREF 0 VREFvIvI vI

R0 R0R1

R1

ISS

vI

R0 R0R1

R1

ISS

vI-kVREF kVREF

0-1-k 1 k

AveragingNetwork

32

Stochastic flash ADCs [29,30]:

• Fully synthesized in a digital flow

• >>2N minimum size comparators with the same VREF

• Output code obtained by counting the number of ‘1’

• Nonlinear transfer function: Gaussian cumulative distribution Linearization through digital calibration

Quantizer-only ADCs

33

Asynchronous architecture.

Operation independent of clk duty cycle

Low noise fully dynamic comparator

Use of time-interleaving: 12b 160MS/s and 320MS/s ADCs

12b 80MS/s digitally calibrated SAR ADC

Sw-CapacitorS/H+ Subtractor+

DACvI

bout

clk

Data Register

Raw digital code

Timing and State Machine

Digital Calibration

residue

34

DAC with capacitive dividers avoids the exponential increase on the number of (small) unit capacitors

Digital calibration: addresses random capacitor mismatches and sensitivity to parasitics in the capacitive divider nodes.• Measures capacitor ratios at startup

• Corrects the raw code provided by the SAR


35

Measurement results:

Calibration bypassed Calibration on


36

Reviewed ADC performance evolution in the last 10 years

Main trend: energy efficiency improvement

Conclusions

37

ADC architectures

• SAR ADC is the direct implementation of the elementary multi-bit ADC architecture

• Speed increase: use parallelization in the code-search process or pipelining

• This yields ADCs based only on quantizers, and those based on residue amplification for further quantization

o…which have significantly different trade-offs

• Speed also increases by parallelizing in time-domain: time-interleaving

Conclusions

38

Conclusions

Reviewed challenges/benefits introduced by technology scaling

Digitally Assisted Analog trend: • Relaxed analog circuits’ complexity…

• …traded favorably by extra digital complexity

Disclosed a few details about Synopsys 12b digitally calibrated pipeline and SAR ADCs• Illustrated how the use of digital calibration can

dramaticaly improve performance

39

1. B. Murmann, http://www.stanford.edu/~murmann/adcsurvey.html

2. G. Manganaro, Advanced Data Converters. Cambridge University Press, 2012.

3. P. Figueiredo, “Recent advances and trends in high-performance embedded data converters” in High Performance AD and DA Converters, IC Design in Scaled Technologies, and Time-Domain Signal Processing. P. Harpe, A. Baschirotto, and K. Makinwa, Ed. Springer, 2014.

4. H. Hong et al., “A 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement,” in Proc. ISSCC Dig. Tech. Papers, pp. 470-471, Feb. 2013.

5. C-H. Chan et al., “A 5.5 mW 6b 5GS/s 4x-interleaved 3b/cycle SAR ADC in 65nm CMOS,” in Proc. ISSCC Dig. Tech. Papers, Feb. 2015.

6. L. Kull et al., “A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS,” in Proc. ISSCC Dig. Tech. Papers, pp. 378-379, Feb. 2014.

7. J. Crols and M. Steyaert, “Switched-Opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages,” IEEE J. of Solid-State Circuits, pp. 936-942, Aug. 1994.

8. H. Kim, D. Jeong, and W. Kim, “A 30mW 8b 200MS/s pipelined CMOS ADC using a switched-opamptechnique,” in Proc. ISSCC Dig. Tech. Papers, pp. 284-285, Feb. 2005.

9. H. Choi et al., “A 15mW 0.2mm2 10b 50MS/s ADC with wide input range,” in Proc. ISSCC Dig. Tech. Papers, pp. 842-843, Feb. 2006.

10. K. Nagaraj et al., “A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers,” IEEE J. of Solid-State Circuits, pp. 312-319, Mar. 1997.

11. B.-M. Min et al., “A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC,” IEEE J. of Solid-State Circuits, pp. 2031-2039, Dec. 2003.

References

40

http://www.stanford.edu/~murmann/adcsurvey.html

12. L. Sumanen, M. Waltari, and K. Halonen, “A 10-bit 200-MS/s CMOS parallel pipeline A/D converter,” IEEE J. of Solid-State Circuits, pp. 1048-1055, Jul. 2001.

13. Y. Yao, D. Ma and F. Dai, “A 12-bit interleaved opamp-sharing pipeline ADC for extreme environment applications,” in Proc. IEEE ICSICT, pp. 394-396, Nov. 2010.

14. J. Kim and B. Murmann, “A 12-bit, 30-MS/s, 2.95-mW pipelined ADC using single-stage class-AB amplifiers and deterministic background calibration,” in Proc. ESSCIRC, pp. 378-381, Sep. 2010.

15. L. Brooks and H.-S. Lee, “A 12b 50MS/s fully differential zero-crossing-based ADC without CMFB,” in Proc. ISSCC Dig. Tech. Papers, pp. 166-167, Feb. 2006.

16. D.-Y. Chang et al., “A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13m CMOS with 74dB SNDR,” in Proc. ISSCC Dig. Tech. Papers, pp. 204-205, Feb. 2014.

17. B. Murmann and B. Boser, "A 12-bit 75 Ms/s pipelined ADC using open-loop residue amplifier," IEEE J. of Solid-State Circuits, pp. 2040-2050, Dec. 2003.

18. F. Goes et al., “A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipeline ADC in 28nm CMOS,” in Proc. ISSCC Dig. Tech. Papers, pp. 200-201, Feb. 2014.

19. P. Figueiredo and J. Vital, “The MOS capacitor amplifier,” IEEE Trans. Circuits Syst. II, pp. 111-115, Mar. 2004.

20. J. Oliveira et al., “An 8-bit 120-MS/s interleaved CMOS pipeline ADC based on MOS parametric amplification,” IEEE Trans. Circuits Syst. II, pp. 105-109, Feb. 2010.

21. M. Anthony et al., “A process-scalable low-power charge-domain 13-bit pipeline ADC,” in Proc. of the IEEE Symp. on VLSI Circuits, pp. 222-223, Jun. 2008.

22. N. Dolev, M. Kramer, and B. Murmann, "A 12-bit, 200-MS/s, 11.5-mW pipeline ADC using a pulsed bucket brigade front-end", in Proc. of the IEEE Symp. on VLSI Circuits, pp. 98-99, Jun. 2013.

References

41

23. P. Figueiredo and J. Vital, Offset Reduction Techniques in High-Speed Analog-to-Digital Converters, Springer, 2009.

24. G. Plas. S. Decoutere, and S. Donnay, “A 0.16pJ/conversion-step 2.5mW 1.25GS/s 4b ADC in 90nm digital CMOS process,” in Proc. ISSCC Dig. Tech. Papers, pp. 566-567, Feb. 2006.

25. T. Danjo et al., “A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS,” in Proc. of Int. Symp. on VLSI Design, Automation and Test, pp. 1-4, Apr. 2012.

26. P. Figueiredo et al., “A 90nm CMOS 1.2 V 1GS/s two-step subranging ADC,” in Proc. ISSCC Dig. Tech. Papers, pp. 568-569, Feb. 2006.

27. K. Kattmann and J. Barrow, “A technique for reducing differential non-linearity errors in flash A/D converters,” in Proc. ISSCC Dig. Tech. Papers, pp. 170-171, Feb. 1991.

28. P. Figueiredo and J. Vital, “Averaging technique in flash analog-to-digital converters,” IEEE Trans. Circuits Syst. I, pp. 233–253, Feb. 2004.

29. S. Weaver et al., “Stochastic flash analog-to-digital conversion,” IEEE Trans. Circuits Syst. I, pp. 2825–2833, Nov. 2010.

30. S. Weaver et al., “Digitally synthesized stochastic flash ADC using only standard digital cells,” IEEE Trans. Circuits Syst. I, pp. 84–91, Jan. 2014.

References

42

43

[email protected]

44

Documents

High-Performance Analog-to-Digital Converters: Evolution ... · High-Performance Analog-to-Digital Converters: Evolution and Trends Pedro Figueiredo [email protected] Topical Workshop