High-Level Synthesis with LabVIEW FPGA - Synthesis with LabVIEW FPG  LabVIEW, LabVIEW Real-Time •Multicore

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  • ni.com

    High-Level Synthesis with LabVIEW FPGA

    National Instruments

  • 2 ni.com

    Introduction

    NI RIO technology

    LabVIEW FPGA & IP Builder

    RIO Hardware Platform

    Application

    Agenda

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    An Ideal Embedded Architecture

    Floating-point processing

    Communications Multicore technology

    High-speed control & processing

    Reconfigurable hardware

    Reliability

    Low-level access to hardware

    Custom timing & triggering

    Modular I/O

    I/O FPGA Processor

    I/O

    I/O

    I/O

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    I/O

    The Challenge

    FPGA Processor

    I/O

    I/O

    I/O

    Low-level tools Verilog & VHDL

    Fixed-point algorithms

    Custom drivers and middleware

    Multicore programming challenge

    Custom timing for different types of I/O

    Custom digital interface/buses

  • 5 ni.com

    Build vs. Buy

    Build

    Custom HW/SW solution

    Use a lot of in-house resources

    Ability to get exactly what you want

    Buy

    Off-the-shelf HW/SW solution

    Use less resources because systems are pre-built

    Often get more than you need

  • 6 ni.com

    Volume per year

    Cost

    100 1000 10000

    Buy

    Build

    Now with new versions of sbRIO: Gives the BUILD customer a cheaper OTS solution Gives the BUY customer a more flexible OTS solution

    Build vs. Buy

  • 7 ni.com

    Enet USB RTOS

    Analysis

    Logging Comm

    Multicore

    Analog I/O Digital I/O

    Comm I/O

    3rd party I/O

    Motion I/O

    IPNet

    Analysis IP

    3rd party IP

    Control IP

    Comm IP Timing IP

    Packaged Board-Level

    NI RIO Technology Platform

    Processor FPGA I/O

    NI RIO Hardware

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    Enet USB RTOS

    Analysis

    Logging Comm

    Control

    Analog I/O Digital I/O

    Comm I/O

    3rd party I/O

    Motion I/O

    IPNet

    Analysis IP

    3rd party IP

    Control IP

    Comm IP Timing IP Bus IP

    LabVIEW FPGA Fixed-point processing Built-in functions for analysis, control and communications Ability to integrate VHDL

    Drivers and middleware Pre-built I/O and communication drivers DMA, single-point communication between processor and FPGA Ability to create custom I/O

    LabVIEW, LabVIEW Real-Time Multicore programming Built-in functions for analysis, control and communications Ability to integrate C code and text-based math

    Processor FPGA I/O

    NI RIO Software

  • 9 ni.com

    NI RIO Software Benefits

    Graphical programming for multicore/real-time processors

    and FPGAs

    Advanced signal processing and control algorithms

    Built-in drivers and middleware for I/O and

    communication

    Open for integration of existing code/IP

  • 10 ni.com

    LabVIEW

    C, C++

    LabVIEW

    FPGA

    Vivado HLS

    VHDL

    Programming

    HLS(High-Level Synthesis)

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    Counter Analog I/O I/O with DMA

    LabVIEW FPGA VHDL 66 Pages ~4000 lines

    LabVIEW FPGA

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    VHDL Generation Analysis

    Logic Reduction

    Place and Route

    Timing Verification

    Generation

    Download/Run

    LabVIEW FPGA Code FPGA Logic Implementation

    Translation Optimization Synthesis Bit Stream

    LabVIEW FPGA

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    LabVIEW FPGA IP Builder

    Add-on Tool for LabVIEW FPGA

    Rapidly develop high performance algorithms for FPGAs

    Quickly explore design tradeoffs using directives

    Reuse IP to meet new design requirements

    LV FPGA IP Builder VI LV FPGA VI

    Manual optimization required Optimization using high-level synthesis

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    Create Algorithm VI

    Specify Directives

    Generate performance estimation

    Generate Design

    Use within top-level LV

    FPGA VI

    Use dataflow programming Limited functions palette

    LabVIEW FPGA IP Builder User Flow

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    Create Algorithm VI

    Specify Directives

    Generate performance estimation

    Generate Design

    Use within top-level LV

    FPGA VI

    LabVIEW FPGA IP Builder User Flow

  • 16 ni.com

    Create Algorithm VI

    Specify Directives

    Generate performance estimation

    Generate Design

    Use within top-level LV

    FPGA VI

    LabVIEW FPGA IP Builder User Flow

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    Create IP VI

    LabVIEW FPGA IP Builder User Flow

    Create Algorithm VI

    Specify Directives

    Generate performance estimation

    Generate Design

    Use within top-level LV

    FPGA VI

    Generate HDL

    Choose VI and Directives

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    LabVIEW FPGA IP Builder User Flow

    Create Algorithm VI

    Specify Directives

    Generate performance estimation

    Generate Design

    Use within top-level LV

    FPGA VI

    Integrate into Single-Cycle Timed Loop Add I/O, DMA FIFOs, Host Communication, etc.

  • 21 ni.com

    Packaged Board-Level

    NI RIO Hardware

    NI RIO Hardware Benefits

    Reconfigurable, off-the-shelf hardware

    Breadth of high-quality I/O (analog, motion, vision, RF,)

    Variety of packaged and board-level form factors

    Open platforms for integration with 3rd-party hardware

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  • 22 ni.com

    NI RIO Technology Curve

    CompactRIO

    Single-Board RIO

    Multicore CompactRIO

    PC RIO / R Series

    PXI / FlexRIO

    Processor FPGA I/O

    I/O

    Custom I/O

    I/O

    Deploy

    Perfo

    rmance

  • 23 ni.com

    CompactRIO

    Enet

    USB Analysis

    Logging Comm

    Control

    Analog I/O Digital I/O

    Comm I/O

    3rd party I/O

    Motion I/O

    IPNet

    Analysis IP

    3rd party IP

    Control IP

    Comm IP Timing IP

    -40 to 70 deg C Hardware and OEM Services Rugged Certifications/Ratings Up to 8 I/O Slots

    VxWorks RTOS

    (Xilinx Virtex/Spartan Class) (Industrial/Embedded Class) (Real-Time, Freescale) Processor FPGA I/O

    Packaging

    Most rugged platform

    Compact size, -40 to 70 C

    Industrial and Embedded I/O

    Analog, digital, motion, communication,

    Integrated FPGA in chassis

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    CompactRIO

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    Extreme Ruggedness

    -40 to 70 C temperature range 50g shock, 5g vibration

    Low Power Consumption

    9 to 35 VDC power, 7-10W

    Real-Time Processor , , , (Maximum Specification) CPU Intel i7 1.33 GHz RAM 2 GB DDR3 Storage 32 GB Enet, RS232, USB

    I/O Modules I/O I/O

    Reconfigurable FPGA 40MHz I/O Xilinx Spartan-6 LX150

    CompactRIO

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    10.3 x 9.7cm

    USB

    Ethernet

    RS232

    CAN

    RIO Real-Time

    FPGA FPGA

    RIO Mezzanine Card (RMC)

    FPGA USB

    Single-Board RIO

  • 27 ni.com

    RIO Architecture & NI LabVIEW

    NI Single-Board RIO NI CompactRIO PC RIO/R Series PXI RIO/FlexRIO

    Processor

    Smart Grid Renewables Life Sciences Industrial Control

    FPGA

    I/O

    I/O

    I/O

    I/O

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    Embedded Design Industrial Control &

    Measurements Test &

    Communications

    Embedded prototyping a Medical devices Renewable Energy Robotics

    Machine prototyping Industrial control Optimized automation

    RF, wireless and custom test Hardware-in-the loop (HIL)

    NI RIO Applications and Industries

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  • 29 ni.com

    NI LabVIEW RIO Evaluation Kit

    RIO Evaluation hardware

    400 MHz Real-Time Controller

    Ethernet, CAN, USB, SDCard,

    RS232 & RS485 serial ports

    AI, AO, DIO, LCD Screen

    Step-by-Step Tutorials

    Cables and accessories

    90-day extended evaluation

    version of NI LabVIEW, Real-Time and FPGA