High Level IC Designl · Hauptseminar: System Design using SystemC ChipDesign.ppt © Fraunhofer IIS, 2005 page 3 IIS Fraunhofer Institut Integrierte Schaltungen Layout and Mask Sets

Hauptseminar: System Design using SystemC

ChipDesign.ppt page 1© Fraunhofer IIS, 2005

IISFraunhofer Institut

Integrierte Schaltungen

High Level IC Design

Frank Mayer ([email protected])

Fraunhofer IIS

Erlangen, Germany





Overview

IC Technology

– layout, mask sets

– cells and libraries

– characterizing cells

– state-of-the-art challenges

Design Flow & Tools

Coding Style

Summary





Layout and Mask Sets

A typical layout ...






Zoom ...






power supply(pad ring)

bond area

ESDprotection

output driverpower supply

(core)

Zoom ...

... PAD

pad logic






Zoom ...





Layout and Mask Setsmetal1

Zoom ...

... logic celllogic cell

output section(drivers)

input section(logic)

poly

vias

metal2





ASICs & FPGAs – A Simple Classification

“full custom ASIC”

– layout-based

– the designer draws each polygon “by hand”

– only for analogue and high(est) volumes

“cell based ASIC”

– used predefined building blocks (“cells”)

– designer creates a schematic that interconnects these cells

– layout = placement & interconnection of cells

– for “functionality” or “time-to market” driven design





ASICs & FPGAs – A simple Classification

“Gate Array” (GA)

– cells are placed on pre-manufactured silicon (“masters”)

– interconnections (metal) defined by the designer

– only some (1 ... 5) custom defined masks (time to market, cost)

“Field Programmable Gate Array” (FPGA)

– universal, fully qualified custom of the shelf (COTS) component

– programmable cell functions, programmable interconnect

– timing depends on P&R (significantly slower than ASICs & GAs)

– one-time programmable (fuses), or RAM/E2PROM/Flash based

– cost efficient for medium complexity (<1M gates) designs





ASICs & FPGAs – A simple Classification

“Programmable Logic Device” (PLD, PLA, PAL, ...)

– AND-OR combinatorial logic, plus FF

– designer writes boolean equations

– predictable timing

– small complexities only

“Complex PLD” (CPLD)

– several PLD blocks

– programmable interconnection matrix





Cells

“cells” are the basic building

blocks for ASICs and FPGAs

A digital standard cell represents

– a simple logical function (AND, OR, XOR, MUX)

– a complex logical function (AND8, AND-OR, ...)

– a register (flip-flop) or a latch

– special elements (pads, bus-holder, delay, memories)

Each cell has

– fixed size / fixed contact points

– fixed functionality

– characterized timing arcs





Libraries

"libraries" are collections of cells common data base, different representations (views)

– “layout view”

– “simulation view”

– “synthesis view”

– ...





Libraries

Example From the STD130 data book (SEG, 0.18 µm):

cell name driver strengthoutput name





Timing characteristics

A simple model ... cell delay = f(input slope, output capacitance)






A simple model ...

requires a lot of calculations

1 2-dimensional table based delay model,

recursive calculation of tR/tF and tPLH/tPHL

2 input / output slope and drive assigned by user

3 pin-to-pin delay (interconnects)

4 distributed interconnects (wire resistance, capacitance)






A simple model ...

best - typical - worst case ?

Derating factors are used to include

– process variations (production)

– temperature (on-chip)

– supply voltage





Challenges

Timing Estimation vs.

Placement

Cell delay:

– 0.6 µm: 400 ps (@ 5 V)

– 0.35 µm: 150 ps (@ 3.3 V)

– 0.18 µm: 35 ps (@ 1.8 V)

Wire delay:

– absolute limit: 3 ps / µm (speed of light)

– interconnect delay (distributed RC):

0.1 ns (local) up to several ns (global)

–> interconnect delay determines maximum clock frequency

–> cells are very sensitive to “spikes” (range: <<100 ps)





Challenges

Timing extraction Down to 0.5µ (0.35µ)

– 2-dimensional RC extraction

– static extraction is sufficient

Below 0.35µ

– full 3-dimensional RC extraction

– dynamic behavior should be considered

The extracted parameters are used to estimate the timing,

but an error margin (varying with tool and methodology)

has to be accepted.





Cross Talk

Parameters for an state-of-the-art technology:

– core voltage: 1.2 ... 1.8 V

– signal rise & fall times: 20..50 V / ns

– wire-to-wire distance: < 1µm

– bus width: typical 32 lines (up to several 100 are possible)

Cross talk

– will affect signal integrity

– will affect signal speed

– needs dynamic analysis under “worst” conditions





Power Supply

Inductance of power

supply bond wires + package

Simple model of

output pad cell:





Power Supply

Only a few nH & pF Example: U = 3.3V, CL = 20pF, tF = 5ns

–> i = 30pF * (3.3 / 2.5ns) = 40 mA

TQFP package, data bus with 8 lines, simultaneous switching

–> u = 10nH * (40mA / 2.5ns) * 8 = 1.3 V





Overview

Technology

Design Flow & Tools

– Synthesis based design flow

– Simulation

– Synthesis

– Layout

– other tools

Coding Style

Summary





Place & Route

Schematic

flowchart, state and block diagram

(V)HDL

Netlist

Netlist

Soft Cores

Code Generator

Core GeneratorTest Insertion

SynthesisNetlister

(V)HDL EntrySchematic Entry

High Level /Graphical Entry

Hard Cores Generated Core

Description

Layout, e.g. GDS-II

Design

Design Flow

ASIC & Gate Array

(Design Implementation Phase)

Abbreviation:(V)HDL = VHDL, Verilog or SystemC-RTL





Design Flow

ASIC & Gate Array

(Production Phase)

Wafer Production

Packaging

Production Test

Mask Generation

testedComponent

Layout, e.g. GDS-II

Production

Mask Set





Design Flow

Programmer

Schematic flowchart, state and block diagram(V)HDL

Design

Production

Boolean EquationsConfiguration Data

Fitter Place & Route

Fusemap / Bitstream

Synthesis Converter

netlistdesign database

Converter

Schematic Entry

configurableMacro Blocks

(V)HDL Entry High Level /Graphical Entry

State TransitionEquations, etc.Boolean Entry

programmeddevice

configurationPROM

FPGA & CPLD






Tools: (V)HDL Simulator

Execution of (V)HDL

Design Descriptions

Used for

– Verification of the (V)HDL Design [Functionality]

– Verification / Regression Test for Netlists [Functionality]

– Timing Verification [Timing]

Requires

– Simulator (VHDL, Verilog, SystemC)

– Design ((V)HDL Source or Netlist)

– Stimuli (+ expected Responses)

– Simulation Libraries (behavioral models)







“Event Driven” Approach For each signal change (“event”):

– set the signal to it’s new value

– calculate the output signal for each gate

– propagate these output changes (–> new events)

Pro

– models the circuits behavior precisely

– may include timing / delay

Cons

– runtime requirements

– each gate’s behavior may be evaluated more than once

&D0

D1

Y10

Y11

Y01

Y001

1

1

1&

&

&

1 2 3Event-Reihenfolge:






Software based tools – runs on workstation / PC (on a general purpose CPU)

– “event driven” simulation

– high level of abstraction (debugging (V)HDL sourcecode)

– only hundred simulation cycles (*) per second

– some 100 MByte(*) memory consumption

– required computing power and memory consumption for

simulation on netlist level, including timing information:

factor 5..10, compared to initial VHDL code

(*) based on a medium size design (some 100k gates)






Accelerators & Emulation Dedicated, specialized hardware

– several “CPUs” work in parallel

– or: mapping to an FPGA-based hardware

– optimized algorithms

– 1,000 to 1,000,000 cycles / second (“real time”)

– several orders of magnitude faster, compared to SW simulation

– simulation on netlists only, i.e. after synthesis

–> low level of abstraction, debugging is very hard to do





Using Simulation: Test benches

Design Entry

Verification

Optimal use of “test benches”:

– automated testing (stimuli)

– automated result checking

– reproducible setup

– self-documenting

DUT

DeviceUnderTest

Simulation Models

Peripherals, Memory, ...

ClockReset

(V)HDLChecker

OutputDriver

(V)HDLTest Pattern

InputDriver

Waveform

Testbench





SystemC & Simulation

Tools & Methodology “OSCI”-Simulator

– simulation capabilities built into SystemC library

(Executable = Self-Contained Design + Event Driven Simulation)

– basic support for waveform tracing (compiled in)

– depends on 3rd party tools (Debugger, Waveform Viewer)

“SystemC-HDL Co-Simulation”

– Industry Standard HDL Simulator (ModelSim, VCS, NCSim, ...)

– SystemC Integration (kernel integration OR simulator coupling)

– HDL Simulator “look and feel” for SystemC

– only signals can be viewed in simulator, no debug support for

user-defined channels





Tools: Synthesis

Courtesy: Synopsys

Synthesis =

Translation +

Optimization +

Mapping





Tools: Synthesis

Requires

– Synthesis Tools (e.g. Synopsys Design Compiler)

– Design (VHDL/Verilog/SystemC-RTL) Source

– Constraints

– Synthesis Libraries (behavioral, area + timing models)

Mapping / Optimization is guided by

– timing (setup and hold time) –> speed

– loads (fan-in / fan-out)

– area

– other constraints





Tools: Synthesis

Courtesy: Synopsys





SystemC & Synthesis

– synthesis frontend

for SystemC

– requires “classical” synthesis

backend (e.g. Synopsys DC or

FPGA Compiler)

Available Tools

– SystemC Compiler (RTL), Synopsys

– translates SystemC-RTL into Synopsys DB format

– optional: Verilog or VHDL Output

– supports RTL sub-set (capabilities similar to Verilog)

– SystemC Compiler (Behavioral), Synopsys

– “behavioral” synthesis frontend (also for VHDL, Verilog)

– automatic scheduling and FSM generation

– Cynthesizer, Forte Design Systems

– “behavioral” and “cycle fixed” synthesis

– SystemC (V)HDL Converters (e.g. Prosilog)





Tools: Layout

Layout = Place & Route Cell based layout:

– place the cells = Placement

– connect all pins = Routing

Layout has to provide

– timing closure (match or improve the estimated timing)

– small area

– signal integrity (net capacitance, buffering, crosstalk)

– no violation of any design rule defined by the silicon vendor

– GDS-II output (database with “polygons”)





Overview

Technology

Design Flow & Tools

Coding Style

– What is RTL ?

– Combinatorial Logic

– Storage Elements (Flipflops)

Summary





What is RTL ?

combinatoriallogic

CLK

IN1

IN2

IN3

OUT2

OUT3

module

OUT1

D Q

CLK

flipflop

D Q

CLK

flipflop

RTL = Register Transfer Level

– inputs

(to combinatorial logic)

– registers

(storage elements)

– outputs

(combinatorial or registered)

RTL provides bit true and

cycle true HW descriptions





Synchronous Design

if (en = 1) then D[2:0] = Q[2:0] + 1 else D[2:0] = Q[2:0]

(combinatorial logic)

D2 Q2

CLK

flipflop

D1 Q1

CLK

flipflop

D0 Q0

CLK

flipflop

Q2

Q1

Q0

EN

CLK

CNT_3BIT_SYNC

– ONE single clock

that goes directly to each FF

and that goes nowhere else

– arbitrary combinatorial logic

driven by primary inputs or FFs

outputs go to FFs

– clocked FF only, no Latches!





Asynchronous Design

D2 = not(Q2)CLK2 = not(Q1)

D0 = not(Q0)CLK0 = EN and CLK

D1 = not(Q1)CLK1 = not(Q0)

D2 Q2

CLK2

flipflop

D1 Q1

CLK1

flipflop

D0 Q0

CLK0

flipflop

Q0

Q1

Q2

EN

CLK

CNT_3BIT_ASYNC

Advantage

– reduced switching activity

(low power)

Disadvantages

– unpredictable timing

– uncontrollable functionality

– test insertion (ATPG) will fail

– layout headache

DON’T DO THAT !!!





Combinatorial Logic

Variant0 (direct)bitselect = 0; // all bitsbitselect[sel] = 1;

Variant0 (direct)bitselect = 0; // all bitsbitselect[sel] = 1;

Coding Style

Example:

bitselect[i] = 1;}

Variant1 (explicit decoding, PLD style)bitselect[0] = !sel[1] & !sel[0];bitselect[1] = !sel[1] & sel[0];bitselect[2] = sel[1] & !sel[0];bitselect[3] = sel[1] & sel[0];

Variant1 (explicit decoding, PLD style)bitselect[0] = !sel[1] & !sel[0];bitselect[1] = !sel[1] & sel[0];bitselect[2] = sel[1] & !sel[0];bitselect[3] = sel[1] & sel[0];

"one hot" (4 bit)2:4decodebinary (2 bit)

Variant2 (case selection)switch(sel){ case 0:

bitselect = 1; break;case 1:



bitselect = 8; break;default:

bitselect = 0; }






bitselect = 0; }

Variant3 (compare loop)bitselect = 0; for (i=0; i<4; i++){ if (sel == i)

bitselect = 0; for (i=0; i<4; i++){ if (sel == i)

bitselect[i] = 1;}

Variant3 (compare loop)





Combinatorial Logic

After “elaboration”Variant0 (direct)bitselect = 0;bitselect[sel] = 1;

Variant0 (direct)bitselect = 0;bitselect[sel] = 1;

... sorry, does not work ...

(restriction in Synopsys DC)





Combinatorial Logic

After “elaboration”Variant1 (explicit decoding, PLD style)bitselect[0] = !sel[1] & !sel[0];bitselect[1] = !sel[1] & sel[0];bitselect[2] = sel[1] & !sel[0];

bitselect[0] = !sel[1] & !sel[0];bitselect[1] = !sel[1] & sel[0];bitselect[2] = sel[1] & !sel[0];bitselect[3] = sel[1] & sel[0];bitselect[3] = sel[1] & sel[0];

Variant1 (explicit decoding, PLD style)





Combinatorial Logic

After “elaboration”Variant2 (case selection)switch(sel){ case 0:





bitselect = 0; }






bitselect = 0; }





Combinatorial Logic

After “elaboration”Variant3 (compare loop)bitselect = 0; for (i=0; i<4; i++){ if (sel == i)

bitselect[i] = 1;}

Variant3 (compare loop)bitselect = 0; for (i=0; i<4; i++){ if (sel == i)

bitselect[i] = 1;}





Combinatorial Logic

After “compile” and optimization

Conclusion:

Today’s synthesis tools are smart

enough to optimize combinatorial

logic independent of the coding

style.Write your code for humans!

Variant 1 = Variant 2 = Variant 3 !





Storage Elements

Flipflop Ports

– D (data input), synchronous

– Q (data output), synchronous

– CLK (clock input)

– optional: set, reset (asynchronous)

Behavior

– sample input D on each pos. clock edge and store this value (=Q)

– if set (or reset) is active, set Q to 1 (or 0)

– D needs to be setup prior to pos. clock edge (no hold time)

– Q appears short time after pos. clock edge

dc

D Q

CLK

RST_N

CLK

RST_N

D

Q

a b

0 c d





Storage Elements

Latches Ports

– D (data input)

– Q (data output)

– EN (latch enable)

– optional: set, reset (asynchronous)

Behavior

– if EN is active: sample D continuously, and store this value (=Q)

– if EN is inactive: hold last value (Q)

– if set (or reset) is active, set Q to 1 (or 0)

– if D changes while EN is active: Q changes after some delay

b dc

D Q

EN

RST_N

EN

RST_N

D

Q

a

0 c db





Storage Elements

Latches Don’t use latches, because:

– a spike on EN (e.g. if driven by combinatorial logic) will change Q

final timing is unknown until after layout

behavior is unpredictable

– testability problem (not handled by normal ATPG tools)

– more timing arcs (compared to flipflops)

b dc

D Q

EN

RST_N

EN

RST_N

D

Q

a

0 c db





– any incomplete decision will potentially interfere a latch, e.g.

– always include else or default block

– or: use default assignments upfront

if (a == b)c = a + 1;

// no else statement, so what happens if a != b ???// --> last value of c is preserved --> latch

if (a == b)c = a + 1;

// no else statement, so what happens if a != b ???// --> last value of c is preserved --> latch

if (a == b)c = a + 1;

elsec = 0; // default

if (a == b)c = a + 1;

elsec = 0; // default

c = 0; // defaultif (a == b)

c = a + 1;

c = 0; // defaultif (a == b)

c = a + 1;

Storage ElementsLatches are easy to create(accidentally)





Code Example (RTL)

Simple Finite State Machine:

0 1 2 3

6789

RSTCLK CLK CLK

CLKCLKCLK CLK CLK





0 1 2 3

6789

RSTCLK CLK CLK

CLKCLKCLK CLK CLK

Code Example (RTL)// Portssc_in< bool > clk;sc_in< bool > rst_n;sc_out< sc_int<4> > cnt;...// Signalssc_signal< sc_int<4> > cnt_d;...SC_CTOR(my_fsm){

// combinatorial process:SC_METHOD(p_fsm_cmb)sensitive << cnt;

// register process:SC_METHOD(p_fsm_reg)sensitive_neg << rst_n;sensitive_pos << clk;

}...

// Portssc_in< bool > clk;sc_in< bool > rst_n;sc_out< sc_int<4> > cnt;...// Signalssc_signal< sc_int<4> > cnt_d;...SC_CTOR(my_fsm){

// combinatorial process:SC_METHOD(p_fsm_cmb)sensitive << cnt;

// register process:SC_METHOD(p_fsm_reg)sensitive_neg << rst_n;sensitive_pos << clk;

}...

SystemC Code

(Fragments) ...// combinatorial processvoid p_fsm_cmb (void){ sc_int<4> v_cnt;

v_cnt = cnt.read();switch(v_cnt){ case 0: case 1: case 2:

case 6: case 7: case 8:v_cnt = v_cnt + 1;break;

case 3: v_cnt = 6;break;


default:v_cnt = 0;}cnt_d.write(v_cnt);

}

...// combinatorial processvoid p_fsm_cmb (void){ sc_int<4> v_cnt;

v_cnt = cnt.read();switch(v_cnt){ case 0: case 1: case 2:

case 6: case 7: case 8:v_cnt = v_cnt + 1;break;



default:v_cnt = 0;}cnt_d.write(v_cnt);

}

...// register processvoid p_fsm_reg(void){

if (rst_n.read() == 0){ // reset

cnt.write(0);}else{ // update

cnt.write(cnt_d.read());}

}...

...// register processvoid p_fsm_reg(void){

if (rst_n.read() == 0){ // reset

cnt.write(0);}else{ // update

cnt.write(cnt_d.read());}

}...





Code Example (RTL)

Result (after Synthesis):





Summary

What did we learn ? IC Technology

– How does a chip look like ?

– Classification: ASICs – FPGAs - PLDs

– “cells” & “libraries” – the building blocks for ASICs

– functionality

– timing characterization

– sub-micron challenges





Summary

What did we learn ? Design Flow & Tools

– Example design flow for ASICs and FPGAs

– (V)HDL Simulation

– event driven approach

– test benches

– SystemC & Simulation

– Synthesis

– What is Synthesis ?

– SystemC & Synthesis

– Layout / Place&Route





Summary

What did we learn ? Coding Style

– What is RTL ?

– synchronous – asynchronous design

– combinatorial logic – storage elements

– Does and Dont’s

– RTL Code Examples in SystemC

Documents

High Level IC Designl · Hauptseminar: System Design using SystemC ChipDesign.ppt © Fraunhofer IIS, 2005 page 3 IIS Fraunhofer Institut Integrierte Schaltungen Layout and Mask Sets