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High Bandwidth Low Power Operational Amplifier Design and Compensation
TechniquesFinal Oral Master/ PhD Qualifier
May 1rst 2009Vaibhav Kumar
AbstractDevelopment of a new compensation technique forbandwidth extended Operational Amplifiers in scaledCMOS process
Proposed easy to follow Design Guideline for practicaldesign where power, speed and manufacturability arecritical
In comparison to state of the art performs up to 100times better in Figure of Merit (FOM)
10/20/2009 VAIBHAV KUMAR - IOWA STATE UNIVERSITY 2
Agenda
• Introduction
• Literature Review
• Indirect Feedback Frequency Compensation
• Design Procedure and Specifications
• Simulation Results
• Analog Layout
• Future Research (part of PhD Qualifier)10/20/2009 3VAIBHAV KUMAR - IOWA STATE UNIVERSITY
INTRODUCTION
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IntroductionThe Operational Amplifier (op-amp) is a fundamental building block in all electronic circuits
Employed profusely in data converters, filters, sensors, drivers etc…..
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Future Process TrendsContinued CMOS Scaling (pushing into the nanoscale arena) has been challenging the established paradigm for op amp design.Consequences due to downscaling in channel length for op amp design
Transition frequency (increased speed)
Open-loop gain reduction
Supply Voltage reduction (lower headroom)
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EBT L
Vf ∝
omEB
Lg r V∝
Supply and Threshold Voltage Trends
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Figure 1: Supply voltage (Vdd) and threshold voltage (Vth) trends in future CMOS semiconductor processes technology (ITRS) [1]
Transition Frequency Trends
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Figure 3: Transistor transition frequency (fT) trends in future CMOS semiconductor processes technology (ITRS) [1]
Entering the NANO CMOS domainWhy do we need CMOS scaling ??
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Strongly driven by Digital VLSI Circuit NeedsGoals: in each Generation
2X increase in density1.5X increase in speed
What about “ANALOG SPEED” ??it is orders of magnitude behind digitalwhy??
Analog Speed IssueAt the center of all analog circuits is an
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OPERATIONAL AMPLIFIER
β
Almost always used in Closed Loop Feedback Configuration
Need to worry about STABILITYof the closed loop system
Applying the Lens of Stability
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Prevalent Compensation Techniques including Miller Compensation provide poor bandwidth efficiency
Result in OP-AMP which are very slow
Extending the OP-AMP bandwidth has been a pursuit for all analog designers
Research Goal of this work Find a practical way to increase bandwidth efficiency
Integration of AMS into Nano CMOSBetter Op-Amp compensation TechniquesDesign low-VDD Op Amps
Replace vertical stacking of transistors (cascoding) by horizontal assembly of stages (cascading)
Better supply rejection noise (PSRR)Minimize
PowerLayout Area
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Effects of AMS Design being Squeezed with Scaling
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Reduced head room challenges compared to traditional AMS designs
Process Variation makes design centering tough
Raises the question for future Analog VDD scaling…
Figure 5: Effects of scaling down Analog Supplies
LITERATURE REVIEW
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Traditional Op Amp Compensation TechniqueParallel Compensation
Capacitor is connected in parallel to the output resistance of gain stage of the Op Amp to modify pole
Pole Splitting (Single Miller Compensation)Slow speed (unless large bias and large devices are used) for a given load CL
Have the right half plane zeroPoor PSRRPoor Slewing
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-1/R2C2 -1/R1C2
pole splitting-1
gm2R2R1C1
-gm2C1+C2
gm2Cc
Direct (Miller) Compensation
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VsA2A1
Vout VsA2A1
Cc
Vout
Rout
AA
-gm1Vd
R1 C1
V1
-gm2V1
R2
CL
Vout
Cc
Ic=(vout-vs)1/sCc
Figure 7: Small Signal Model for SMC
Figure 6: Two Stage Miller Compensation
Figure 8: Pole Splitting effect of SMC
Transfer Function
Pole/Zero LocationsBandwidth Reduction
RHP Zero
Miller CompensationCompensation capacitor is between the output of the two stage. This results in pole splitting between the dominant and non dominant poleA RHP zero exists at
Due to the feedforward component of the compensation current (Ic)
The second pole exists at
The unity gain frequency is at fun = gm1/2πCc
ISSUES WITH MILLER COMPENSATIONRHP zero reduces the phase margin of the amplifier and thus causes instability
Requires large Cc for stability Slow speed for a given load, CL
Poor PSRRSupply noise feeds through the compensation capacitor to the output
Requires large die area
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Miller Compensation with Zero Nulling ResistorA common method to cancel the RHP zero is by using a series resistor with compensation capacitorThe new location of the zero is
The resistor Rz can be implemented using a transistor in triode region
However introduces a third pole to the system
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Need More Stable Op AmpsWe can increase Rz and create a LHP zero to improve phase margin
Becomes difficult to manage the location of the Rz over temperature and process variations
Stability of the op amp is a becoming a problem because of the non-dominant pole associated with the output (f2) is too lowIncrease f2 requires increase of gm of the output stage
Increase areaIncrease output stage current (Id2)
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Need a more practical way to CompensateAvoid using Miller Compensation
Avoid connecting a compensation capacitor between two high impedance nodes !Literature has many examples illustrating how to avoid miller connections for high speed
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This research develops Indirect Feedback Frequency CompensationA more practical way to compensateFeedback compensation current indirectly using
Common Gate AmplifierCascoded Structures
Improved PSRRSmaller Die Area (Compensation capacitor reduced 4~10 times)Much Faster ..!
VsA2A1 Buffer
Cc
Differential Amplifier Gain Stage Output Buffer
Vout
iccRi
A
Indirect Feedback - History• First proposed by B.K. Ahuja in “AN IMPROVED FREQUENCY COMPENSATION
TECHNIQUE FOR CMOS OPERATIONAL-AMPLIFIERS,” Ieee Journal of Solid-State Circuits, vol. 18, no. 6, pp. 629-633, 1983
• However it is still seldom used in practice ??• Looks very similar to Miller compensation• Prompts most designers to use design strategy for Miller-Rz compensation• However the Indirect Compensation Scheme has much different pole/zero
locations and conditions that need to be satisfied to tap the true potential of the compensation scheme
• Thus this work Provides analytical model/solution for the architectureProposes a design procedure based on the analytical resultsDesign Example using the proposed design procedureSimulation Results show the performance is orders of magnitude higher than miller compensation and far better than state of the art
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INDIRECT FEEDBACK FREQUENCY COMPENSATION
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Indirect Feedback Frequency Compensation
Improvements due to a simple changeThe compensation current is indirectly fedback from low impedance node VA to V1
The RHP pole zero can be eliminated as the feedforward current is blocked by the common gate amplifierNode V1 is now not loaded by the compensation capacitor (as previously) and thus results in a much faster second stage and increased unity gain frequency
AND MUCH MORE ………
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M1 M2
M3 M4
M5
M6c
VDD
VSS
Cc
Vin- Vin+
M9
ic
VA
V1
Mb3M7
Mb1
Isupply
Mb2
Mb4
Mb5 Mb6
Vout
Vbb
Small Signal Analysis
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Cc
gm1Vd
R1 C1
V1 VA
gmcVA
roc
1/gmc RA CA gm5V1 R2CL
Vout
TAKING KCL AT EACHNODE
Simplified Transfer Function
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The transfer function can be simplified and approximated as:-
The coefficients can be evaluated as
Evaluating the poles and zerosAssuming the pole |p1| >> |p2|, |p3|
The denominator can now beapproximated
Real Poles Complex Poles
The third order transfer function as 3 poles and 1 zeroDominant Pole location
Non-dominant Real Poles locationCondition For Real Poles
LHP Zero Location
bserving the Pole/Zero Locations
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Remains at the same location
Large gmc ?
Improves Phase Margin
Analytical Results Summary
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Pole / Zero Location
Real Poles Condition
Quick Facts
Pole p2 moved to much higher frequency
Can use much smaller gm5 Less Power
LHP zero improves the phase margin
Much faster op-amp with lower power and CC
Will EXPLORE more ….
Extended by a factor >1
M1 M2
M3 M4
M5
VDD
VSS
Cc
Vin- Vin+
M9
ic
V1
M7Mb1
Isupply
Mc1 Mc2
Vbb
A
if
Vout
Vcc
Alternative Implementations of Indirect Feedback
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The common gate amplifier is embedded in the cascode actionSimilar to the common gate amplifier analyzed in the previous section, the LHP zero and the three poles are given by Equations provided previouslyReduction in Power at cost of Flexibility choosing the transconductance of gmc
M1 M2
M3 M4
M5
VDD
VSS
Cc
Vin- Vin+
M9
ic
V1
M7Mb1
Isupply
Mc1 Mc2
Vbb
A
Vout
Vcc
Similar to cascoded PMOS loadsHowever additional RHP zero located at:
RHP zeroHigh Frequency
Summarizing the Advantages of Indirect Feedback
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Pole splitting can be achieved with a much smaller compensation capacitor (Cc)
Faster Op Amp Much Smaller Area
Lower Value of second stage transconductance (gm5) value required
Lower Power and Less Total Current Required
Improved PSRR
Analytically the reason the non-dominant pole shifted to a higher frequency is because the compensation capacitor now does not load the first stage output.
DESIGN PROCEDURE AND SPECIFICATIONS
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Op Amp Design Dilemma
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Need a clear robust design procedure …
Pre - Design Procedure Guidelines
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To quantify how good of a job our transistor does, we can therefore define the following “figure of merits (FOM)
Tranconductor Efficiency Transit Frequency
Good RegionFor AMI 0.5CNVEB ≈ 0.1-0.2 V
Indirect Feedback Design Procedure Summary
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Noise Specification
Slew Rate Specification
Output Swing Specification
Gain-Bandwidth Requirement
Real Poles Requirement
Class A Output Stage Design
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Bad Output Stage DesignNot Controlling current in the output stage leads to:
Bad input-referred offsetPotential for large power dissipationNot controlling output stage gm (and thus stability)
Class A output stages also suffer from poor slew rate
M1 M2
M3 M4
M5
M6c
VDD
VSS
Cc
Vin- Vin+
M9
ic
VA
V1
Mb3M7
Mb1
Isupply
Mb2
Mb4
Mb5 Mb6
Vout
Vbb
M1 M2
M3 M4
M5
VDD
Cc
V1
Mc1 Mc2Vbb
Vout
SR = inf
CLM1 M2
M3 M4
M5
VDD
Cc
V1
Mc1 Mc2Vbb
Vout
Iss2CL
SR =
CL
Class AB Output Stage Design
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Class AB Output StageThe Class AB output stage is realized by have a floating current source biased between the output stages transistors behaving like a push pull:
Slew Rate Improved during dischargingControlled output stage current and gmSlew rate limitation shifted to the compensation capacitor which is small in the proposed compensation scheme and thus achieves much higher slew rate
M1 M2
M3 M4
M5
VDD
Cc
V1
Mc1 Mc2Vbb
Vout
CL
Mpcasc
M6
Mncasc
Iss2
M1 M2
M3 M4
M5
VDD
Cc
V1
Mc1 Mc2Vbb
Vout
CL
Mpcasc
M6
Mncasc
Iss2
Figure of Merit (FOM)
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To perform a comparison in terms of speed among the many compensation approaches independently of the particular amplifier topology, design choices, and technology, a figure of merit (FOM) that relates the load capacitance CL, the gain-bandwidth product ωGBW, and the total current consumption of the amplifier I-Total has been proposed [ref].
Small Signal FOM
DC Transient FOM
Single Stage Comparison
Total TranscoductanceGm in multi-stage op amp
MHz pfmA•
V s pfmAµ •
Design Example – Op Amp Specifications
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Op Amp Specification
Supply Voltages ± 1.25 V
Load Capacitance: CL 100 pF
Total Current (max) 30 μA
DC gain: Ao 70 dB
Unity-gain Frequency: fu 2 MHz
Phase Margin: φM 60°
Slew Rate: SR 1 V/μs
Input Common Mode Range: VCMR ± 1 V
Output Swing: Vout {max,min} ± 0.5 V
Input Referred Noise 15 nV/√Hz
Very Low Power
Large Load
Good Stability
Design Example – Device Sizing
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Op Amp Sizing
Transistor Multiplier Size (μm)
M1,22 4.05/0.9
M3,42 3.6/2.4
M56 10.05/1.5
M612 15/1.05
M76 1.65/1.05
M9,b1110 1.65/4.05
Mb11 1.65/4.05
Mb21 1.65/1.05
Mb312 1.65/1.05
Mb41 2.4/1.05
Mb51 12/1.05
Mb612 12/1.05
Mb72 3/1.2
Mb81 1.65/1.05
Mb9,1010 1.95/0.6
Cc- 5 pF
Isupply- 1.25uA
SIMULATION RESULTS
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Summary of Simulated Results
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Simulated Results
Specification Specifications Simulation
DC gain: Ao 70 dB 72.45 dB
Unity-Gain Frequency: fu 2 MHz 2.01 MHz
Phase Margin: φM 60° 61.83°
Slew Rate: SR+/- ± 1 V/μs 1/-2.45 V/μs
Input Common Mode Range:
VCMR + / VCMR=
± 0.5 V 1.1/-0.75 V
Output Swing:
Vout MAX/Vout MIN
± 1 V 1.14/-1.1
ITotal 30 μA 30 μA
Power - 75 μW
High Speed
+
Low Power
AC Frequency Response (CL = 100pf)
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Bandwidth Extension
Large Signal Transient Response (CL = 100pf)
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Sine Wave Transient Response (CL = 100pf)
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Robustness of Analytical Results
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Small Error
Alternative Indirect Feedback Compensation Scheme Results
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Comparison of Alternative Indirect Feedback Compensation
Specification Common Gate Cascode NMOS Cascode
PMOS
DC gain: Ao 72.45 dB 91.1 dB 86.1 dB
Unity-Gain
Frequency: fu
2.01 MHz 1.99 MHz 2.2 MHz
Phase Margin: φM 61.83˚ 61.29˚ 61.7˚
M1 M2
M3 M4
M5
VDD
VSS
Cc
Vin- Vin+
M9
ic
V1
M7Mb1
Isupply
Mc1 Mc2
Vbb
A
Vout
Vcc
M1 M2
M3 M4
M5
VDD
VSS
Cc
Vin- Vin+
M9
ic
V1
M7Mb1
Isupply
Mc1 Mc2
Vbb
A
if
Vout
Vcc
M1 M2
M3 M4
M5
M6c
VDD
VSS
Cc
Vin- Vin+
M9
ic
VA
V1
Mb3M7
Mb1
Isupply
Mb2
Mb4
Mb5 Mb6
Vout
Vbb
Common Gate Cascode PMOSCascode NMOS
Improved gain dueTo cascoding
Performance Comparison to Miller Compensation and Single Stage Amplifiers
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M1 M2
M3 M4
M5
M6c
VDD
VSS
Cc
Vin- Vin+
M9
ic
VA
V1
Mb3M7
Mb1
Isupply
Mb2
Mb4
Mb5 Mb6
Vout
Vbb
Indirect Feedback
Comparison with Miller Compensation and Single Stage Amplifiers
Specification Single Stage Single Miler
Compensation
Indirect Feedback
Compensation
DC gain: Ao 36.93 dB 70.45 dB 72.45
Unity-Gain
Frequency: fu
1.098 MHz 293.1 KHz 2.01 MHz
Phase Margin: φM 90˚ 60.29˚ 61.7˚
Cc Required -NA- 35 pF 5 pF
Miller CompensationSingle Stage
Winner
Performance Comparison to Literature
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Conference Author Total Id (mA) GBW (MHz) Slew Rate (V/μs) CL (pf) IFOMs (MHz•pf)/mA IFOML ((V/μs)•pf)/mA
ECCTD -2007 [25] Pennisi 1.950 700.00 2000.00 0.3 107.69 307.69
TCAS - 2005 [24] Mahattanakul 0.076 5.00 6.00 5 330.69 396.83
WESEAS -2006 [26] Franz 12.800 1060.00 863.00 4 331.25 269.69
JCSC 2008 [27] Hamed 7.667 300.00 -NA- 8.5 332.61 -NA-
JSSC - 1995 [28] Kovacs 0.110 4.50 -NA- 10 409.09 -NA-
AICSP - 2009 [29] Pugliese 0.318 27.10 25.00 10 851.71 785.71
TCAS - 1997 [6] Palumbo 0.158 28.00 6.59 5 886.08 208.54
E-Letter 2007 [30] Pugliese 0.032 6.70 1.00 10 2125.96 317.31
ECCTD - 2005 [31] Loikkanen 0.210 6.80 6.40 200 6476.19 6095.24
TCAS - 2008 [18] Palumbo 0.150 9.89 -NA- 100 6593.33 -NA-
This Work - Cascode NMOS Kumar 0.025 1.99 1.50 100 7960.00 6000.00
This Work - Common Gate Kumar 0.025 2.00 2.00 100 8000.00 8000.00This Work - Cascode PMOS Kumar 0.025 2.20 2.00 100 8800.00 8000.00
ANALOG LAYOUT
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Floor Planning
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Diff Input
TAIL CURRENT
PMOS OUT
CURRENT SOURCE CG
NMOS OUT
RESISTOR AVSS
AVDD
BIAS PMOS
BIAS NMOS
SIGNAL PATH
COMPENSATION CAPACITOR
PMOS LOAD
PMOS LOAD
CMFB PMOS CG LOAD
CG AMPLIFIER
SIGNAL PATH
SIGNAL PATHSIGNAL PATH
FLOOR PLANNING
INP
INNVOUT
ConsiderationsOrientation of TransistorsPower DistributionRouting EaseCurrent Mirror Matching
Final Layout
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Comments and Conclusions
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We need to increase Unity Gain Frequency of the amplifierThe only way to do this are to decrease the compensation
capacitor and/or increase the diff-amps transconductance fun = gm1/2πCc
The problem with this is stability (the pole, f2 associated with the output of the op amp is comparable to fun)
Need to push f2 to a higher frequency
Moves the pole to a much higher frequency
Thus Indirect Feedback leads to significantlyFaster Lower PowerImproved PSRRSmaller Die Area
Indirect Feedback
FUTURE RESEARCH
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Future Trends - Revisit
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Figure 2: Open loop gain trends in future CMOS semiconductor processes technology (ITRS) [1]
Where we simulate
State of the art
Difference
Op-Amp Number of Stages
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Figure 4: Number of stages required to achieve the DC gain requirement for 10 and 14 bit resolution settling. The figure shows number of cascaded stages required with employing any cascoding for 10 bit ADC settling. It also shown the number internal stages with wide swing cascoded stage required for a 14 bit resolution settling [1]
Future holds tomulti-stage op-amps
Multi-Stage Op Amps
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Multi-stage op amps carve the future of analog designs
Can we implement the indirect feedback frequency compensation to multi-stage amplifier?
What would the general form and design strategy for N stage indirect feedback amplifier look like ?
Do the amplifiers need to have REAL POLES?
VsA2A1
Cc
Differential Amplifier Gain Stage
iccRi
ABuffer
Output Buffer
VoutA2
Cc
Moving the poles to the complex domain..?
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Uncompensated
Derived in [] leads to complex poles.. So the frequency response looks like?
Control DampingWith some creativeFeedback loop ??
Three Stage Topologies: Latest in the Literature
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Transconductance Capacitor Feedback
Employs some form of indirect feedback frequency compensation
Report stellar response compared to other multi-stage amplifiers
Unity Gain Frequency is given by:
Ratio can be large
Moves the poles to the complex domain
Manages the frequency peaking through a feedback loop
[2]
One of the proposed methods• Combine Indirect Feedback Technique to Sansen’s
approach of moving poles to the complex domain
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To control dampingFactor of complex poles Indirect Compensation
to provide compensation current
Proposed Methods AnalysisApproach
Appropriate Circuit ImplementationTheoretical AnalysisPotential and MeritsPropose a Design ProcedureDesign exampleFabricateEvaluate the performance and use it in an application
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References• [1] "Overall Roadmap Technology Characteristics (ORTC)," 03/19/2009, 2009; http://www.itrs.net/Links/2005ITRS/Exec
Sum2005.pdf.• [2] X. H. Peng, and W. Sansen, “Transconductance with capacitances feedback compensation for multistage
amplifiers,” Ieee Journal of Solid-State Circuits, vol. 40, no. 7, pp. 1514-1520, 2005.• [3] P. J. Hurst, S. H. Lewis, J. P. Keane et al., “Miller compensation using current buffers in fully differential CMOS two-
stage operational amplifiers,” Ieee Transactions on Circuits and Systems I-Regular Papers, vol. 51, no. 2, pp. 275-285, 2004.• [4] A. Pugliese, F. A. Amoroso, G. Cappuccino et al., “Design approach for fast-settling two-stage amplifiers employing
current-buffer Miller compensation,” Analog Integrated Circuits and Signal Processing, vol. 59, no. 2, pp. 151-159, 2009.• [5] M. Kayal, and Z. Randjelovic, “Auto-zero differential difference amplifier,” Electronics Letters, vol. 36, no. 8, pp. 695-
696, 2000.• [6] H. Mahattanakul, and J. Chutichatuporn, “Design procedure for two-stage CMOS opamp with flexible noise-power
balancing scheme,” Ieee Transactions on Circuits and Systems I-Regular Papers, vol. 52, no. 8, pp. 1508-1514, 2005.• [7] P. Monsurro, G. Scotti, A. Trifiletti et al., “Very low voltage CMOS two-stage amplifier,” 2007 European Conference on
Circuit Theory and Design, Vols 1-3, pp. 743-746, 2007.• [8] F. Schlogl, H. Dietrich et al., “Operational Amplifier with Two-Stage Gain-Boost,” Proceedings of the 6th WSEAS
International Conference in Simulation, Modeling and Optimization, Vols 22-24, pp. 482-486, 2006.• [9] H. Aminzadeh, and R. Lotfi, “On the power efficiency of cascode compensation over Miller compensation in two-stage
operational amplifiers,” Journal of Circuits Systems and Computers, vol. 17, no. 1, pp. 1-13, 2008.• [10] R. J. Reay, and G. T. A. Kovacs, “AN UNCONDITIONALLY STABLE 2-STAGE CMOS AMPLIFIER,” Ieee Journal of
Solid-State Circuits, vol. 30, no. 5, pp. 591-594, 1995.• [11] A. Pugliese, F. A. Amoroso, G. Cappuccino et al., “Design approach for fast-settling two-stage amplifiers employing
current-buffer Miller compensation,” Analog Integrated Circuits and Signal Processing, vol. 59, no. 2, pp. 151-159, 2009.• [12] A. Pugliese, F. Amoroso, G. Cappuccino et al., “Settling time optimisation for two-stage CMOS amplifiers with current-
buffer Miller compensation,” Electronics Letters, vol. 43, no. 23, pp. 1257-1258, 2007.• [13] M. Loikkanen, and J. Kostamovaara, “Improving capacitive drive capability of two-stage op amps with current buffer,”
Proceedings of the 2005 European
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Acknowledgements• Dr. Degang Chen (Major Professor)• Dr. Randall Geiger• Dr. Mani Mina• Dr. Ayaman Fayed
Friends and VLSI Group (Past and Present)
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• Rien Biel • Ryan Boesch• Jake Sloat• Ben Curtin
• Tao Zeng• Siva Sudani• Bharath Karthik• Vipul Katyal
• Jingbo Duan• Chen Zhao• Jun He
Committee Members
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