HDL(HARDWARE DEFINITION LANGUAGE)deccancollege.ac.in/ITLABMANUALS/VLSILABMANUAL.doc · Web viewINDEX. S NO CONTENTS/PROGRAM NAME Page No . INTRODUCTION . I Hardware Description

VLSI DESIGN LAB DCET

INDEX

S NO CONTENTS/PROGRAM NAME Page No

INTRODUCTION

I Hardware Description Language 5

SWITCH LEVEL MODELING 7

1 Design a NOT gate using CMOS 9

2 Design a 2-Input NAND gate using CMOS 14

3 Design a 2-Input NOR gate using CMOS 19

4 Design an AOI f= using CMOS 24

5 Design an OAI f= using CMOS 30

6 Design a Complex logic gate f= using CMOS 35

STRUCTURAL GATE LEVEL MODELING 40

7 Design an AOI gate f= 46

8 Design a Half Adder 52

9 Design a Full Adder 58

10 Design a S-R Latch 64

11 Design a 2:1 MUX using Tri State Buffer 70

RTL LEVEL MODELING 76

12 Design a 4:1 MUX 78

13 Design a 8:1 MUX 85

14 Design a 2:4 Active High Decoder 89

15 Design a 4:2 Priority Encoder 93

16 Design a Positive Edge Triggered Master-Slave D Flipflop 97

17 Design a Positive Edge Triggered Master-Slave JK Flipflop 102

STUDENT NAME PAGENO ROLL NAME


18 Design a Positive Edge Triggered Master-Slave T Flipflop 106

19 Design a Gated D Latch with Enable Input 110

SIMPLE LAYOUT DIAGRAMS 114

20 Draw a Layout diagram for NOT gate 117

21 Draw a Layout diagram for a 2-Input NAND gate 121

22 Draw a Layout diagram for a 2-Input NOR gate 126

SYNTHESIS OF DIGITAL CIRCUITS 131

23 Implement Ripple Carry Adder using RTL & Behavioral Modeling

132

24 Implement Carry Look Ahead Adder using RTL & Behavioral Modeling

138

25 Implement Register Multiplier using RTL & Behavioral Modeling

145

26 Implement Array Multiplier using RTL Modeling 151



INTRODUCTION



HDL(HARDWARE DESCRIPTION LANGUAGE)HDL -> Hardware description language allows us to specify the components that makeup instead of having to use a pictorial representation like a block or logic diagram. Every component is defined by its input and output part logic function. It performs and timing characteristics such as delay and clocking. An entire digital system can described in text format using prescribed set of roles and keywords(reserved words).

Generally two types of HDL

(1) VHDL (VHSLC HDL):

Very high speed: Integrated circuit HDL

(2) Verilog HDL:

Mostly in VLSI design uses verilog HDL.

Verilog HDL is a relatively loose and free following language.

It uses similar procedures and constructs C- programming language.

Verilog HDL provides for description of a digital System at all of the levels in VLSI design flow.

Verilog code use sans serif font type.

This language is case sensitive.

In VLSI we have following types of modeling

(1) Structural Gate level modeling.

(2) Switch level modeling.

(3) Hierarchal modeling (mixed level modeling Gate and Switch level modeling).

(4) Behavioral modeling.

(5) Dataflow and RTL modeling.



VLSI DESIGN FLOW

SWITCH STUDENT NAME PAGENO ROLL NAME


LEVEL

MODELING

SWITCH LEVEL MODELING

Verilog allows switch level modeling that is based on the behavior of MOSFETS.

Switch level models have a direct one-one correspondence with CMOS circuits and logic gates.

The switch primitives are named nmos,pmos,and cmos.



Verilog syntax for these primitives are in the form of

nmos name(out,data,ctrl);

pmos name(out,data,ctrl);

Verilog keywords suppy1 and supply0 that define the power supply vdd and gnd connections.

These represent the strongest logic 1 and logic 0 drivers respectively.

The verilog module treats these as the data into the fets while the gate input is the switch ctrl.

The cmos primitive:

The syntax for the cmos tg is:

Cmos tg1(out,data,n_ctrl,p_ctrl);

The delay times:The syntax for time delays is identical to that used for logic gates .the delays are specified in time units using the pound sign designator # (times). Examples:

Nmos #(2) n1 (out,data,ctrl);

Pmos #(3,4) p1(out_p,data_n,p_ctrl);

Cmos #(2,3,3) tg1(output,input,n_sig,p_sig);

RESISTIVE RMOS SWITCHES:

Syntax is :Rnmos #(1,2,2) fet_1(output,input,gate_ctrl);

1.NOT LOGIC GATEAIM: To design NOT logic gate in switch level modeling using verilog code

Description: The NOT or INVERT function is often considered the simplest Boolean operation.



NOT logic gate Cmos is built using one PFET and one NFET. Gate input ‘a’ is given common to both FETS and o/p ‘f’ is drawn connecting both FETS in series.

If gate i/p a=0 then PFET mp is ON and NFET mn is off. This connect the o/p node ‘f’ to power supply voltage VDD (i/p) giving an o/p f=1

If the gate i/p a=1 then NFET mn is on and PFET mp is off. This connect the o/p node f to ground (i/p).

Expression for o/p:

f = . 1 + a . 0 =

f = NOT ( a ) =

NOT GATE:

Symbol:



CMOS Diagram:

TRUTH TABLE:

VERILOG CODE:

module not2(

input a,


INPUT OUTPUT

a f

0

1

1

0


output f);

supply1 vdd;

supply0 gnd;

pmos(f,vdd,a);

nmos(f,gnd,a);

endmodule

OUTPUT WAVEFORM:



TIMING DIAGRAM:

2.NAND LOGIC GATE

AIM: TO design NAND logic gate in switch level modeling using verilog code.



Description: NAND gate is called as universal gate. NAND2 logic gate Cmos circuit is built using 2 parallel connected PFET and 2 series connected NFET.

If gate inputs a = b = 1 then PFET are off [p1 & p2] and NFET [n1 & n2] are ON. This connecting ground (i/p) to o/p node f = 0.

If either of gate inputs is zero then o/p node f=1.

NAND gate is complement of NOR gate.

NAND function is negation of ‘and’ function.

Expression for o/p:

f (a , b)= . 1 + . 1+ a . b . 0

f = + =

f =

SYMBOL:

CMOS DIAGRAM:



TRUTH TABLE:

INPUT OUTPUT

a b f

0 0 1

0 1 1

1 0 1

1 1 0

VERILOG CODE:



module nand2(

input a,

input b,

output f);

wire wn;

supply1 vdd;

supply0 gnd;

pmos p1(f,vdd,a);

pmos p2(f,vdd,b);

nmos n1(f,wn,a);

nmos n2(wn,gnd,b);

endmodule

OUTPUT WAVEFORM:



TIMING DIAGRAM:



3.NOR LOGIC GATE:AIM:- To design NOR logic gate in Switch level modeling using verilog code.

DESCRIPTION:- NOR is an universal gate.

NOR2 logic gate CMOS circuit is built using two series PFET (p1&p2) and two parallel connected NFET (n1&n2).

If both inputs a=b=0 then PFET p1&p2 are ON and NFETS (n1&n2) are off. This connects the VDD input to output node f=1

If either gate inputs is one then output f=1.

NOR gate is complement of NAND gate.

NOR gate is negation of OR gate.

EXPRESSION FOR OUTPUT:-

f (a,b) = . .1 + .b.0 + a. .0+a.b.0

f(a,b)= . =

f=

SYMBOL:



CMOS DIAGRAM:

TRUTH TABLE:



INPUT OUTPUT

a b f

0 0 1

0 1 0

1 0 0

1 1 0

VERILOG CODE:module nor2(

input a,

input b,

output f);

wire wp;

supply1 vdd;

supply0 gnd;

pmos p1(wp,vdd,a);

pmos p2(f,wp,b);

nmos n1(f,gnd,a);

nmos n2(f,gnd,b);

endmodule



OUTPUT WAVEFORM:

TIMING DIAGRAM:



4.AOI LOGIC GATEAIM:-To design AOI gate in Switch level modeling using verilog code.

DESCRIPTION :- The inverting nature of CMOS logic circuits allows to construct logic circuit for AOI logic expression.

An AOI [AND-or-inverter] function is the one that implements the operation in the order AND->OR->NOT.

AOI function can also be called as inverted SOP (Sum Of Products).

AOI4->here four inputs are used to design AOI gate.

AOI4 CMOS circuit built using serves and parallel FET’s connected.

n1 and n2, n3 and n4, n5 and n6 are connected in series (n1.n2,n3.n4,n5.n6).

n1.n2,n3.n4,n5.n6 are parallel to each other (n1.n2|n3.n4|n5.n6).

p1 and p2 are parallel, p3 and p4are parallel , p5 and p6 are parallel.

p1 and p2, p3and p4, p5 and p6 are in series with each other[(p1|p2).()p3|p4).(p5|p6)].

| -> parallel representation-> OR operation.

. -> series representation ->AND operation.


f =



CIRCUIT:

CMOS CIRCUIT FOR AOI:



TRUTH TABLE(AOI)

INPUT OUTPUT

a b c d f

0 0 0 0 1

0 0 0 1 1

0 0 1 0 1

0 0 1 1 1

0 1 0 0 1

0 1 1 1 0

0 1 1 0 1

0 1 1 1 0

1 0 0 0 1



1 0 0 1 1

1 0 1 0 0

1 0 1 1 0

1 1 0 0 0

1 1 0 1 0

1 1 1 0 0

1 1 1 1 0

VERILOG CODE:

module AOI(

input a,

input b,

input c,

input d,

output f);

wire w1,w2,w3,w4,w5;

supply 1 vdd;

supply 0 gnd;

pmos p1(w1,vdd,a);

pmos p2(w1,vdd,b);

pmos p3(w2,w1,a);



pmos p4(w2,w1,c);

pmos p5(f,w2,b);

pmos p6(f,w2,d);

nmos n1(f,w3,a);

nmos n2(w3,gnd,b);

nmos n3(f,w4,a);

nmos n4(w4,gnd,c);

nmos n5(f,w5,b);

nmos n6(w5,gnd,d);

endmodule

OUTPUT WAVEFORM:

\\

TIMING DIAGRAM:



5.OAI LOGIC GATE

AIM : - To design OAI gate in Switch level modeling using verilog code.

DESCRIPTION: - CMOS inverting nature allows to construct logic circuit for OAI function

OAI is complement of AOI.

OAI function performs the operation in order OR->AND->INVERTER.

OAI is also called as inverted POS (Product Of Sum).

OAI CMOS circuit is built using Series-Parallel connected FETS.

p1.p2, p3.p4, p5.p6 are connected in series.

(p1.p2)|(p3.p4)|(p5.p6) are connected in series.

n1 and n2 are parallel, n3 and n4 are parallel, n5 and n6 are parallel.

(n1|n2).(n3|n4).(n5|n6) are in series with each other.

OAI@-> here four inputs are taken and gives one output.




f= (a+b).(a+c).(b+d)

CIRCUIT DIAGRAM FOR OAI:

CMOS DIAGRAM FOR OAI :



TRUTH TABLE(OAI)INPUT OUTPUT

A b c d F

0 0 0 0 1

0 0 0 1 1

0 0 1 0 1

0 0 1 1 1

0 1 0 0 1

0 1 0 1 1

0 1 1 0 0

0 1 1 1 0



1 0 0 0 1

1 0 0 1 0

1 0 1 0 1

1 0 1 1 0

1 1 0 0 0

1 1 0 1 0

1 1 1 0 0

1 1 1 1 0

VERILOG CODE:module oai(

input a,

input b,

input c,

input d,

output f);

wire w1,w2,w3,w4,w5;

supply 1 vdd;

supply 0 gnd;

pmos p1(w1,vdd,a);



pmos p2(f,w1,b);

pmos p3(w2,vdd,a);

pmos p4(f,w2,c);

pmos p5(w3,vdd,b);

pmos p6(f,w3,d);

nmos n1(f,w4,a) ;

nmos n2(f,w4,b) ;

nmos n3(w4,w5,a) ;

nmos n4(w4,w5,c) ;

nmos n5(w5,gnd,b) ;

nmos n6(w5,gnd,d) ;

endmodule

OUTPUT WAVEFORM:



TIMING DIAGRAM:

6.COMPLEX LOGIC GATE

AIM: TO design Complex logic gate f = in Switch level modeling using Verilog code.

DESCRIPTION: One of the most powerful aspects of building circuit that provides several primitives operations (NOT, AND, OR) in an integrated manner.

Complex logic gate are very useful in VLSI system level design.

p3.p4 I sin series , p2 is parallel with p3.p4. and p1 is in series with p2|(p3.p4)

p1. [p2|(p3.p4)]

n3 and n4 are in parallel n2 is series with n3|n4 . n1 is parallel with n2.(n3|n4)

n1|(n2.(n3|n4))

| represent parallel OR operation

. represent series AND operation.



EXPRESSION FOR O/P:

f =

SYMBOL;

CMOS CIRCUIT DIAGRAM;



TRUTH TABLE (COMPLEX LOGIC CIRCUIT SLM )

INPUT OUTPUT

a b c D F

0 0 0 0 1

0 0 0 1 1

0 0 1 0 1

0 1 1 0 0

0 1 0 0 1

0 1 0 1 0



0 1 1 1 0

0 0 1 1 1

1 0 0 0 0

1 1 0 0 0

1 0 1 0 0

1 0 1 1 0

1 0 0 1 0

1 1 0 1 0

1 1 1 0 0

1 1 1 1 0

VERILOG CODE:

module complex1(

input a,

input b,

input c,

input d,

output f);

wire w1,w2,w3;

supply 1 vdd;

supply 0 gnd;



pmos p1(w2,vdd,b);

pmos p2(w1,vdd,c);

pmos p3(w2,w1,d);

pmos p4(f,w2,a);

nmos n1(f,gnd,a) ;

nmos n2(f,w3,b) ;

nmos n3(w3,gnd,c) ;

nmos n4(w3,gnd,d) ;

endmodule

OUTPUT WAVEFORM:



TIMING DIAGRAM:



GATE LEVEL

MODELING

STRUCTURAL GATE LEVEL MODELLING:

Structural modeling describes a digital logic network in terms of the components that make up the syste. Gate level modeling is based on using primitive logic gates and specifying how they are wired together.

The keyword “module” defines the start of the listing for a network. The last line of the listing “end module “ indicates that the description of the module is complete. The names of output and input “identifiers” are then listed in parentheses with the output first and then the input. Semicolons are used as delimiters in Verilog. A wire decalaration is a datatype called a net. A net value is determined by the output if the driving gate.

IDENTIFIERS:



Identifiers are the names of modules , variables and other objects that we can reference in the design . identifiers consists of upper and lower case letters, digits 0 through 9, the underscore character(_) and the dollar sign($). The first character must be a letter or the underscore in normal usage.

An identifier must be a simple group of characters .

VALUE SET:

The value set refers to the specific values that a binary variable can have. Verilog provides 4 levels for the values needed to describe hardware:0,1, X , Z. the 0 and 1 levels are the usual binary values. A 0 is either a logic 0 or a FALSE statement. While a 1 indicates a either a logic 1 or a TRUE statement. The context determines which interpretation is valid and X represents an unknown value and Z is the high impedence(Hi-Z) value. The unknown value X is important as there are manu situations where there is insufficient information.

GATE PRIMITIVES:

Primitive logic function keywords provides the basis for structural modeling at this level. The important operations in Verilog are and , nand, or, nor xor, xnor, not, and buf where buf is the non inverting drive buffer. All gates except for “not “ and “buf” can have 2 or more inputs.

AND



OR



Xor

nand

nor



xnor

tri-state primitives are bufif0,bufif1,notif0,notif1.

COMMENTS LINES:

Comments are useful for documenting code. If the comment extenhds over two or

more lines , then we use /*.to denote to start the of the comment on the first lint and

*/for the end on the last line.

PORTS : Ports are interface terminals that allow the module to communitae with other

modules.



Examples:

Input in_0,in_1;

Output s_out,c_out;

GATE DELAYS:A hardware description language must use modeling that allows the simulation to

include time delays.delays are specificed in instantitations using the pound sign that is

# as in

Nand #(prop_delay) G1(output,in_a,in_b);

Where prop_delay is the vaule of the dealy.if the rise and fall times are known

separetly they can be used by writing nand #(t_rise.t_fall) G1(output,in_a,in_b);.

A single entry implies a propagation delay ,two entries implies tr and tf valus,while

three entries implies the turn off time.

7.AOI GATEAIM: To design AOI gate [with and without delays] in GATE level modeling using verilog code.

DESCRIPTION : AND - OR – INVERTER [AOI] circuit is built using and gate, OR gate and not gate which is equivalent to use AND and NOR gate. We also requires wires i.e., wire keyword identifies w1 and w2 as interval values that are needed to describe network but are not i/p and o/p ports.

Usage: AOI analysis the SOP Expression.

EXPRESSION FOR OUTPUT:

f =

SYMBOL:



a,b,c&d are inputs and f is output.

CIRCUIT DIAGRAM:

TRUTH TABLE:



VERILOG CODE:



gate level modelling (with delay):

module aoi(

input a,

input b,

input c,

input d,

output f);

wire w1,w2;

and #(100) a1(w1,a,c);

and #(100) a2(w2,b,d);

nor #(100) a3(f,w1,w2,a,b);

endmodule

OUTPUT WAVEFORM:



VERILOG CODE:

Gate level modeling( without delay):

module aoi(

input a,

input b,

input c,

input d,

output f);

wire w1,w2;

and a1(w1,a,c);

and a2(w2,b,d);

nor a3(f,w1,w2,a,b);



endmodule

OUTPUT WAVEFORM:



8.HALF ADDER

AIM : To design Half adder with and without delays] in Gate level modeling using Verilog.

DESCRIPTION: A half adder is a logical circuit that performs an addition on two binary digits as inputs and produces an two binary digits outputs as Sum and Carryout.

Half adder is built from XOR gate and AND gate.

Half adder adds to one bit binary numbers.

Advantage:

Half adder would be used to add the least Significant bits in ripple carry adder, as this addition can have no carry input.

It is significantly less complex than full adder.

It saves on hardware in the situation where carry input is not needed.

Drawback:

Half adder cannot be used for multi bit addition since it cannot include a carry input.

Equations or formula:

Sumout = a b

Carryout = Cout = a . bWhere a &b are inputs to half adder circuit and Sumout and Carryout are outputs.



SYMBOL:

CIRCUIT DIAGRAM:



Truth Table:



VERILOG CODE:

Gatelevel modeling(without delay):

module halfadd(

input a,

input b,

output sumout,

output cout);

xor(sumout,a,b);

and(cout,a,b);

endmodule



OUTPUT WAVEFORM:



VERILOG CODE:

Gatelevel modeling(with delay):

module halfadd(

input a,

input b,

output sumout,

output cout);

xor #(100,20) (sumout,a,b);

and #(100) (cout,a,b);

endmodule



OUTPUT WAVEFORM:

9.FULL ADDER



AIM : To design full adder [ with and without delays] in Gate level modeling using Verilog.

DESCRIPTION: The 3-bit full adder circuit adds 3- one.bit binary number Cin, a, b as inputs and produces an output two one bit numbers as Sumout and Carryout(Cout).

Full adder is simply 2 half adders joined by an OR gate. The o/p of XOR gate is called Sumout and o/p of AND gate is carry [ w2 & w3].

Advantages:

Full adders are used in nbit binary words [multiput i/p].

It is usually a component in a cascade of adders which add 8,16,32 etc, binary numbers. Carry i/p for full adder circuit is from carry o/p from circuit “above” itself in cascade. The carry o/p from full adder is fed to another full adder “below” itself in cascade.

Disadvantage:

Complex than half adder.

Equations or formulae:

Sumout = a b Cin

Cout = (a . b) + (Cin.(a b))

Cout = (a . b) + (Cin . a) + (Cin . b)

SYMBOL:



CIRCUIT DIAGRAM :

TRUTH TABLE:



INPUTS OUTPUTS

a b cin sumout Cout

0 0 0 0 0

0 1 0 1 0

1 0 0 1 0

1 1 0 0 1

0 0 1 1 0

0 1 1 0 1

1 0 1 0 1

1 1 1 1 1

VERILOG CODE:

gate level modelling(without delay):



module fulladd(

input a,

input b,

output sumout,

output cout);

wire w1,w2,w3;

and(w3,a,b);

xor(w1,a,b);

xor(sumout,w1,cin);

and(w2,w1,cin);

or(cout,w2,w3);

endmodule

OUTPUT WAVEFORM:



VERILOG CODE:

gatelevel modelling(with delay):module fulladd(

input a,

input b,

output sumout,

output cout);

wire w1,w2,w3;

and #(100) (w3,a,b);

xor #(100) (w1,a,b);

xor #(100) (sum,w1,cin);

and #(100) (w2,w1,cin);

or #(100) (cout,w2,w3);



endmodule

OUTPUT WAVEFORM:



10.SR LATCHAIM: To design SR latch [with and without delays] in gate level modeling using verilog code.

DESCRIPTION : SR Latch circuit is built making use of 2 NOR gate that are cross coupled [i.e the output of one NOR gate is passed as an input to another NOR gate]

Usage:

A Latch is a storage device that can receive and hold an input bit.

A Latch is transparent [that is a change can be seen in outputs]

SR Latch has 2 inputs S & L and produces two outputs Q and ~Q.

Disadvantages: When both inputs are one the outputs are invalid or undetermined state.

Equation or expression of outputs:

Q= R+Qbar

Qbar = S+Q



SYMBOL:

S Q bar

R Q

LOGIC DIAGRAM:


SR

LATCH


TRUTH TABLE

INPUTS OUTPUTS

S R Q Qbar

0 0 Previous previous

0 1 0 1

1 0 1 0

1 1 0 0

when S=0 and R=0 , the output Q will have the previous state.

When S=0 and R=1, it is in the reset state.

When S=1 and R=0, it is in the set state.

When both S=1 and R=1, the output is invalid or undetermined.



SR LATCH Gatelevel modeling code without delay

module srlatch(

input S,

input R,

output Q,

output Qbar);

nor n1(Qbar,S,Q);

nor n2(Q,Qbar,R);

endmodule



OUTPUT:

SR LATCH Gatelevel modeling (with delay)

module srlatch(

input S,

input R,



output Q,

output Qbar);

nor #(100) n1(Qbar,S,Q);

nor #(100) n2(Q,Qbar,R);

endmodule

OUTPUT:



11.MUXES USING BUFFER

AIM : To design 2:1 Mux using tristae buffer in gate level modeling using verilog code.

DESCRIPTION: Multiplier can be considered as multiple inputs and single output switch.

2:1 mux have 2 inputs and produces a single output depending upon the select input [s]

2:1 mux is designed using 2 buffers that is active low buffer and active high buffer

Active low buffer is on when input is zero

Active high buffer is on when input is one

EXPRESSION :

out = . + . s



SYMBOL( 2:1 MUX USING BUFFER)

CIRCUIT DIAGRAM:



TRUTH TABLE (2:1 MUX USING BUFFER)

INPUTS OUTPUT

P0 P1 S Out

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 1



VERILOG CODE (WITHOUT DELAY):

module mux(

input p0,

input p1,

input s,

output out);

bufif0(out, p0, s);

bufif1(out, p1, s);

endmodule



OUTPUT:



VERILOG CODE( WITH DELAY ):

moduel 2_1mux(

input p0,

input p1,

input s,

output out);

bufif0 #(100) (out,p0,s);

bufif1 #(100) (out, p1, s);

endmodule



OUTPUT :



RTL MODELING

BEHAVIORAL AND RTL MODELING:

Verilog behavioural modeling is based on specifying a group of concurrent procedures that characterize a block. The basis for behavioural modeling is the construction of procedural blocks.a procedural block is a listing of statements that describe how a sset of operations are performed. Procedural blocks contain assignments statements , hilgh level constructs such as loops and conditional



statements and timing control. There are two types of blocks that start with the keywords “initial “ and “always”. An initial block executes once in the simulation and is used to set up initia conditions and step by step data flow and always block executes in aloop and repeats during the simulation. The block statements are used to gropu two or more statements together. Sequential statements are inserted between the keywords “begin’ and ‘end”.

It is also possible to write concurrently executed statements using th fork and join keywords.

DATA FLOW MODELING AND RTL:

Data flow modeling describes a system by how the data moves and is processed. Assign keyword is used in RTL modeling. Data flow description is a high level abstraction that does not provide structural details.

12. 4:1 MULTIPLEXER IN RTLAIM: to design 4:1 multiplexer in RTL modeling using verilog code

DESCRIPTION: Multiplexer or mux is a device that performs multiplexing, it selects one of that into a single line digital input signals and outputs that into a single line

4:1 mux is built using 4 AND gates, 2 NOT gate and one OR gate.



Each AND gate has 3 inputs[ that is 4 inputs a to d is applied to one input of AND gate, 2 inputs are select inputs to AND gate]

Select lines s0 ans s1 are decoded to select a particular AND gate to produce an output of

a.~s0.~s1to G1 AND gateb.s0.~s1 to G2 AND gatec.~s0.s1 to G3 AND gated.s0.s1 to G4 AND gate

EXPRESSION

f = (a . . ) + (b . . ) + (c . . ) + (d . . )

SYMBOL:



CIRCUIT DIAGRAM:

TRUTH TABLE:



INPUTS OUTPUT

S1 S0 d c b a

f

0 0 0 0 0 0

0 0 1 1

0 1 0 1

1 1 0 1

0

1

1

1

0 1 0 0 0 0

0 0 0 1

0 1 1 0

0

0

1

1 0 0 0 0 0

0 0 0 1

0 1 0 1

1 0 1 1

0

0

1

0

1 1 0 1 1 1

0 0 0 1

1 1 1 1

1 0 0 0

0

0

1

1

VERILOG CODE:

module mux41(



input a,

input b,

input c,

input d,

input s0,

input s1,

output f);

wire w1,w2,w3,w4;

assign w1=a&~s1&~s0;

assign w2=b&~s1&s0;

assign w3=c&s1&~s0;

assign w4=d&s1&s0;

assign f=w1|w2|w3|w4;

endmodule

OUTPUT(MUX4:1):



13. 8:1 MULTIPLEXER AIM: To design 8:1 MUX in RTL MODELING using Verilog code.

DESCRIPTION:

An electronic multiplexer can be considered as multiple –input ,sinle-output switch i.e performing multiplexing.

8:1 MUX has 8 inputs,i[7] toi[0] and one single output f amd 3 select a , b and c.

8:1 mux has each 8 input lines i[7] to i[0] is applied to two 4:1 mux and 2 outputs.

Obsereved are again combuned using a 2:1 mux using total of three selection lines a, b and c and decoded to select to produce an o/p “f”.

Muxes are use din telecommunication applications.




f = (i[0] . . . ) + (i[1] ] . . . c) + (i[2] . . b . ) + (i[3] . . b . c) + (i[4] . a . . ) + (i[5] . a . . c) + (i[6] . a . b . ) + (i[7] . a . b . c)

SYMBOL:

CIRCUIT DIAGRAM:



TRUTH TABLE(8:1 MUX)

Select Inputs output

a b c f0 0 0 i[0]0 0 1 i[1]0 1 0 i[2]0 1 1 i[3]1 0 0 i[4]1 0 1 i[5]



1 1 0 i[6]1 1 1 i[7]

VERILOG CODE

module mux81(

input [7:0] i,

input a,

input b,

input c,

output f);

wire w0,w1,w2,w3,w4,w5,w6,w7,x0,x1;



assign w0=i[0]&~a&~b&~c ;

assign w1=i[1]&~a&~b&c ;

assign w2=i[2]&~a&b&~c ;

assign w3=i[3]&~a&b&c ;

assign w4=i[4]&a&~b&~c ;

assign w5=i[5]&a&~b&c ;

assign w6=i[6]&a&b&~c ;

assign w7=i[7]&a&b&c ;

assign x0=w0|w1|w2|w3;

assign x1=w4|w5|w6|w7;

assign f=x0|x1;

endmodule

OUTPUT:



14. 2:4 BINARY DECODERAIM: To design 2-4 Binary Decoder in RTL modeling using verilog code.

DESCRIPTION: A decoder is a device which does the reverse of an encoder, undoing the encoding so that original information can be retrieved decoder is a multiple input, multiple output logic. Circuit that converts coded inputs into coded outputs where the input and output codes are different. Ex: n to 2n, BCD decoders.

APPLICATIONS: Data multiplexing, 7-segment display and memory address decoding.

2 Types of Binary Decoder.

(1) Active high decoder: It sets a 1 on the selected line and keep others at zero.

(2) Active low decoder: It set zero on the selected line and keep others at 1.

Simplest decoder circuit would be AND gate because the output of AND gate is high.

(1) Only when all its inputs are high such output is called as active high output.

2-4 binary decoder have 2 inputs lines s0 and s1 that combinationally pass

through 4 AND gates to provide 4 lines output d0,d1,d2,d3.

EXPRESSION FOR OUTPUTS:

= .

= .



= .

= .

SYMBOL:

s1 s0

d0d1

d2 d3

CIRCUIT DIAGRAM


2:4

Binary

decoder


TRUTH TABLE( 2:4 BINARY DECODER)

Input Outputss1 s0 d0 d1 d2 d30 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1



VERILOG CODE:

module decoder 24(

input s0,

input s1,

output d0,

output d1,

output d2,

output d3);

assign d0 = ~s1&~s0;

assign d1 = ~s1&s0;



assign d2 = s1&~s0;

assign d3 = s1&s0;

endmodule

OUTPUT:



15. 4to2 PRIORITY ENCODERAIM: To design 4to2 Priority Encoder in RTL modeling using Verilog code.

DESCRIPTION: A priority encoder examines the input bits of an n bit word and produces an output that indicates the position of highest priority Logic 1 bit.

4 bit priority encoder is a circuit basically converts the 4 bit input into 2 bit binary representation. If the input ‘n’ is active, all lower inputs (n-1….0) are ignored.

Each output is driven by an OR gate which is connected to NAND-INV outputs of the corresponding input lines. NAND gate of each stage receives its input bit as well as the NAND gate outputs of all higher priority stages. An active input on stage n effectively disables cell lower stages n-1…0.

Circuit function does not depend at all on least significant input bit.

APPLICATIONS:

Used for intercept controllers.

They are used when multiple components(eg: processor, memory, I/O devices, etc) are to share a common resource(eg: a bus). Each component is assigned certain priority whenever there is conflict, the highest priority component will be granted usage of resource.


= 1 . + . 1 + . 0 + . 0

= +

= 1 . + . 0 + . 1 + . 0

= +



SYMBOL

CIRCUIT DESIGN



x0 is dummy

TRUTH TABLE

Input output

x3 x2 x1 x0 y1 y0

1 x x x 1 1

0 1 x x 1 0

0 0 1 x 0 1

0 0 0 x 0 0



VERILOG CODE:

module priority42(

input x0,

input x1,

input x2,

input x3,

output y0,

output y1);

wire w0,w1;

assign w0 = ~(x2&~x3);

assign w1 = ~(w0&~x3&x1);

assign y0 = x3|~w0;

assign y1 = x3|~w1;

endmodule



OUTPUT:

16. D-FLIP FLOP:AIM:To design d-flip flop in RTL modeling using verilog code.

DESCRIPTION :flipflop is a storage device which can hold or store 1 bit numbers.



A flipflop differs from latch in that it is nontransperent. D flipflop(DFF) is most

commonly used flipflop in CMOS circuits.

Basic DFF design is master-slave configuration obtained by cascadfing two oppositively phased d latches.

Two types of master slave flipflop 1. Positive edge triggered2. Negative edge triggered.

Master slave positive edge triggered d-flipflop:It is obtained by applying input d and d-bar to master,clock signal

(clk) is directly given to slave and (~clk)is given to master outputs .outputs of master

are given to slave and slave outputs are q and q-bar.additionally preset and clear

intput is given to master to preset the output q=1 and clear the output q=0.

Clock signal controls the operation and synchronization. Preset and clear inputs are active low inputs i.e, if preset(pr)=0 then

q=1->irrespective of d=1 or 0 clear(cr)=0 then q=0 ->irrespectiveof d=0 or 1. D flipflop is built using 8 nand gates If preset =1 or clear=1 then output normal flipflop If preset and clear=0 cannot be same as zero simultaneously .

LOGICAL SYMBOL:



CIRCUIT DIAGRAM:


q_bar d

pr

cr

q

q

q_bar

master slave

w2

w1 w3 w5

w4 w6

clk


TRUTH TABLE ( D-FLIP FLOP)

Inputs Output

D Clk Pr Cr q q bar

0

1

0

0

1

1

X

1

1

1

0

0

1

0

1

1

0

1

1

1

1

1

1

1

1

1

0

0

0

1

1

0

1

0

0

1

0

0

1

0

1

1



VERILOG CODE:module Dflipflop(

input d,

input clk;,

input pr,

input cr,

output q,

output qbar);

wire w1,w2,w3,w4,w5,w6;

assign w1=~(qbar&d&(~clk));

assign w2=~(q&(~d)&(~clk));

assign w3=~(pr&w1&w4);

assign w4=~(cr&w2&w3);

assign w5=~(w3&clk);


assign q=~(w5&qbar);

assign qbar=~(w6&q);

endmodule



OUTPUT WAVEFORM:

17. JK FLIP FLOP:AIM : To design J-K flipflop in RTL modeling using verilog code.

DESCRIPTION:

Flip flop is a storage element based on gated latch principle which can have it’s output state changed only on the edge of controlling clock signal.

JK flipflop combines the behavior of SR &T flipflops. It behaves as SRflipflop when J=S & K=R for all input values except J=K=1, it behaves as T flipflop & toggles it’s state.

JK flipflop is a versatile circuit.

It can be used for storage purpose.

It can serve as T flipflop by connecting J&K inputs together.



JK flipflop with presert & clear inputs is designed using 8 NAND gates. It is positive edge triggered flipflop.

LOGIC SYMBOL



CIRCUIT DIAGRAM:

TRUTH TABLE:



Inputs Outputs

j k Pr Cr Clk Q Qbar

X X 1 0 1 0 1

0 0 1 1 1 0 1

0 1 1 1 1 0 1

1 0 1 1 1 1 0

1 1 1 1 1 1/0 0/0

When both pr and cr=1 and j=0 and k=1, the flip flop is in reset state.

When both pr and cr=1 and j=1 and k=0, the flip flop is in set state.

When both pr and cr=1 and j=1 and k=1, the flip flop is in toggle state.

VERILOG CODE:



module JKflipflop(

input j,

input k,

input pr,

input cr,

input clk,

output Q,

output Qbar);


assign w1=~(Qbar&j&(~clk));

assign w2=~(Q&(~k)&(~clk));





assign Q=~(w5&Qbar);

assign Qbar=~(w6&Q);

endmodule

OUTPUT :



18. T FLIP-FLOPAIM:to design t-flipflop in RTL modeling using verilog modeling.

DESCRIPTION:T Flipflop name is derived from the behavior of circuit which toggles its state when T=1.this toggle feature makes this flipflop a useful element for building counter circuit.

T –flipflop positive edge triggered is built using eight NAND gate .

It is obtained by applying input t and t-bar to master,clock signal(clk) is directly

given to slave and (~clk)is given to master outputs .outputs of master are given to

slave and slave outputs are q and q-bar.additionally preset and clear intput is given to

master to preset the output q=1 and clear the output q=0.

Clock signal controls the operation and synchronization. Preset and clear inputs are active low inputs i.e, if preset(pr)=0 then



q=1->irrespective of t=1 or 0 clear(cr)=0 then q=0 ->irrespectiveof T=0 or 1. T flipflop is built using 8 nand gates If preset =1 or clear=1 then output normal flipflop If preset and clear=0 cannot be same as zero simultaneously .

LOGIC SYMBOL:

preset

clk

clear

CIRCUIT DIAGRAM:


t q

qbar


TRUTH TABLE (T-FLIP FLOP):

INPUTS OUTPUT

t Clk pr cr q q bar

1

1

1

1

1

1

0

1

0

1

0

1

0

1

0

0

1

1

1

1

0

1

1

0

0

1

1

1

1

1

0

0

1

1

1

0

0

1

1

0

0

0



VERILOG CODE:module Tflipflop(

input t,

input clk,

input pr,

input cr,

output q,

output qbar);


assign w1=~(q bar&t&(~clk));

assign w2=~(q&(~t)&(~clk));







assign q=~(w5&q bar);

assign qbar=~(w6&q);

endmodule

OUTPUT :



19. GATED D-LATCH:AIM: To design Gated-D-Latch in RTL modeling using verilog code.

DESCRIPTION: Latch is storage device that receive and hold an input bit. It is transparent.

USAGE:

D latch is a variation of SR latch that is to overcome the problem of SR latch when both s and r are equal to one then we get invalid output. So in D latch, single ‘D’ input is also inverted to provide signal to reset latch.

D latch cannot experience a rare condition caused by all inputs at logic 1 simultaneously.

D latch circuit is built using 2 AND gate and 2 NOR gates cross coupled.

In this we have 2 inputs‘d’ and enable bit and 2 outputs q and q bar.


If enable e = 1

q = d

q-bar = not (d) =



SYMBOL:

d

Q

e Q bar

enable=e

CIRCUIT DIAGRAM:


D

LATCH


TRUTH TABLE :



RTL modeling:

VERILOG CODE:

module dlatchI(

input d,

input e,

inout Q,

inout Qbar);

wire S,R;

assign S=d&e;

assign R=~d&e;

assign Q=~(Qbar|R);

assign Qbar=~(Q|S);

endmodule



OUTPUT:



SIMPLE LAYOUT

DIAGRAMS

MICROWIND-2 AND DSCH-2 ARE USER FRIENDLY TOOLS FOR DESIGN AND STIMULATION .

DSCH-2 : Digital schematic editor and simulator of version 2-software.

The DSCH program is a logic editor and simulator .

DSCH is used to validate the architecture of logic circuit before the microelectronic

design is started.



DSCH provides a user friendly environment for hierarchical logic design and fast

simulation.

DSCH 2 is the companion software for logic design based on primitive, a hierarchical

circuit is built and simulated. Interactive symbols such as keyboards, led and displays

are used for friendly simulation. which includes delay and power consumption

evaluation.

MICROWIND-2 : Microwind version 2 software is used to draw mosfet layout and simulates the behavior.

Microwind software allows the designer to simulate and design an integrated circuit at

physical description level.

It includes all the comments for a mask editor as well as digital tools never gathered

before in a single module.

Microwind works as a comprehensive layout and simulation tool and can be applied

to micro engineering and science.

Layout diagram is used to describe about each layers of CMOS fabrication.

Layout of basic structure has following steps

STEP(0) - start with p-type substrate.

STEP(1) - n well

STEP(2) - active

STEP(3) - poly

STEP(4) - p select

STEP(5) - n select

STEP(6) - active contact

STEP(7) -poly contact

STEP(8) - metal 1



STEP(9) - via

STEP(10) - metal 2

STEP(11) – over glass

20. DRAW A LAYOUT OF NOT GATE

AIM: To design NOT logic gate in switch level modeling using verilog

code



Description: The NOT or INVERT function is often considered the

simplest Boolean operation.

NOT logic gate Cmos is built using one PFET and one NFET. Gate

input ‘a’ is given common to both FETS and o/p ‘f’ is drawn

connecting both FETS in series.

If gate i/p a=0 then PFET mp is ON and NFET mn is off. This

connect the o/p node ‘f’ to power supply voltage VDD (i/p) giving

an o/p f=1

If the gate i/p a=1 then NFET mn is on and PFET mp is off. This

connect the o/p node f to ground (i/p).

Expression for o/p:

f = . 1 + a . 0 =

f = NOT ( a ) =

Symbol:

CMOS Diagram:



TRUTH TABLE:

OUTPUT:


INPUT OUTPUT

a F

0

1

1

0




21. DRAW A LAYOUT OF NAND GATE

AIM: TO design NAND logic gate in switch level modeling using

Verilog code.

Description: NAND gate is called as universal gate. NAND2 logic gate

CMOS circuit is built using 2 parallel connected PFET and 2 series

connected NFET.

If gate inputs a = b = 1 then PFET are off [p1 & p2] and NFET [n1

& n2] are ON. This connecting ground (i/p) to o/p node f = 0.

If either of gate inputs is zero then o/p node f=1.

NAND gate is complement of AND gate.



NAND function is negation of ‘and’ function.

Expression for o/p:

f (a , b)= . 1 + . 1+ a .b . 0

f = + =

SYMBOL:

CMOS DIAGRAM:



TRUTH TABLE:

INPUT OUTPUT

a B F

0 0 1

0 1 1

1 0 1

1 1 0

OUTPUT:







22. DRAW A LAYOUT OF NOR GATE



AIM:-To design NOR logic gate in Switch level modeling using Verilog

code.

DESCRIPTION:-NOR is an universal gate.

NOR2 logic gate CMOS circuit is built using two series PFET (p1&p2)

and two parallel connected NFET (n1&n2).

If both inputs a=b=0 then PFET p1&p2 are ON and NFETS (n1&n2) are

off. This connects the VDD input to output node f=1

If either gate inputs is one then output f=1.

NOR gate is complement of NAND gate.

NOR gate is negation of OR gate.


f (a,b) = . .1 + .b.0 + a. .0+a.b.0

f(a,b)= . =

SYMBOL:



CMOS DIAGRAM:

TRUTH TABLE:

INPUT OUTPUT

A b F

0 0 1

0 1 0

1 0 0

1 1 0



OUTPUT:







SYNTHESIS OF DIGITAL

CIRCUITS

23. RIPPLE CARRY ADDER



AIM:Implement Ripple Carry Adder in RTL and Behavioral modeling

using verilog code.

DESCRIPTION: Adding two n-bit words yields an n-bit sum and carry-out bit Cn that can either be used as carry-in to another higher order adder or act as an overflow flag.

An n-bit ripple carry adders requires n-full adders with carry-out bit Ci+1

used as carry-in bit to next column.

Ripple carry adder is cascading of full adders.

It is based on the addition equation.

Suppose 4-bit ripple carry adders(i.e n=4)

c3 c2 c1 c0

+ a3 a2 a1 a0

+ b3 b2 b1 b0

c4 s3 s2 s1 s0

ADVANTAGE:

Instead of adding single bits we can add binary words.

Easier construction of neighbouring circuits


Sumout of full adder = Si = ⊕ ⊕

Carryout=cout= + .( ⊕ )



DEMERITS:

Ripple carry latency makes slow.

Since the output of any full adder is not valid until the incoming carry bit

is valid(calculated).

Needs to ripple carry bits serially down the chain.

LOGIC SYMBOL

RIPPLE CARRY ADDER OF 4-BIT

+ :indicate fulladder

c1,c2,c3,c4 are carryout



s3,s2,s1,s0 sumout of fulladder

a0—a3, b0---b3 and c0 are input

TRUTH TABLE:

VERILOG CODE:

module RCA(



input [3:0]a,

input [3:0]b,

input cin,

output [3:0]s,

output cout);

assign {cout, s}=a+b+cin;

endmodule

OUTPUT ;



BEHAVIOURAL LEVEL:

VERILOG CODE;

module RCA(

input [3:0] a,

input [3:0] b,

input cin,

output [3:0]s,

output cout);

reg cout;

reg [3:0]s;

always @ (a or b or cin)

{cout,s}=a+b+cin;

endmodule



OUTPUT :



24. CARRY LOOK-AHEAD ADDERS (CLA)AIM: Implement CLA in RTL and behavioral modeling using verilog code.

DESCRIPTON: CLA algorithm is based on the origin of the carryout bit in the equation ci+1 = ai.bi + ci . (ai^bi)

In CLA the sumout and carryout equations are written in terms of generate and propagate terms.

Generate term ‘gi’ is used since inputs one viewed as “generating” the carryout bit.

Propagate term ‘pi’ is used where an input carry ci=1 may be propagated through the full adder.

MERITS:

CLA adders are designed to overcome the latency introduced by the rippling effect of

carry bit in ripple carry adder.

EXPRESSIONS FOR OUTPUTS :

= .

= ⊕

Carryout = = + .

Sumout = = ⊕


gi pi

ai . bi ai ^ bi

ai = bi = 0

ai = bi = 1

ai ≠ bi

0

1

0

0

0

1


LOGIC SYMBOL

SUM CALCUTATION USING CLA



CIRCUIT DIAGRAM FOR CLA:

c1 = g0 + p0 . c0

c2 = g1 + p1 . c1 = g1 + p1 . (g0 + p0 . c0)

c3 = g2 + p2 . c2 = g2 + p2. g1 + p2 . p1 .g0 + p2 . p1 . p0 . c0

c4 = g3 + p3 . c3 = g3 + p3. g2 + p3 . p2 .g1 + p3 . p2 . p1 . g0 + p3 . p2 . p1 . p0 . c0



TRUTH TABLE:

Inputs Output

a3 a2 a1 a0 b3 b2 b1 b0 c0 s3 s2 s1 s0 Cout

0

1

0

0

1

1

0

1

1

0

1

0

0

1

1

0

1

1

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

1

0

1

0

0

1

1



BEHAVIOURAL LEVEL:

VERILOG CODE:

module CLA(

input [3:0]a,

input [3:0]b,

input c0,

output [3:0]s,

output cout);

reg cout;

reg [3:0]s,p,g;

reg [5:0]c;

integer i;

always @ (a or b or c0)

begin

c[0]=c0;

g=a&b;

p=a^b;

for(i=0;i<=3;i+1)

begin

c[i+1]=g[i]|p[i]&c[i];

end

s=p^c;

cout=c[4];

end

end module



OUTPUT

VERILOG CODE

module CLA(

input [3:0]a,

input [3:0]b,

input c0,

output cout,

output s0,s1,s2,s3);



wire [3:0]p;

wire [3:0]g;

wire c1,c2,c3,c4;

assign g[0]=a[0]&b[0];




assign p[0]=a[0]^b[0];




assign c1=g[0]|p[0] &c0;

assign c2=g[1]|p[1] &g[0]|p[1]&p[0]&c0;

assign c3=g[2]|p[2] &g[1]|p[2]&p[1]&g[0]| p[2]&p[1]&p[0]&c0;

assign c4=g[3]|p[3] &g[2]|p[3]&p[2]&g[1]| p[3]&p[2]&p[1]&g[0]|p[3]&p[2]&p[1]&p[0]&c0;

assign s0=p[0]^c0;

assign s1=p[1]^c1;

assign s2=p[2]^c2;

assign s3=p[3]^c3;

assign cout=c4;

endmodule

OUTPUT:



25. REGISTER MULTIPLIER:AIM: To design register multiplier in RTL and behavioral modeling using verilog code.

DESCRIPTION: Binary multiplication is based on the basic operation 0x0=0, 0x1=0, 1x0=0, 1x1=1.

Multiplying two bits we use logical AND operation that produces the producta x b.

Multiply two 4-bit binary numbers a=a3a2a1a0 & b=b3b2b1b0

Product a x b given by 8-bit(2n) where n=4-bit



LOGIC SYMBOL:



Figure: Register-based multiplier network

Multiplier bits bi are used to control 2:1 mux. If bi=0, n bit zero word is sent to adder while bi=1 directs multiplicand ‘a’ to the input.

TRUTH TABLE:

INPUTS OUTPUTS

a3 a2 a1 a0 b3 b2 b1 b0 p7 p6 p5 p4 p3 p2 P1 p0

0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1

0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0



1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1

RTL LEVEL:

VERILOG CODE:module rtl(

input [3:0]a,

input [3:0]b,

output [7:0]p);

wire [7:0] w1,w2,w3,w4;



assign w1=a*b[0]*1;

assign w2=a*b[1]*2;

assign w3=a*b[2]*4;

assign w4=a*b[3]*8;

assign p=w1+ w2 + w3+ w4;

endmodule

OUTPUT :



BEHAVIOURAL LEVEL;

VERILOG CODE:

module m2(

input [3:0] a,

input [3:0]b,

output [7:0]p);

reg [7:0] w1,w2,w3,w4;

reg [7:0]p;

always @ ( a or b )

begin

w1=a*b[0] *1;

w2=a*b[1] *2;

w3=a* b[2]*4;

w4=a* b[3]*8;

p=w1 + w2 + w3 +w4;

end

endmodule



OUTPUT :

26. ARRAY MULTIPLIERAIM: To design an array multiplier in RTL and behavioral modeling using verilog code.

DESCRIPTION: An array multiplier accepts the multiplier and multiplicand & uses an array of cells to calculate the bit products aj.bk individually in parallel manner. Each block requires to calculate bit product ajbk and then add to other contibutions in coloumn i=(j+k)



Array multiplier accepts all of the inputs bits simultaneously.

Array multiplier for n bit words requires n(n-2) full-adders, n-half adders and n2 AND gate.(4bit array multiplier requires 8-fulladders,4-halfadders and 16-and gates)

P7 originates from carry hit from p1 column and propagates through p2-p6

LOGICAL SYMBOL OF 4*4 ARRAY MULTIPLIER:



.



Fig:Details of 4x4 array multiplier



TRUTH TABLE:

inputs Outputs

a3 a2 a1 a0 b3 b2 b1 b0 p7 p6 p5 p4 p3 p2 p1 p0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 1 0 1 1 1 0 0 0 0 1 1 1 1 0 0

1 1 1 0 1 1 0 1 0 1 0 0 0 1 0 0



VERILOG CODE:

module amp(

input [3:0] a,

input [3:0]b,

Output [7:0]p);

wire [10:0]c;

wire [20:0]w;

assign p[0]=a[0]&b[0];

assign w[0]=a[0]&b[1];


assign {c[0],p[1]}=w[0]+w[1];



assign {c[1],w[4]}=w[2]+w[3];


assign {c[2],p[2]}=w[4]+w[5]+c[0];



assign {c[3],w[8]}=w[7]+w[6];


assign {c[4],w[10]}=w[8]+w[9];

assign w[11]=a[0]&b[3];

assign {c[5],p[3]}=w[10]+w[11]+c[2];

assign w[12]=a[2]&b[2];

assign w[13]=a[3]&b[1];

assign {c[6],w[14]}=w[12]+w[13];

assign w[15]=a[1]&b[3];

assign {c[7],w[16]}=w[14]+w[15];

assign {c[8],p[4]}=w[16]+c[5];



assign w[17]=a[2]&b[3];

assign w[18]=a[3]&b[2];

assign {c[9],w[19]}=w[18]+w[17]+c[6];

assign {c[10],p[5]}=w[19]+c[7]+c[8];

assign w[20]=a[3]&b[3];

assign {p[7],p[6]}=w[20]+c[9]+c[10];

endmodule



OUTPUT :


Documents

HDL(HARDWARE DEFINITION LANGUAGE)deccancollege.ac.in/ITLABMANUALS/VLSILABMANUAL.doc · Web viewINDEX. S NO CONTENTS/PROGRAM NAME Page No . INTRODUCTION . I Hardware Description