Hdl-V3a Selected Upgraded 1 - Student Copy

8/3/2019 Hdl-V3a Selected Upgraded 1 - Student Copy

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What is VHDL?What is VHDL?VHDL: VHSIC Hardware Description

Language

VHSIC: Very High Speed IntegratedCircuit

Developed originally by USDOD (United State,Developed originally by USDOD (United State,

Department ofDepartment of DefenceDefence).).

for specifying digital systems Hardwarefor specifying digital systems HardwareDescription, Simulation, SynthesisDescription, Simulation, Synthesis


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vlsivlsi

Front endFront end BackBack endend

Designing &Designing &

TestingTesting PartPartUsesUses VHDL,VHDL, verilogverilog andand

OtherOther HDLsHDLs

DevelopmentDevelopment &&

Fabrication PartFabrication Part

Too costly and timeToo costly and time

consuming processconsuming process


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Back ENDBack END

BackBack endend consistconsist of of thethe manufacturingmanufacturing &&fabricationfabrication partpart ofof chipchip designdesign..

InIn realreal worldworld thethe manufacturingmanufacturing andand fabricationfabrication

ofof ICsICs oror chipschips areare veryvery costlycostly inin termsterms ofofmoneymoney andand timetime also,also, andand theythey areare alsoalso veryverycomplexcomplex toto developdevelop becausebecause ofof somesome typicaltypicalconditionsconditions likelike 100100AA..


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VHDL CONSIST OF

Sequential languages.Sequential languages.

Concurrent languages.Concurrent languages.

Net list languages.Net list languages.

Timing specification.Timing specification.

Waveform generation languageWaveform generation language..


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Basic FeaturesofVHDLBasic FeaturesofVHDL

Concurrency.Concurrency.VHDL executes statements at theVHDL executes statements at the

same time insame time in parallel,asparallel,as in Hardware.in Hardware.

Support sequential statements.Support sequential statements.SupportsSupports HirerchiesHirerchies..

Support test and simulation.Support test and simulation.

Strongly typed language.Strongly typed language.Support user defined libraries andSupport user defined libraries andpackages and data types.packages and data types.


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Systemsmay designusingVHDLSystemsmay designusingVHDL

Microcontrollers, Microprocessors,Microcontrollers, Microprocessors,

RAM

DDRRAM

DDR--2,DDR2,DDR--3,3,Mobile chips.Mobile chips.

Automation chips, CNC machines,Automation chips, CNC machines,

Robots like ASIMO,Robots like ASIMO,

Traffic Light Controllers, etc.Traffic Light Controllers, etc.


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Simulation ModelingSimulation Modeling

VHDL programs describe the generation of events in digital systemsVHDL programs describe the generation of events in digital systems

Discrete event simulator manages event ordering and progression ofDiscrete event simulator manages event ordering and progression oftimetime

Now we can quantitatively understand accuracy vs. time tradeNow we can quantitatively understand accuracy vs. time trade--offsoffs

Greater detailGreater detail more eventsmore events greater accuracygreater accuracy

Less detailLess detail smaller number of eventssmaller number of events faster simulation speedfaster simulation speed

b

a sum

carry

VHDL Model

compiler

Discrete Event SimulatorfromVendor


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ModellingModelling StylesinVHDLStylesinVHDL

DataflowDataflow

BehavioralBehavioral

StructuralStructural

DataData FlowFlow levellevel

InIn thisthis stylestyle ofof modelingmodeling thethe flowflow ofof datadatathroughthrough thethe entityentity isis expressedexpressed usingusingconcurrentconcurrent signalsignal assignmentassignmentstatementsstatements..

StructuralStructural levellevel

InIn thisthis stylestyle ofof modelingmodeling thethe entityentity isisdescribeddescribed asas aa setset of of interconnectedinterconnectedstatementsstatements..

BehavioralBehavioral levellevel ThisThis stylestyle of of modelingmodeling specifiesspecifies thethe

behaviorbehavior ofof anan entityentity asas aa setset ofof statementsstatementsthatthat areare executedexecuted sequentiallysequentially inin thethespecifiedspecified orderorder..


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Method ofWritingthe codeMethod ofWritingthe code

foran ICforan IC

Three types ofThree types ofdeclarations aredeclarations arerequired to writerequired to write

a program ina program inVHDL to design anVHDL to design anIC.IC.

LibraryLibrarydeclarations.declarations.

EntityEntitydeclarationdeclaration

ArchitectureArchitecturedeclaration.declaration.

BasicBasic VHDL codestructureVHDL codestructure


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Library DeclarationLibrary Declaration

SyntaxSyntax

LibraryLibrary library_namelibrary_name;;

UseUse library_name.package_name.clauselibrary_name.package_name.clause;;

ExampleExample

librarylibrary ieeeieee;;use ieee.std_logic_1164.all;use ieee.std_logic_1164.all;


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my_ckt

A

B

S

X

Y

VHDL entityVHDL entityentityentitymy_cktmy_ckt isis

port (port (

A: in bit; A: in bit;

B: in bit;B: in bit;S: in bit;S: in bit;

X: out bit;X: out bit;

Y: out bitY: out bit

););

endendmy_cktmy_ckt;;

Name of the circuit User-defined Filename same as circuit

name Example.

Circuit name: my_ckt Filename: my_ckt.vhd

Port names orSignal names

Name of the circuit User-defined Filename same as circuit

name recommended Example:

Circuit name: my_ckt Filename: my_ckt.vhd

Datatypes: In-built User-defined

Direction of port

3 main types: in: Input out: Output inout: Bidirectional

Note the absence of semicolon; at the end of the last signaland the presence at the end ofthe closing bracket


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EntityEntity--Architecture PairArchitecture Pair

entity name port names port mode (direction)

port type

reserved words

punctuation


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VHDL IDENTIFIERSVHDL IDENTIFIERS

Identifiers are used to name items in a VHDLIdentifiers are used to name items in a VHDLmodel.model.

A basic identifier may contain only capital AA basic identifier may contain only capital A -- ZZ

, a, a -- z,z,00 -- 9, underscore character _9, underscore character _

Must start with a alphabet.Must start with a alphabet.

May not end with a underscore character.May not end with a underscore character.

M

ust not include two successive underscoreM

ust not include two successive underscorecharacters.characters.

Reserved word cannot be used as identifiers.Reserved word cannot be used as identifiers.

VHDL is not case sensitive.VHDL is not case sensitive.


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OBJECTSOBJECTS

There are three basic object types in VHDLThere are three basic object types in VHDL

Signal : represents interconnections that Signal : represents interconnections that

connect components and ports.connect components and ports. Variable : used for local storage within a Variable : used for local storage within aprocess.process.

Constant : a fixed value. Constant : a fixed value.

The object type could be a scalar or an array.The object type could be a scalar or an array.


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Keywords in VHDLKeywords in VHDL

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Hdl-V3a Selected Upgraded 1 - Student Copy