HBZVR-Type Single-Phase Transformerless PV grid connected … · clamping method is suitable for transformerless PV inverters due to improved CMV and low leakage current [17]-19].The

International Journal of Electronics Engineering Research.

ISSN 0975-6450 Volume 9, Number 6 (2017) pp. 791-808

© Research India Publications

http://www.ripublication.com

HBZVR-Type Single-Phase Transformerless PV grid

connected Inverter with Constant Common-mode

voltage

Ahmad Syed1 and Tara Kalyani Sandipamu2*

1,2EEE Department, Jawaharlal Nehru Technological University Hyderabad, Kukatpally, Hyderabad, India.

Abstract

Transformerless photovoltaic (PV) inverters are attractive in grid-connected

applications due to the advantages of lower cost, smaller in weight and higher in

efficiency compared to isolated systems. Nonetheless, reduction of leakage current

should be carefully considered, when designing a transformerless inverter because of

the high operational risk and high output current distortion. According to the

international standards, the leakage current must be suppressed within permissible

levels. This paper reviewed the complete elimination of the leakage current using

HBZVR-based inverter. Subsequently, the relationship among the existing topologies

and the performance of CMV clamping branches are also investigated. Based on the

analysis, a simple HBZVR-type transformerless PV inverter is proposed. To verify

the accuracy of the proposed topology, the theoretical findings are validated via

Matlab/Simulink. Finally, a universal prototype is built and tested for validation of

both theoretical and simulation results.

Keywords: Photovoltaic (PV) inverter, HBZVR, leakage current, common mode

voltage (CMV).

I. INTRODUCTION

The energy demand is increasing due to fact that the rapid increase of the human

population and fast-growing industries [1] - [5]. Recently, photovoltaic (PV) energy has

become very popular because of government incentives, declining price of PV arrays

mailto:[email protected],[email protected]



792 Ahmad Syed and Tara Kalyani Sandipamu

and advancement of semiconductor technology [4]. PV inverters are usually

categorized into with transformer and without transformer grid-tied systems.

Traditionally, PV inverter is embedded with low frequency transformer on the AC

side and high frequency transformer on DC side. Nonetheless, the transformer

increases the cost, size and the difficulty in installation [8]-[9]. Therefore,

transformerless PV inverters are introduced with reduced size, weight and higher

efficiency [6]-[7]. In order to suppress the leakage current in transformerless PV

inverter, the common mode voltage (CMV) must be kept constant [10]-[11].

According to German VDE 0126-1-1 standard, the grid must be disconnected within

0.3s if the root-mean-square value of the leakage current is more than 30 mA [16].

The root mean square value of the leakage current and their corresponding maximum

allowable disconnection time are illustrated in Table 1. Many transformerless

topologies have been proposed to solve the issues of leakage current and low

conversion efficiency in [5]-[25]. A family of half bridge inverter is proposed in [18].

However, half Nonetheless, it leads to high switching losses and magnetic inductor

losses, which results in lower conversion efficiency. On the other hand, the CMV

clamping method is suitable for transformerless PV inverters due to improved CMV

and low leakage current [17]-19].The required conditions for improved CMV is the

potential of the freewheeling path should be clamped to half input voltage during the

freewheeling periods, instead of disconnect the PV array from the utility grid. Based

on this principle, different topologies were introduced in [17]-[25]. In [18], author

Kerekes et al, introduce the new freewheeling path via passive elements (diode),

which allows only one way of directional clamping, results relatively poor CMV in

freewheeling periods. Suan [19] et al brings the additional diode to solve the issues of

floating voltage and leakage current. Apparently, the performance of the CMV and

leakage current are different among the discussed topologies due to clamping ability.

In this paper HBZVR based clamping transformerless inverter is reviewed. A simple

PV inverter is then proposed by adding one bidirectional switch, which ensures the

half input DC-link voltage during freewheeling periods.

Table 1. Leakage current value and corresponding disconnection time illustrates in

VDE 0126-1-1 standard [16].

Leakage current(mA)

Disconnection

time(s)

30 0.3

60 0.15

100 0.04

150 0.04

HBZVR-Type Single-Phase Transformerless PV grid connected Inverter… 793

This results in constant CMV and thus low leakage current. Finally, a universal

prototype has been built to validate the performance of the proposed topology.

This paper is organized as follows: Existing single phase transformerless topologies

are reviewed in section 2, proposed topology and its operating principles are

discussed in section 3. Loss analysis is carried out in sections 4, Simulation and

experimental tests are presented in section 5 and section 6 respectively. The final

conclusion is reported in section 7 to summarize the observations and results.

II. REVIEW ON EXISTING TRANSFORMERLESS TOPOLOGIES

In this section, existing HBZVR type clamping inverters are reviewed in detail. The

CMV of the PV systems, can be calculated as

𝑉𝑐𝑚 =𝑉𝐴𝑁+𝑉𝐵𝑁

2 (1)

(a) HBZVR It extends the principle of HERIC (Highly Efficient and Reliable Inverter Concept)

topology with a passive clamping method known as HBZVR (H-bridge zero voltage

state rectifier), as shown in Fig.1 (a). The operating principle is almost similar to the

HERIC topology with an additional clamping function which is implemented through

an active switch and four diodes. Due to limitations of the clamping branch, CMV is

floating in one half of the grid period. As a result, leakage current is increased.

(b) HBZVR-D As shown in Fig.1 (b), HBZVR-D (H-bridge zero voltage state rectifier diode) is

recently introduced by modifying the HBZVR [18]. To improve the common-mode

behaviour, one additional fast-recovery diode D6 is added to the freewheeling path, to

fully clamp the CMV to constant, and the leakage current is eliminated. It is clearly

seen that the clamping branch is important as it determines the common-mode

behaviour of the PV system.

gridPV

S1

S2

S3

S4

S5 D1

D2

D3

D4

L1

L2

CDC1

CDC2

CPV1

CPV2

A

B

VAN VBN

P

N

D5

(a)


gridPV

S1

S2

S3

S4

S5 D1

D2

D3

D4

L1

L2

CDC1

CDC2

CPV1

CPV2

A

B

VAN VBN

P

N

D5

D6

(b)

Fig. 1. Existing topologies (a) HBZVR [18], (b) HBZVR-D [19].

III. PROPOSED TOPOLOGY

According to the above analysis, a simple modified HBZVR topology is proposed by

adding of one bidirectional switch at midpoint of the DC-link known as HBZVR-S

(H-bridge zero voltage state rectifier switch), as shown in Fig.2. In addition, switches

S1-S4 are employed in the full bridge inverter; the clamping circuit consists of four

diodes D1-D4, switches S5 and S6. The filters are made up of L1 and L2 (L2=L1) at

the grid lines. With the clamping effect, the CMV is clamped to half of the DC input

voltage.

gridPV

S1

S2

S3

S4

S5D1

D2

D3

L1

L2

CDC1

CDC2

CPV1

CPV2

S6

A

B

P

N

D4

(a)

gridPV

S1

S2

S3

S4

S5D1

D2

D3

L1

L2

CDC1

CDC2

CPV1

CPV2

S6

A

B

P

N

D4

(b)


(c)

Fig. 2. (a) Proposed topology (b) Proposed topology with different locations of the

clamping branch (S6) (c) Modulation scheme (S1-S6).

Table 2. Operation modes, switching states, differential mode voltage and common

mode voltage under USPWM

S1 S2 S3 S4 S5 D1 D2 D3 D4 VAN VBN VDM VCM

1 0 0 1 0 0 0 0 0 VDC 0 +VDC VDC/2

0 0 0 0 1 0 1 1 0 VDC/2 VDC/2 0 VDC/2

0 1 1 0 0 0 0 0 0 0 VDC -VDC VDC/2

0 0 0 0 1 1 0 0 1 VDC/2 VDC/2 0 VDC/2

If compared with existing topologies presented in Fig.1, the difference among

proposed topology is automatically observed in the freewheeling path ability.

Furthermore HBZVR-S topology simplifies the CMV clamping branch, from few

diodes to one single switching device. It is reported in [28] that active clamping is

more superior to passive clamping method in terms of loss distribution. The loss

analysis will be carried out in a later section.

(a) Analysis and Modes of operation: The operating principles of the proposed topology and its equivalent circuits are

illustrated in four modes, which are depicted in Fig.3.

In Mode1: During the positive half cycle S1, S4 is turned on and remains off, inductor

current increases and flows through S1,S4, equivalent circuit as shown Fig.3 (a). In

this mode VAN=VDC, VBN=0 and VAB=+VDC, therefore the common mode voltage can

be derived as 𝑉𝑐𝑚 =𝑉𝐴𝑁+𝑉𝐵𝑁

2=

1

2(𝑉𝐷𝐶 + 0) =

𝑉𝐷𝐶

2= 0.5𝑉𝐷𝐶 (2)

In Mode2: During the positive freewheeling period the S5 on and other turned off,

inductor current decreases and freewheels via D2, D3 and the grid lines, equivalent

circuit as shown in Fig.3 (b). In this mode VAN=VDC/2, VBN=VDC/2 and VAB=0,

therefore the common mode voltage can be derived as



2=

1

2(

𝑉𝐷𝐶

2+

𝑉𝐷𝐶

2) =

𝑉𝐷𝐶

2= 0.5𝑉𝐷𝐶 (3)

In Mode3: During the negative half cycle S2, S3 are turned on and remains are turned

off, inductor current increases and flows via S2, S3 and grid lines, equivalent circuit

as shown inFig.3 (c). In this mode VAN=0, VBN=VDC and VAB= -VDC, therefore the

common mode voltage can be derived as


2=

1

2(0 + 𝑉𝐷𝐶 ) =

𝑉𝐷𝐶

2= 0.5𝑉𝐷𝐶 (4)

In Mode4: During the negative freewheeling period S5 on and the other turned off,

inductor current decreases and freewheels via D1,D4, and the grid lines, equivalent

circuit as shown in Fig.3 (d). In this mode VAN=VDC/2, VBN=VDC/2, therefore

common mode Voltage can derive

gridPV

S1

S2

S3

S4

S5D1

D2

D3

L1

L2

CDC1

CDC2

CPV1

CPV2

S6

A

B

P

N

D4

(a)

gridPV

S1

S2

S3

S4

S5D1

D2

D3

L1

L2

CDC1

CDC2

CPV1

CPV2

S6

A

B

P

N

D4

(b)

gridPV

S1

S2

S3

S4

S5D1

D2

D3

L1

L2

CDC1

CDC2

CPV1

CPV2

S6

A

B

P

N

D4

(c)


gridPV

S1

S2

S3

S4

S5D1

D2

D3

L1

L2

CDC1

CDC2

CPV1

CPV2

S6

A

B

P

N

D4

(d)

Fig.3. Equivalent circuits of proposed HBZVR-S topology (a) Conduction mode (b)

Freewheeling mode in positive half cycle,(c) Conduction (d), freewheeling mode in

negative half cycle.

as

𝑉𝑐𝑚 =𝑉𝐴𝑁 + 𝑉𝐵𝑁

2=

1

2(

𝑉𝐷𝐶

2+

𝑉𝐷𝐶

2) =

𝑉𝐷𝐶

2= 0.5𝑉𝐷𝐶 (5)

It is clear that the CMV is constant at VDC/2 and VDM varies between +VDC, 0, -VDC

isolated full bridge USPWM. Nonetheless, Table 2 shows the operation modes,

switching states and the direction of the grid-in current, the differential-mode voltage.

Hence, proposed topology is suitable for transformerless application.

b. Operating principles of the proposed clamping branch

gridPV

S1

S2

S3

S4

S5D1

D2

D3

L1

L2

CDC1

CDC2

CPV1

CPV2

S6

A

B

P

N

D4

Down

(a)

gridPV

S1

S2

S3

S4

S5

D1

D2

D3

L1

L2

CDC1

CDC2

CPV1

CPV2

S6

A

B

P

N

D4

UP

(b)

Fig.4. Equivalent circuits of the proposed topology during the clamping mode (a)

Potential down (b) Potential up.


The freewheeling branch is bidirectional. During freewheeling periods (mode 2 and

mode 4 shown in Fig.3), if the freewheeling path voltage (VFP) (VFP=VAN~VBN) is

lower than the DC-link voltage, the current freewheels through switch S6 and anti-

parallel diode of the switch S5. As a result, the freewheeling path voltage is

completely clamped the VFP to VDC/2, as shown in Fig.4. (a). On the other hand, if

freewheeling path voltage is higher than to DC-link voltage, the current freewheels

via body diode of switch S6 and anti-parallel diode of the switch S5 to increase the

freewheeling path voltage to VDC/2, as shown in Fig.4 (b).

In HBZVR, the ability of freewheeling path is limited due to unidirectional clamping

diode known as passive clamping via D5. The freewheeling path is only clamped to

half of the input voltage. The clamping path is not functioning properly due to

reverse biased D5 in one half of the cycle. This can be rectified by adding of

bidirectional switch in the proposed HBZVR-S topology. With improved clamping

branch via active switch S6, it guarantees that CMV holds to VDC/2 during the whole

freewheeling periods. Therefore, leakage current is completely reduced, which

dependent on the constant CMV, as discussed earlier.

IV. TOTAL LOSS CALCULATION AND COMPARISON IN SEVERAL

TOPOLOGIES

It is hard to measure the device losses for predicting the maximum efficiency in

power electronics converters [31].

Table 3 Analysis of device operation in discussing topologies.

Topologies Device type HBZVR HBZVR-D HBZVR-S

Number of devices IGBT 5 5 6

Switching loss IGBT 3 3 4

Conduction loss IGBT 2 2 2

Freewheeling loss IGBT 1 1 1

Diode 2 2 2

Reverse recovery losses IGBT 2 2 2

Gate loss IGBT 2 2 2

However, it is noticeable that the loss calculation is based on the theory and its

accuracy depends on the device data sheet accuracy. In this section device loss are

calculated and compared via thermal module in PSIM [30].The diode conduction

losses are calculated in the following equations (6)-(7), which is dependent on the

duty ration (D) on the device with periodically conduction.

𝐶𝑜𝑛𝑑𝑢𝑐𝑡𝑖𝑜𝑛 𝑙𝑜𝑠𝑠𝑒𝑠 = 𝑉𝑑 ∗ 𝐼𝐹 (6)


𝐶𝑜𝑛𝑑𝑢𝑐𝑡𝑖𝑜𝑛 𝑙𝑜𝑠𝑠𝑒𝑠 = 𝑉𝑑 ∗ 𝐼𝐹 ∗ 𝐷 (7)

While Vd presents the diode voltage drop and IF describes the forward current of the

diode. Similarly turn-off losses are calculated in the following equations, when the

diode is neglected.

𝑃𝑠𝑤−𝑜𝑓𝑓 = 𝐸𝑟𝑟 ∗ 𝑓 ∗𝑉𝑅

𝑉𝑅−𝑑𝑎𝑡𝑎𝑠ℎ𝑒𝑒𝑡 (8)

𝑃𝑠𝑤−𝑜𝑓𝑓 = 0.25 ∗ 𝑄𝑟𝑟 ∗ 𝑉𝑅 ∗ 𝑓 (9)

Where the reverse recovery losses are presented with the Err, Qrr recovery charge,

switching frequency ‘off’, an actual reverse blocking voltage as VR and VR_datasheet

presents reverses blocks voltage in the data sheet with characteristics of Err. Under test

conditions the Qrr can be calculated in the following equation (10).

𝑄𝑟𝑟 = 0.5 ∗ 𝑡𝑟𝑟 ∗ 𝐼𝑟𝑟 (10)

Under specific conditions, Err presents in the datasheet then losses are calculated

using Err, if not considered it can measured through Qrr .

Table 4. Total power device losses

Topology Losses (W)

Total losses(W)

Conduction losses External diode losses

HBZVR S1 S2 S3 S4 S5 S6 D1 D2 D3 D4 D5 D6

1.732 1.699 1.735 1.720 3.166 0 1.032 1.026 1.026 1.032 0.656 0 14.824

HBZVR-

D

1.725 1.718 1.720 1.727 3.176 0 1.038 1.032 1.032 1.039 0.709 0.710 15.626

HBZVR-S 1.727 1.719 1.717 1.718 2.163 0.664 1.032 1.023 1.029 1.035 0 0 13.827

And predominantly if the Qrr is not mentioned then utilize trr, Irr and finally both are

not specified and then assume the losses are null. Furthermore, in the discussed

topologies are configured with active IGBT modules, therefore the losses are

measured in the following equations (11)-(12), which conducts in both continuous

and periodical modes conditions

𝐶𝑜𝑛𝑑𝑢𝑐𝑡𝑖𝑜𝑛 𝑙𝑜𝑠𝑠𝑒𝑠 = 𝑉𝑐𝑐 ∗ 𝐼𝐶 (11)

𝐶𝑜𝑛𝑑𝑢𝑐𝑡𝑖𝑜𝑛 𝑙𝑜𝑠𝑠𝑒𝑠 = 𝑉𝑐𝑐 ∗ 𝐼𝐶 ∗ 𝐷 (12)

While Vce illustrates the saturation voltage between the collector and emitter, IC

presents the collector current and ‘D’ for duty cycle. Consequently the switching

losses of the IGBT during ON and OFF conditions are calculated in the following

equations’s.

𝐼𝐺𝐵𝑇 𝑇𝑢𝑟𝑛 𝑜𝑛 𝑙𝑜𝑠𝑠𝑒𝑠 = 𝐸𝑜𝑛 ∗ 𝑓 ∗ 𝑉𝐶𝐶 ∗ 𝑉𝐶𝐶

𝑉𝐶𝐶−𝑑𝑎𝑡𝑎𝑠ℎ𝑒𝑒𝑡 (13)


𝐼𝐺𝐵𝑇 𝑇𝑢𝑟𝑛 𝑜𝑓𝑓 𝑙𝑜𝑠𝑠𝑒 = 𝐸𝑜𝑓𝑓 ∗ 𝑓 ∗ 𝑉𝐶𝐶 ∗ 𝑉𝐶𝐶

𝑉𝐶𝐶−𝑑𝑎𝑡𝑎𝑠ℎ𝑒𝑒𝑡(14)

Where Eon & Eoff describe the energy losses during ON and OFF conditions with

switching frequency, Vcc presents the DC-bus voltage and Vcc-datasheet describes the

DC bus voltage of Eon, Eoff using datasheet under test conditions. The IGBT

FGA15N120 [30] with 1200V of rated voltage and current is loaded in the PSIM via

thermal module device database editor. Table.3 shows the distribution of device

number in HBZVR, HBZVR and HBZVR-S topologies as shown in Fig. (1)- (2)

respectively. Fig.5 shows the total losses of each switching device for the discussed

topologies. However, the loss distribution is mostly depends on the switching criteria

together with good thermal design. And other calculation methods and theoretical

analysis are studied and verified in the literature [23] -[27] which is not major

contribution in this paper. Table.4 shows the loss analysis of the discussed topologies.

On the other hand, it is shown that the proposed HBZVR-S topology has lower losses

as compared to its HBZVR-D counterpart, due to the simplified CMV clamping

branch, and also an active clamping method.

Fig.5. Device losses

V. SIMULATIONS

To verify the theoretical analysis and overall Performance of the HBZVR, HBZVR-D

and Proposed topologies are conducted in MATLAB/Simulink. And simulations

parameters are followed and listed in Table.5. The PV array is modeled with DC

supply 400V, the two parasitic capacitance (Cpv1, Cpv2) 100nF and the symmetrical

filter inductance can be considered as (L1, L2) 3mH, the filter capacitance can be

considered as (CF) 4µF, the switching frequency is 10 kHz with the grid voltage of

230V (rms) at a 50Hz frequency respectively [19].


Fig.6 shows the simulation waveforms of VAN, Vcm, VBN, Vout, Iout, and ileak for

HBZVR, HBZVR-D and proposed HBZVR-S topologies. It is clear that, large

oscillation presents in HBZVR with magnitude of 0-200V due to poor utilization of

clamping branch. As a result, leakage current will be increased significantly with

HBZVR topology, as shown in Fig.7. And HBZVR-D, proposed topologies present

constant common mode voltage with magnitude of 200V, as a result zero leakage

current is observed in both HBZVR-D, proposed topologies, which is most dependent

on CMV. Hence, from simulation results, it can be concluded that the proposed

topology with improved clamping branch using bidirectional switch could overcome

the demerits regarding CMV and leakage current.

(a) (a)

(b) (b)

0 0.02 0.04 0.060

200

400

VA

N(V

)

0 0.02 0.04 0.060

200

400

Vcm

(V)

0 0.02 0.04 0.060

200

400

Time (seconds)

VB

N(V

)

0 0.02 0.04 0.06-500

0

500

Vout(V

)

0 0.02 0.04 0.06-50

0

50I o

ut(A

)

0 0.02 0.04 0.06-0.5

0

0.5

Time (seconds)

i leak(A

)

0 0.02 0.04 0.060

200

400

VA

N(V

)

0 0.02 0.04 0.060

200

400

Vcm

(V)

0 0.02 0.04 0.060

200

400

Time (seconds)

VB

N(V

)

0 0.02 0.04 0.06-500

0

500

Vout(V

)

0 0.02 0.04 0.06-50

0

50

I out(A

)

0 0.02 0.04 0.06-0.5

0

0.5

Time (seconds)

i leak(A

)


(c) (c)

VI. EXPERIMENTAL RESULTS

In order to verify the simulation results and the effectiveness of the proposed topology

a universal prototype has been built and tested in the laboratory using same

specifications are listed in Table.5.The photograph of the test-bed experimental setup

is depicted in Fig.6. For the convenience in the simulation results grid is replaced with

resistive loads without affecting the performance [18]-[19]. All control algorithms are

realized in FPGA Spartan-6. The experimental results of the output grid current, DM

voltage VAB for the HBZVR, HBZVR-D topologies are depicted in sub Fig. 9. And

the common mode voltage and leakage current for the HBZVR, HBZVR-D and

proposed HBZVR-S topologies are illustrated in Fig.9, Fig.10. The output voltage of

three topologies follows unipolar with three level output voltage VPV, 0, -VPV, where

spikes arise during the dead time between the active and freewheeling periods with

magnitude of 200V, as shown in Fig.9 and Fig.10. And the load current is fulfilling the

requirement of IEEE 1547.std [29].Fig.9 and Fig.10 shows the experimental waveform

of VAN, 2Vcm (=VAN+VBN), calculated in the digital oscilloscope (DSO) by using the

math function)), VBN and leakage current. In all three

0 0.02 0.04 0.060

200

400

VA

N(V

)

0 0.02 0.04 0.060

200

400

Vcm

(V)

0 0.02 0.04 0.060

200

400

Time (seconds)

VB

N(V

)

0 0.02 0.04 0.06-500

0

500

Vout(V

)

0 0.02 0.04 0.06-50

0

50

I out(A

)

0 0.02 0.04 0.06-0.5

0

0.5

Time (seconds)

i leak(A

)

Fig.7. Simulation wave forms of Vout, iout, ileak for

(a) HBZVR, (b) HBZVR-D (c) proposed HBZVR-S

topologies (Top-Bottom)

Fig.6. Simulation wave forms of VAN, Vcm,

VBN and Vout, iout, ileak for (a) HBZVR, (b)

HBZVR-D (c) proposed HBZVR-S topologies

(Top-Bottom)


H-bridge Switches(S1-S4)

Clamping switches(S5,S6)

Clamping switches(S7,S8)

DSO Gate signals

FPGA Controller

Driver CircuitGround current port(CT)

DC-link Capacitors

Fig.8. Universal experimental test-bed

(a) (c)

(b) (d)

Fig.9.Tested DM.CM characteristics of HBZVR,HBZVR-D topologies (a)-(c)ig

(CH1) ,VDM (CH2),Enlarge of VDM(CH3),(b)-(d)VAN,Vcm,,VBN and ileak (Left-Right)


(a) (b)

(c) (d)

Fig.10. Tested DM.CM characteristics of the proposed topology (a)-(b)ig (CH1) ,VDM

(CH2),(b)VAN,Vcm,VBN and ileak (Left-Right),(c)-(d) Voltage stress across S1,S3 and

enlarge of gate signals of S5,S6(left),ig,S6 Z1(VS6)(Right).

topologies extra spikes are present due to junction capacitance and turn-on delay time of

the freewheeling diode. In addition, the common mode voltage fluctuation can be

minimized by using the different power switches. However, the proposed HBZVR-S

topology has excellent DM characteristics, which is good agreement with Fig.9. (a)- (b)

and Fig.10.(a). It is observed that, during negative power region CMV oscillation

present in HBZVR topology, as shown in Fig. 9 (a), which increases the leakage

current. On the other hand, the magnitudes of the measured leakage current for

HBZVR, HBZVR-D and Proposed HBZVR-S topologies are follows 45.82 mA,

21.12 mA and 21.18 mA (rms) respectively. According to listed in Table 1, the RMS

values are still minor and acceptable for transformerless PV grid connected systems.

Obvious the leakage current in HBZVR topology is double among other existing


topologies due to high frequency common mode voltage are not clamped properly as

discussed earlier. Therefore, it confirms that proposed HBZVR-S topology has a lower

leakage current compared to HBZVR topology, but closer to HBZVR-D topology.

Fig.10 (c)-(d) shows the experimental waveforms of collector-emitter voltage stress

across the switches S1, S3, S4 and gate drive signals of S5, S6.It is clear that no extra

voltage present and there is no blocking voltage of the added switch is half the DC input

voltage. As a result switching losses for the added devices are reduced significantly.

Fig.11 shows the efficiency comparison curve between HBZVR, HBZVR-D and

proposed topologies with unity power factor. The HIOKI 3198 power analyzer has

been used to measure the efficiency. It is well noted that the present efficiency

diagram covers the total device losses and filter losses, which does not include the

control circuit losses. The calculated Californian efficiency for HBZVR, HBZVR-D

and HBZVR-S are 95.25, 96.27 and 96.28 respectively [18], shown in Fig.11.

However the conversion efficiency is higher than to the HBZVR topology due to the

fact that blocking voltages of the gate drive signals of switches S5, S6 are clamped

Table 6. Performance comparisons of discussing topologies

S.No Parameter HBZVR HBZVR-D HBZVR-S

1 VLL pattern Unipolar Unipolar Unipolar

2 CMV Floating

(~200V)

Constant

Constant

3 Leakage current

(mArms)

45.84 21.12 21.18

4

THD (%)

1.9 1.8 1.6

5

Californian Efficiency

(%)

95.25 96.27 96.28

Fig.11. Efficiency analysis


half input voltage and its current through S6 is too small and little impact on the

capacitor divider, The proposed topology with HBZVR-type active clamping inverter

is a suitable candidate for high performance PV transformerless grid connected

system. It is shown that proposed topology maximum efficiency is 96.28% under full

load conditions, but higher than HBZVR. , HBZVR-D. The Californian efficiency can

be calculated by combining several weighted factors at different output power,

depicted in (15).

ŋ𝐶𝐸𝐶 = 0.04ŋ10%+ 0.05ŋ20%

+ 0.12ŋ30%+ 0.21ŋ50%

+ 0.53ŋ75%

+ 0.05ŋ100% (15)

Therefore, proposed topology with active clamping is not only eliminating the leakage

current, but also achieves higher conversion efficiency. Table 6 summarized the

performance comparisons of the all discussed topologies.

VII. CONCLUSIONS

This paper presents an improved HBZVR type inverter with active clamping method.

In addition, proposed topology has following advantages:

(1) Common mode voltage is constant during the whole the grid period, thus leakage

current is reduced significantly.

(2) The blocking voltages of the added switch are half of the input DC voltages, as a

result switching losses are reduced considerably during the whole grid period.

Above merits are validated and compared by universal prototype rated at 1kW,

230V/50Hz. Hence, it is concluded that the proposed HBZVR based clamping

inverter (known as HBZVR-S) is a suitable for high performance single-phase

transformerless PV grid connected applications.

REFERENCES

[1] Myrzik, J.M.A., Calais, M.: ‘String and module integrated inverters for single-

phase grid connected photovoltaic systems – a review’. IEEE Bologna Power

Tech Conf., 2003, pp. 1–8.

[2] Xue, Y.S., Divya, K.C., Griepentrog, G., Liviu, M., Suresh, S., Manjrekar, M.:

‘Towards next generation photovoltaic inverters’.IEEE Energy Convers.

Congr. Expo., 2011, pp. 2467–2474.

[3] Freddy Tan Kheng Suan, Nasrudin Abd Rahim, Hew Wooi Ping” Three-phase

transformerless grid-connected photovoltaic inverter to reduce leakage

currents” Clean Energy and Technology (CEAT), 2013 IEEE Conference on

277-280, Nov 2013.

[4] Can,Erol.”Novel high multilevel inverters invetigated on simulation”Electrical

Engineering (2016):1-6.DOI 10.1007/s00202-016-0396-z.

http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6775640




[5] Can,E,Sayan,H.(2016).SSPWM three phase inverter design and experimental

on unbalanced loads.Tehncickivjesnik,23(5).doi:10,17599/TV-

20150730222021.

[6] M. Victor, F. Greizer, S. Bremicker, and U. H¨ubler, “Method of converting a

direct current voltage from a source of direct current voltage, more

Specifically from a photovoltaic source of direct current voltage, into an

alternating current voltage,”U.S.Patent7

[7] Heribert, S., Christoph, S., Jurgen, K.: ‘Inverter for transforming a DC voltage

into an AC current or an AC voltage’. Europe Patent 1 369 985(A2), 13 May

2003.

[8] Can,Erol,and H.Huseyin Sayan.”PID and fuzzy controlling three phase

asynchronous machine by low level DC source three phase inverter/PID i

neizrazito upravljanje trofaznim asinhronim mototom pomocu trofaznog

izmjenjivaca slabe istosmjerne struje.”Tehnicki vjesnik.Technical Gazette

23.3(2016):753-761.

[9] Koutroulis, E., Blaabjerg, F.: ‘Methodology for the optimal design of

transformerless grid-connected PV inverters’, IET Power Electron., 2012, 5,

(8), pp. 1491–1499.

[10] Gu, Y.J., Li, W.H., Zhao, Y., Yang, B., Li, C.S., He, X.N.:‘Transformerless

inverter with a virtual DC bus concept for cost-effective grid-connected PV

power systems’, IEEE Trans. Power Electron., 2013, 28, (2), pp. 793–805

[11] M. Calais, J.Myrzik, T. Spooner, and V. G. Agilities, “Inverters for single-

phase grid connected photovoltaic system – an overview, “in Proc. IEEE

Power Electron. Spec. Conf., 2002, pp. 1995–2000.

[12] F. T. K. Suan, N. A. Rahim, and H. W. Ping, “Modeling, analysis and control

of various types of transformerless grid connected PV inverters” Proc. IEEE

Clean Energy Technol., Jun. 2011, pp. 51–56.

[13] Ahmad Syed and S.Tara Kalyani “Evaluation of single phase transformerless

photovoltaic inverters” `Electrical and Electronics Engineering: An

International Journal (ELELIJ) Vol 4, No 2, and May 2015,pp.25-39

[14] Can,E,Sayan,H.(2016)”Differential Mathematical model for the chopper

circuit.Techicki glasnik,10(1-2),13-15.

[15] Can,Erol,Sayan,H.Huseyin.”A novel SSPWM controlling inverter running

nonlinear device.”Electrical Engineering(2016):1-8 DOI 10.1007/s00202-016-

0480-4.

[16] Automatic Disconnection Device between a Generator and the Public Low-

Voltage Grid, DIN Electro technical Standard DIN VDE0126–1–1, 2005.

[17] R.Gonzales,J. Lopez, P. Sanchis, and L. Marroyo, "Transformerless Inverter

for single phase photovoltaic systems," IEEE Transactions on Power

Electronics, vol. 22, no. 2, pp. 693-697, March2007.

[18] T.Kerekes, R. Teodorescu, P. Rodriguez, G. Vazquez, and E. Aldabas,“A new

high-efficiency single-phase transformerless PV inverter topology,” IEEE

Trans. Ind. Electron., vol. 58, no. 1, pp. 184–191, Jan.2011.


[19] T. K. S. Freddy, N. A. Rahim, W. P. Hew, H. S. Che, “Comparison and

Analysis of Single-Phase Transformerless Grid-Connected PV Inverters,” ,”

IEEE Trans. Power Electron. vol. 29, no. 10, pp5358–5369, oct-2014.

[20] Wuhua li, Yunjie GU , Haoze luo , Wenfeng cui , Xiangning he , Changliang

xia “Topology Review and Derivation Methodology of Single- Phase

Transformerless Photovoltaic Inverters for Leakage current suppression”, IEEE Trans. Ind. Electron vol. 62, no. 7, july 2015.

[21] Yang, B., Li, W.H., Gu, Y.J., Cui, W.F., He, X.N.: ‘Improved transformerless

inverter with common-mode leakage current elimination for a photovoltaic

grid-connected power system’, IEEE Trans. Power Electron., 2012, 27, (2),

pp. 752–762.

[22] Yu, W.S., Lai, J.-S., Qian, H., et al.: ‘High-efficiency inverter with H6-type

configuration for photovoltaic non-isolated AC module applications’. IEEE

Appl. Power Electron. Conf. Expo., 2010,pp. 1056–1061.

[23] H. Xiao, S. Xie, Y. Chen, and R. Huang, “An optimized transformerless

photovoltaic grid-connected inverter,” IEEE Trans. Ind. Electron., vol58,no. 5,

pp. 1887–1895, May 2011.

[24] Huafeng Xiao, Xipu, ke lan,”optimized full bridge transformerless

photovoltaic grid connected inverter with low conduction loss and low leakage

current, IET power electron. 2014, vol.7.iss.4, pp.1008-1015.

[25] H. Xiao and S. Xie, “Leakage current analytical model and application in

single-phase transformerless photovoltaic grid-connected inverter,”IEEE,

Trans Comput. vol. 52, no. 4, Nov 2010.

[26] T. K. S. Freddy, N. A. Rahim,” Photovoltaic Inverter Topologies for Grid

Integration Applications chapter Advances in Solar Photovoltaic Power

PlantsPart of the series Green Energy and Technology , Publisher Springer

Berlin Heidelbergpp 13-4216 June 2016.

[27] T. K. S. Freddy, N. A. Rahim, W. P. Hew, H. S. Che” An Improved Three-

Phase Transformerless Photovoltaic Inverter with Reduced Leakage Currents” pp.45 (4.)-45 (4.) IET Jan 2014.

[28] Davide Barater, Evcarlo concari,Giampolo Butic chi,Emre Gurpinar,Dipankar

and Alberto Castellazzi “Performance Evaluation of a 3-level ANPC

photovoltaic grid connected inverter with 650V Sic devices and optimized

PWM”,14-18 Sept 2014,proc.IEEE ECCE,pp.2233-2240.

[29] "IEEE Standard Conformance Test Procedures for Equipment Interconnecting

Distributed Resources with Electric Power Systems," IEEE Std 1547.1-2005, pp. 0_1-54, 2005.and Exposition (ECCE), sept 2015, pp.442-449.

[30] PSIM User’s Guide.(2007 [Online]. http://www.psim europe. com.

[31] G. vazquez, T. kerekes, A. rolan, D. Aguilar, A. Luna, and G. azevedo, Losses

and CMV evaluation in transformerless grid-connected PV topologies in Proc.

IEEE Int. Symp. Ind. Electron 5–8, Jul. 2009 pp. 544–548.

http://link.springer.com/book/10.1007/978-3-662-50521-2

http://link.springer.com/book/10.1007/978-3-662-50521-2

http://link.springer.com/bookseries/8059

Documents

HBZVR-Type Single-Phase Transformerless PV grid connected … · clamping method is suitable for transformerless PV inverters due to improved CMV and low leakage current [17]-19].The