hArteshArtes OverviewOverview

hArteshArteshArteshArtes

hArteshArteshArteshArtes

hArteshArteshArteshArtes

HHolisticolistic AApproach to pproach to RReconfigurableeconfigurable real real TTimeime

EEmbedded mbedded SSystemsystems

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hArteshArteshArteshArtes What’s hArtes?What’s hArtes?

hArtes: FP6 applied research integrated project (IP)Started on 01 Sept 2006 currently in specification development phase17.3 M€ cost, 10.15 M€ funding

61% industry, 39% university

3 years duration140 person month14 Partners, 5 Nations6 Universities, 6 Companies, 2 Research Centers

hArtes web site: www.hartes.org (under construction)

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hArteshArteshArteshArtes hArtes objectiveshArtes objectives

Develop a toolchain and a methodology supporting effective automatic or semi-automatic design of complex heterogeneous embedded systems.Design a scalable heterogeneous and reconfigurable hardware platform that can be re-targeted to produce optimized real-time embedded systems.Validate the tool chain on a set of innovative applications in the audio and video field

“To develop the next generation of technologies, methods and tools for modelling, design, and implementation and operation of hardware/software systems embedded in intelligent devices. An end-to-end systems vision should allow building cost-efficient ambient intelligence systems with optimal performance, high confidence, reduced time to market and faster deployment.”

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hArteshArteshArteshArtes hArtes: holistic visionhArtes: holistic vision

Reduce time spent dealing with implementation details

OEMOEMThalesThalesFaitalFaital

ThomsonThomson

SOLUTIONsAtmelLeaff

Scaleo Chip

ALGORITHMsALGORITHMsFraunhofer IGDFraunhofer IGDUni P. MarcheUni P. MarcheUni d’AvignonUni d’Avignon

TOOLsTOOLsTU DelftTU Delft

Poli MilanoPoli MilanoImperial CollegeImperial College

InriaInriaUni FerraraUni Ferrara

Strong Industrial / Academic Collaboration to develop tool chain for heterogeneous

reconfigurable multichip platforms

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hArteshArteshArteshArtes Objectives of the tool chainObjectives of the tool chain

Holistic approach:Fill the gap between algorithms, architectures, integration and test groupsFacilitate the management of the entire flow, to allow identifying optimisation opportunities hidden in different parts of the design

Reduced time to market.Start from high level application description using graphical entry, domain specific languages or CSupport the automatic system implementation

System flexibility through:ReconfigurabilityEasier design space exploration to identify the best system solution: from feasibility to optimalityManage product variants

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hArteshArteshArteshArtes hArtes tool chain top level hArtes tool chain top level flowflow

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hArteshArteshArteshArtes Tool chain detailsTool chain details

TUD

Atmel+TUD

TUD

TUD

Imperial

Imperial

Imperial

Imperial

Polimi

Generic GPP (C+macros)

GPP Molen code

DSPC code

FPGA

Annotated C Annotations

C2C

Profiling

TaskPartitioning

TasksTransformation

DataRepresentation

DecisionMapping

CodeGeneration

Annotated C

Annotated C

Annotated C

Annotated C

Annotated C

Annotated C

GPP comp Molen DSP comp C2VHDL

ELF obj ELF obj ELF obj Bitstream

Linker

Loader

Executable code (ELF)

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hArteshArteshArteshArtes Performance improvement in Performance improvement in hArteshArtes

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hArteshArteshArteshArtes hArtes toolchain innovationhArtes toolchain innovation

Innovations of the hArtes tool chain include:a framework that allows implementing novel algorithms for design space exploration, supports design partitioning automation, task transformation, choice of data representation, and metric evaluation for HW and SW components;a system synthesis tool producing near optimal implementations that best exploits the capability of each type of processing element; dynamic HW reconfigurability can be exploited to support system upgrade or adaptation to operating conditions;diagrammatic and textual formats in algorithm description and exploration.

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hArteshArteshArteshArtes hArtes hArtes applicationsapplications

Standard and Legacy applications AND innovative applications for:

In car / home / office speech and audio enhancementWavefield synthesis for audio applicationsAudio surveillance and controlVideo applications

Allowing:Testing and validation of the tool chain on complex use casesDemonstration of the achievements

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hArteshArteshArteshArtes hArtes ApplicationshArtes Applications

ACIS = Advanced Car Information System. Includes advanced audio, speech processing enhancement and speech / speaker recognitionImmersive audio. Includes audio acquisition and reproduction for different environments Video processing. Includes legacy video and challenging video transcoding

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hArteshArteshArteshArtes Advanced Car Information System Advanced Car Information System (ACIS)(ACIS)

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hArteshArteshArteshArtes hArtes ACIS on the road hArtes ACIS on the road

hArtes based ACIS

prepre

pre

other systems connections (radio-TV, GPS, UMTS, network, etc.)

mediastorage

microphones loudspeakers

Windows PC

hARTES platform

other sys(cabin)

remote web access

ampliampli

ampli

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hArteshArteshArteshArtes Immersive audioImmersive audio

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hArteshArteshArteshArtes hArtes application platform hArtes application platform hypothesishypothesis

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hArteshArteshArteshArtes hArtes HW platformhArtes HW platform

Scope of the HW platform:Provide a flexible, reconfigurable platform for the selected application domain where the hArtes tool chain can be exercised.Must provide an heterogeneous, reconfigurable platform and the appropriate set of interfaces. Detailed specification ongoing in strict relation with the Application partners

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hArteshArteshArteshArtes

HDK dissemination initiativeHDK dissemination initiative

HDK FREE - hArtes Development Kit with Floating point for Real time Embedded EquipmentObjective: academic + SME dissemination & hands-on tool for workshops

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hArteshArteshArteshArtes Consortium compositionConsortium composition

Partners:INDUSTRY: Atmel (it), FAITAL (it), Thales (fr), Thomson (fr)

SME: LEAFF (it), Scaleo Chip (fr)

ACADEMIA: TU Delft (nl), PoliMi (it), UNIVPM (it), INRIA (fr), Fraunhofer (de), Imperial College (uk), UNIFE(it), Université d’Avignon-LIA (fr)

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hArteshArteshArteshArtes Partners rolePartners role

ApplicationsUNIVPM, FAITAL, Thales, Fraunhofer, Thomson, LIA

Tools / methodologies: TU Delft, PoliMi, Imperial College, INRIA, LEAFF

Hardware:Atmel, UNIFE, Scaleo Chip

Integration / Proof of conceptAtmel, UNIVPM, FAITAL, Thales, Fraunhofer, Thomson

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hArteshArteshArteshArtes Partners rolePartners role

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hArteshArteshArteshArtes Project Duration/BudgetProject Duration/Budget

Project Duration: 3 Years Project Budget: 17 M€

10.5 M€ Funding – Biggest funding in Embedded Systems– Highest evaluation score (27)

Work Packages:WP0. Project management.WP1. Requirements for tools and target applications.WP2. Methodology and tool development.WP3. Demonstrations and Evaluations.WP4. System Integration and Validation.WP5. Exploitation and dissemination.