Harmonic Analysis and Improvement of a New Solid State Fault Current Limiter

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1012 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 40, NO. 4, JULY/AUGUST 2004

Harmonic Analysis and Improvement of a NewSolid-State Fault Current Limiter

M. M. R. Ahmed , Member, IEEE , Ghanim A. Putrus, Li Ran , Member, IEEE , and Lejun Xiao

Abstract—This paper presents a harmonic study on a newlydeveloped solid-state fault current limiter. Using this device, thesupply voltage sag is reduced when a short-circuit fault occurs ona cable feeder in the downstream network, hence improving thepower quality. The device will eventually isolate the faulted partfrom the healthy network. Harmonics caused by the fault currentlimiter are analyzed and a method is proposed to prevent unde-sirable harmonic interactions. Analytical and experimental resultsare compared with existing regulations. It is verified that, with pre-cautions, the operation of the solid-state fault current limiter willnot cause problems to either the supply network or the loads.

Index Terms—Fault current limiters, harmonics, power qualityand switched-mode power supply (SMPS).

I. INTRODUCTION

FAULT CURRENT limiters are being developed to improve

the performance of distribution networks. Advantages

of using a fault current limiter include reduced fault level

of the supply and smaller voltage sag during a short-cir-

cuit fault. These will avoid upgrading switchgears during

system expansion and improve the power quality delivered

to customers. Previous studies have proposed designs with

impedance insertion, switched using semiconductor devices[1], [2]. Superconducting fault current limiters are also being

developed [3], [4]. A shortcoming with previous fault current

limiters using impedance insertion is that the limited faultcurrent varies with the supply system condition and fault

location. In addition, operation time is limited due to power

dissipation in the impedance, which is usually very resistive.

For such reasons, a new solid-state fault current limiter was

proposed [5] and more recently developed. The semiconductor

devices in the proposed fault current limiter are controlled in a

repetitive switching pattern during operation so that the fault

current is always limited to a predetermined level. A side effect

Paper ICPSD-01-D5, presented at the 2001 IEEE Rural Electric Power Con-ference, Little Rock, AR, April 29–May 2, and approved for publication in theIEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Rural Electric Power

Committee of the IEEEIndustryApplications Society.Manuscript submitted forreview May 15, 2001 and released for publication April 12, 2004. The work of M. M. R. Ahmed was supported by Northern Electric Distribution Ltd., U.K.,and the Egyptian Government through a scholarship to study at NorthumbriaUniversity.

M. M. R. Ahmed is with the Industrial Education College, Cairo, Egypt(e-mail: [email protected])

G. A. Putrus is with the School of Engineering and Technology, NorthumbriaUniversity, Newcastle upon Tyne NE1 8ST, U.K. (e-mail: [email protected])

L. Ran is with the School of Engineering, University of Durham, DurhamDH1 3LE, U.K. (e-mail: [email protected])

L. Xiao is with the School of Engineering, University of Salford, ManchesterM45 7FN, U.K. (e-mail: [email protected])

Digital Object Identifier 10.1109/TIA.2004.830774

Fig. 1. Construction of FCLID.

of the repetitive switching of the semiconductor devices is that

harmonics are generated. This paper considers the harmonic

characteristics, and the effects on supply system and loads nearthe fault current limiter.

This paper first outlines the construction and operation of

the new solid-state fault current limiter. Its features are sum-

marized. The mechanism of harmonic generation is then an-

alyzed and a MATLAB/SIMULINK model proposed to pre-

dict the harmonic level. The calculated harmonics are checked

against IEEE standard 519–1992 [6] and the U.K. standard G5/3

[7], regarding short-duration harmonics. A control method is

proposed to improve the harmonic signature. Laboratory exper-

iments are performed to verify the harmonic calculation and the

control method. Tests are also carried out to investigate the risk

and solutions regarding harmonic resonance with power factor

correction capacitors in the network or cable capacitance. The

effect on sensitive loads such as switched-mode power supplies

(SMPSs) in the customer loads is also investigated.

II. FAULT CURRENT LIMITING AND INTERRUPTING DEVICE

(FCLID)

The solid-state fault current limiter concerned in this study is

actually an FCLID. Fig. 1 shows the configuration of a single-

phase FCLID. It consists of a high-speed bidirectional switch

realized using power semiconductor devices such as insulated

gate bipolar transistor (IGBT), a varistor (nonlinear resistor),

and a snubber circuit, all connected in parallel.

In operation without a fault, the semiconductor devices areconstantly gated on. Alternatively, the whole FCLID can be by-

passed using a circuit breaker to avoid losses. The bypass cir-

cuit breaker is opened when the FCLID is required to operate.

Considering that a short-circuit fault occurs on the load side,a semiconductor device will initially conduct the fault current.

The switch is turned off when the fault current reaches a preset

value which should be within the interrupting capability

of the semi-conductor device. The fault current is, thus, diverted

to the varistor. The clamping voltage of the varistor is set to be

higher than the peak supply voltage. Therefore, the current in

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AHMED et al.: HARMONIC ANALYSIS AND IMPROVEMENT OF A NEW SOLID-STATE FAULT CURRENT LIMITER 1013

Fig. 2. FCLID incorporated in a typical distribution network.

Fig. 3. Current through FCLID.

the faulted circuit starts to decrease. The varistor voltage re-

mains almost constant as long as it is conducting. The semicon-

ductor device is turned on again to reestablish the current as it

reduces to a preset low value . Switching logic is the same

for both positive and negative half cycles of the fault current

and the operation is maintained for a specified period of time

which is useful to collect information about the fault location

and to coordinate protection relays [8]. If the fault persists, the

semiconductor devices are turned off permanently, after a cer-

tain time, and the fault current is completely interrupted.

To illustrate the above operating principle, a simulation model

is established using MATLAB/SIMULINK for the single-phase

230-V system shown in Fig. 2 [9]. It is assumed that the pre-fault

load current is less than 40 A. Without the fault current limiter,

the prospective peak short-circuit current at the busbar of Load 4

is 1 kA. The value changes to 2, 3, and 4 kA if the fault location

is at Load 3, Load 2, and Load 1, respectively. Busbar A is thepoint of common coupling (PCC) with other cable feeders.

For the case of a fault at Load 4, the maximum through cur-

rent, which is potentially 1 kA without the FCLID, is limited by

the fault current limiter to A. Fig. 3 shows the cur-

rent through the fault current limiter. is set to 0 A (practi-

cally the small leakage current of the varistor) in this case. The

simulation is performed for three half cycles only. As will be

shown later, the corresponding laboratory model of the FCLID

is able to operate for about 1 s. The features of the proposed

FCLID can be summarized as follows.

1) The limited fault current is independent of the supply

system condition and fault location. The maximum, min-

Fig. 4. Spectrum of FCLID current.

imum, and average values of the current are all deter-

mined by the controller.

2) The current-limiting function is achieved via the insertionof the varistor. Power dissipation in the varistor may be

carefully dealt with such that the FCLID can operate for

a considerable period of time. A method was developed

to provide equal current sharing between parallel varistors

[10].

3) The rate of change of the current depends on the total

series inductance in the circuit, the supply system con-

dition, and fault location. Therefore, these will affect

the switching frequency of semiconductor devices in the

FCLID.

4) The varistor presents its clamping voltage when con-

ducting but the supply source voltage is time variant.

Therefore, the switching rate is not constant even withina half cycle.

While the proposed FCLID provides some very desirable

characteristics, it is also clear from the above that the FCLID

will exhibit some special harmonic characteristics which should

be carefully analyzed.

III. HARMONIC CALCULATION AND IMPROVEMENT

Fig. 4 shows the frequency spectrum of the current waveform

shown in Fig. 3. In deriving the spectrum, the current was sam-

pled for one fundamental cycle and Fourier analysis was then

applied to the sample. It is observed that the harmonics origi-

nate from two distinct mechanisms: the harmonics around theaverage switching frequency of the semiconductor devices in

the FCLID, and the lower order harmonics due to the constant

and modulation control. The latter have similar dis-

tribution to the harmonics in a square wave [11].

Referring to Fig. 2, the simulated voltage waveforms across

the FCLID and at the PCC (A) are shown in Fig. 5. During oper-

ation, the FCLID alternatively presents the clamping voltage of

the varistor (varistor conducting) and about 0 V (switch turned

on) in series in the power circuit. The voltage across the FCLID

(upper trace) is, therefore, very distorted. As for the voltage at

the PCC, the harmonics in the FCLID voltage are divided be-

tween source impedance and the impedance from the PCC to





Fig. 5. Voltage across FCLID and at PCC.

Fig. 6. FCLID current with I m i n = 5 0 A.

the fault. Therefore, as long as the FCLID is installed close to a

strong supply and the fault location is sufficiently far from the

FCLID, the voltage at the PCC before the fault current limiter

will be close to a sine wave. For this reason, an extra inductor

may be integrated in the fault current limiter, or protective mea-

sures are taken in the controller so that the FCLID does not re-

spond when the fault is very near to it.

Other feeders connected to the PCC will be subjected to the

voltage waveform shown in Fig. 5. Little voltage sag may be

present during the fault. Also, the voltage will be more dis-

torted for a fault closer to the fault current limiter. Addition-ally, the harmonic current shown in Fig. 3 must be absorbed by

the supply system. It is, therefore, advisable to improve the har-

monic characteristics of the fault current limiter.

A method to reduce the harmonic content in the current

during the operation of the fault current limiter is to modify the

switching strategy. Instead of turning on the switches when the

current reduces to 0 A, the semiconductor devices can be turned

on at a higher current level. Fig. 6 shows the simulated current

waveform with A. Its spectrum is shown in Fig. 7.

It is observed that the effect of increasing is to re-

duce the bandwidth of the limited fault current. This will in-

crease switching frequency. Therefore, device switching loss

Fig. 7. Spectrum of FCLID current with I m i n = 5 0 A.

and system fault level should be considered. The harmonics in

the FCLID current are of higher frequency and can be more

easily absorbed using a passive filter at the PCC. The voltageat the PCC will also be slightly improved.

IV. STANDARDS REGARDING SHORT-DURATION HARMONICS

There are two main recognized standards dealing with the

short-duration harmonic as their main goal. These are:

IEEE Standard 519–1992, which states that for short-du-

ration harmonics “Devices such as a thyristor-controlled

drive applied to a rolling mill generate short duration

harmonic currents as the material passes through the mill.

Generation of intermittent harmonics and the resulting

voltage stress on the capacitors, the transformers, and

other apparatus is sometimes more tolerable than the stresscaused by the constant generation of harmonics.” [6].

Engineering Recommendation G5/3, which states that

“short duration transients are tolerable provided the

current bursts and related voltage distortions are of an

intermittent nature, e.g., the burst duration does not

exceed 2 seconds and the interval between bursts is not

less than 30 seconds. The principal concern is to prevent

damage to other plant such as capacitors. Provided that

the fundamental voltage at the metering point does not

exceed the nominal supply voltage plus 6 per cent, there

should be no risk of damage.” [7].

Operation of the fault current limiter is a rare event as com-

pared to a rolling mill drive. Its duration is usually less than 2 s.

According to the above standards, the harmonics produced by

the fault current limiter may not be a problem. This is particu-

larly the case if the harmonics are reduced using the modulation

control. However, the risk of damage to the FCLID and other

equipment must be prevented. Therefore, it is important to in-

vestigate the possibility of harmonic resonance with the supply

network and loads connected to the PCC.

V. CONSIDERATION OF HARMONIC RESONANCE

It has been shown that duringthe operation of theFCLID, rich

harmonics over a quite wide spectrum band are produced. The





Fig. 8. Harmonic current flow.

worst case is that some harmonics could coincide with the nat-

ural frequencies of the circuit formed by power factor correction

capacitorat the PCC and the supplysystem impedance in the up-

stream. If this happens, the harmonics injected into the supply

system will be amplified and overvoltage/overcurrent may cause

damage to the plant. To analyze the situation, harmonic current

flow analysis for the distribution network shown in Fig. 2 has

been carried out. A simple equivalent circuit of the network isshown in Fig. 8, where the FCLID is assumed to be a source

of harmonic current . The current at any harmonic frequency

divides between the shunt capacitor and supply as

where istheharmoniccurrentgenerated, istheharmonic

current that flows into the supply system, and is the har-

monic current that flows into the capacitor.

Then,

(1)

(2)

where and are the impedances of the supply system and

capacitor, respectively, at the frequency examined.

Harmonic resonance corresponds to the case when the induc-

tive reactance of the supply equals the capacitive reactance of

the capacitor. Both and will be greater than . Anal-

ysis is performed for different values of the capacitance and

system fault level. The ratio is plotted in Fig. 9 for a

system fault level of 1 kA. The shunt capacitance is varied from

1 to 10 mF and the resonant peak is captured for each capaci-

tance value. It is clear that the switching frequency should avoidthe range from 200 to 800 Hz. If the switching frequency of the

FCLID is increased above 800 Hz by setting proper and

, there will be no risk of parallel resonance.

It is worth pointing out that this is the worst case where

power-factor-correction capacitors are connected directly at

the PCC of the FCLID, point A in Fig. 2. Normally, when

capacitors are connected in the distribution network, the PCC

will be at a higher voltage level.

The cable capacitance and inductance could also introduce a

resonant mode. For the 230-V single-phase circuit, the cable ca-

pacitance is about 1 F/km and inductance is about 230 H/km.

Fig. 10 shows the relationship between the resonance frequency

Fig. 9. Resonant peak with different capacitance.

Fig. 10. Resonance frequency versus cable length.

and cable length. The supply fault current level is assumed to be

1 kA.

It is clear that for cables shorter than 5 km, which is usually

the case, there is no risk of resonance as long as the switching

frequency of the FCLID is under 2 kHz. Too high a switching

frequency should also be avoided from the device point of view

to prevent excessive switching losses.

VI. EXPERIMENTAL RESULTS

An experiment was set up for the network shown in Fig. 2,

where the line current and voltage as well as the current in other

load connected at the PCC were recorded. Fig. 11 shows a cycle

of theline current with set to 120 A and set to 50 A.

Its spectrum is shown in Fig. 12. Good agreement is observed

with previous simulation results. Earlier analysis and conclu-

sions based on computer simulation are, therefore, validated.

VII. EFFECT OF FCLID ON SMPS

Typical loads that are most sensitive to the distorted wave-

forms produced by the FCLID are domestic and commercial

electronic equipment such as a personal computer (PC) and

television (TV). Such equipment normally includes SMPS. As

shown in Fig. 13, the SMPS derives its power from the utility

supply via a diode rectifier with a capacitively smoothed dc link.





Fig. 11. Measured FCLID current waveform (I = 1 kA).

Fig. 12. Spectrum of measured FCLID current.

Fig. 13. SMPS.

The input current is usually discontinuous as shown in Fig. 14. It

is useful to consider the effects of the proposed FCLID on such

load when connected to the PCC in the distribution network.

A main concern is that the FCLID may affect the operation

of the SMPS due to the high rate of change of voltage when

the semiconductor device in the FCLID is turned off and the

clamping voltage of the varistor appears across the FCLID. Test

has been performed for a case when the short-circuit fault is far

from the FCLID. The prospective fault current is 1 kA. A PC is

connected in front of the FCLID. Figs. 15 and 16 show the PC

Fig. 14. Input current to SMPS.

Fig. 15. PC current with a remote fault.

Fig. 16. PC voltage with a remote fault.

current and voltage waveforms. For a fault close to the FCLID,

the corresponding waveforms are shown in Figs. 17 and 18.





Fig. 17. PC current with fault close to FCLID.

Fig. 18. PC voltage with fault close to FCLID.

It is shown that the high applied at the input of the

SMPS will be seen by the dc-link capacitor, causing input cur-

rent spikes. The spikes are higher when the fault is close to the

fault current limiter and, hence, the PCC. The current spikes

may exceed the fuse rating of the SMPS and cause fuse fatigue.

Fig. 17 shows the moment when the PC fuse blew at 220 ms

after the fault current limiter started operating.

The second problem which may arise, particularly when thefault is close to the FCLID, is that more zero-crossing points

are introduced in the voltage waveform. This may affect the

operation of equipment that is phase locked to the sinusoidal

supply voltage. A simulation model is used to recreate the situ-

ation shown in Figs. 17 and 18. The results are given in Figs. 19

and 20. Similar signatures can be observed between the simu-

lation and experiment if the measured waveforms are zoomed

in. As a solution to the above problem, a small inductor of 100

H may be inserted in series with the FCLID. The simulation

results for this case are shown in Figs. 21 and 22. The rating

of the inductor depends on and the required duration of

FCLID operation. Referring to the analysis about harmonics in

Fig. 19. Simulated PC current.

Fig. 20. Simulated PC voltage.

Fig. 21. PC current with series inductor.

Section III, it is generally advisable to include a series inductor

with the FCLID proposed.





Fig. 22. PC voltage with series inductor.

VIII. CONCLUSION

This paper has investigated the problems associated with har-

monic generation in a new solid-state FCLID. Simulation and

test were performed regarding the application of the FCLID in

a typical 230-V single-phase distribution network. Factors af-

fecting the harmonic characteristics were identified. The risk of

harmonic resonance and adverse effect on sensitive loads such

as SMPSs were assessed. Remedy actions were recommended.

The results obtained from simulation and the experimental test

show the following.

1) Operation of the proposed FCLID will produce harmonic

current into the supply system which can be reduced by

increasing .

2) The short-duration harmonics produced by the FCLIDcomply with the harmonics standards (IEEE 519–1992

and G5/3).

3) Proper measures can be taken to avoid the risk of har-

monic resonance between the cable or power-factor-cor-

rection capacitance, and the supply network inductance.

Insertion of a small series inductor will attenuate the un-

desirable effects on sensitive loads such as SMPS. The

voltage waveform at the PCC is also improved.

4) Provided that a detailed system study is carried out, the

major problems regarding harmonics in the proposed

FCLID are generally solvable.

ACKNOWLEDGMENT

The authors would liketo thank Northern ElectricDistribution

Ltd., U.K., and the Regional Center for Electronic Technology

(ReCET), U.K., for their support to and advice on this work.

This paper describes part of a development work, the results

of which have been submitted in a patent application.

REFERENCES

[1] R. K. Smith, P. G. Slade, and H. Mehta, “Solid-state distribution currentlimiter and circuit-breaker application requirements and control strate-gies,” IEEE Trans. Power Delivery, vol. 8, pp. 1155–1164, July 1993.

[2] T. Ueda, M. Morita, and H. Arita, “Solid-state current limiter forpower distribution system,” IEEE Trans. Power Delivery, vol. 8, pp.1796–1801, Oct. 1993.

[3] A. J. Power, “An overview of transmission fault current limiter,” in IEE Colloq. Fault Current Limiter — A Look at Tomorrow, June 1995, Dig.1995/026, pp. 1/1–1/5.

[4] L. Salasoo, “Comparison of superconducting fault limiter concepts inelectric utility applications,” IEEE Trans. Appl. Superconduct., vol. 5,pp. 1079–1082, June 1995.

[5] G. A. Putrus, N. Jenkins, and C. B. Cooper, “A static fault current lim-iting and interrupting device,” in IEE Colloq. Fault Current Limiter — A

Look at Tomorrow, June 1995, Dig. 1995/026, pp. 5/1–5/6.[6] IEEE Recommended Practices and Requirements for Harmonic Control

in Electrical Power Systems, ANSI/IEEE Std. 519-1992.[7] Limits for Harmonics in the United Kingdom Electricity Supply System,

Engineering Recommendation G5/3, 1979.[8] M. M. R. Ahmed and G. Putrus, “Investigation into custom power tech-

nology,” in Proc. UPEC ’99, 1999, pp. 519–522.[9] M. M. R. Ahmed, “Report on development of a solid-state FCLID,”

School Eng. Technol., Univ. Northumbria, Newcastle upon Tyne, U.K.,1999.

[10] G. A. Putrus, M. M. R. Ahmed, and L. Ran, “Improving current sharingbetween parallel varistors,” in Proc. IEEE ISIE ’01, Pusan, Korea, June2001, pp. 1324–1327.

[11] J. Arrillaga, D. A. Bradley, and P. S. Bodger, Power System Har-

monics. New York: Wiley, 1985.

M. M. R. Ahmed (M’00) was born in Cairo, Egypt,in 1967. He received the B.Sc.E.E. degree fromHelowan University, Helowan, Egypt, in 1989, theM.Sc. degree in electrical engineering from CairoUniversity, Cairo, Egypt, in 1994, and the Ph.D.degree from Northumbria University, Newcastleupon Tyne, U.K., in 2002.

He was a Lecturer at the National Civil AviationTraining Institute, Cairo, Egypt, from 1990 to 1991,followed by four years as an Administrate and

Teacher at the Industrial Education College, Cairo,Egypt. From 1993 to 1996, he was with the Abha Technical College, Abha,Saudi Arabia, as a Teacher. He is currently a Lecturer with the Faculty of Industrial Education, Industrial Education College. His research areas are inpower electronics, microcomputer control, dc motor drives, power systems,and power quality.

Dr. Ahmed has reviewed papers for several IEEE conferences.

Ghanim A. Putrus was bornin Mosul, Iraq,in 1955.He received the Ph.D. degree from the University

of Manchester Institute of Science and Technology(UMIST), Manchester, U.K.

He joined Northumbria University, Newcastleupon Tyne, U.K., as a Senior Lecturer in PowerSystem Engineering in January 1995, after workingfor six years at UMIST. Since moving to Northum-bria, he has provided consultancy to severalcompanies, including Northern Electric DistributionLtd., VATECH Reyroll, and National Grid Company

(NGC). He has over 20 years of research experience in electrical powerengineering and has authored over 35 publications in journals and conferenceproceedings. His main research interests are the application of power elec-tronics in power systems, in particular, FACTS, custom power technology, andactive control of power distribution networks.

Dr. Putrus was a Member of the 1999–2000 Professional Group P7 of theInstitution of Electrical Engineers, U.K. (IEE). He is still regularly involved inIEE professional activities such as organizing lectures and refereeing papers.





Li Ran (M’98) was born in Sichuan, China, in 1963.He received the Ph.D. degree in power engineeringfrom Chongqing University, Chongqing, China, in1989.

He then became a Lecturer at Chongqing Univer-sity. Between 1992–1999, he was a Research Fellowat the Universities of Aberdeen, Aberdeen, U.K.,Nottingham, Nottingham, U.K., and Heriot-Watt,Edinburgh, U.K., where he was involved in research

on marine and offshore electrical systems, andindustrial drives. Between 1999–2003, he was aLecturer in Power Electronics at Northumbria University, Newcastle uponTyne, U.K. He joined the University of Durham, Durham, U.K., in 2003. Hispresent research interests include the control and grid integration of offshorerenewable energy systems.

Dr. Ranreceiveda StanleyGray Award—OffshoreTechnology fromthe Insti-tute of Marine Engineersin 1999for his workon the interconnection of offshoreoil platforms.

Lejun Xiao was born in Hunan, China, in 1963. Hereceived the B.Eng. and M.Eng degrees from Xi’anJiaotong University, Xi’an, China, in 1983 and 1986,respectively, and the Ph.D. degree from the Univer-sity of Bradford, Bradford, U.K., in 2000.

He was an Associate Professor at Hunan Univer-sity, Changsha, China, before joining the Universityof Strathclyde, Glasgow, U.K., as an Academic Vis-itor in 1995. Between 2000–2001, he was a Senior

Research Assistant a t Northumbria University, New-castle upon Tyne, U.K. He is currently a ResearchFellow at the University of Salford, Manchester, U.K. His main research inter-ests are in power electronics, power systems, electromagnetism, roomacoustics,and controller design and DSP implementation.

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Harmonic Analysis and Improvement of a New Solid State Fault Current Limiter