Hardware-Software Codesign 11. Thermal-Aware Design

11 - 1Swiss FederalInstitute of Technology

Computer Engineeringand Networks Laboratory

Hardware-Software Codesign

11. Thermal-Aware Design

Iuliana Bacivarov & Lothar Thiele



Contents

Why is it important to consider temperature in system design?

Power and temperature models

Thermal simulation

Thermal-aware scheduling



Power/Thermal Wall

Power/Thermal wall is recognized as the most significant barrier towards high performance



Multi-Cores Face the Power/Thermal Wall Too

[Loh: 3D-Stacked Memory Architectures for Multi-Core Processors, 2008]72-Core Intel Xeon Phi platform



Some SolutionsVLSI design and cooling solutions Thermal-aware design, materials, reduce leakage and switching, ... Use better heat sinks, fans, air cooling, liquid cooling

Thermal management Voltage/frequency scaling Stop-go execution

completely TURN OFF components to allow for cooling

Migration of tasks from hot to cool area

[MJPEG decoder on 25-core processor]

[source: Wikipedia]



But scheduling of jobs and thermal management techniques affect both timing and thermal properties

Thermal and performance objectives must be considered simultaneously during design



Some Design Questions

How can we simultaneously consider during design both timing and temperature?

What is the worst case peak temperature of the chip?

What is an optimal temperature-aware mapping scheme?

What are temperature-aware scheduling techniques with low overhead (simple control, no temperature sensors)?

Thermal and performance objectives must be considered simultaneously during design



Contents



Thermal simulation




Single Source Power Model Frequently used power model for constant voltage

Active processing Idle mode

Silicon chipSingle power source

)()()( ttTtP ψφ +⋅= iii

aaa

tTtPtTtP

tPψφψφ

+⋅=+⋅=

=)()()()({)(

, for active processing

, for idle mode

Including both dynamic and leakage power

Justleakage power

temperature

power



Power Model

- Independent of temperature- Different power consumption for

every code segment- Separate power consumption for

each component (core, cache, memory, …)

- Independent of temperature- Different power consumption for

every code segment- Separate power consumption for

each component (core, cache, memory, …)

- Independent of the load- Depends on the current temperature of

the component- Model [Skadron et al. 2004]

- For the remaining lecture: We use a linear approximation (see above).

- Independent of the load- Depends on the current temperature of

the component- Model [Skadron et al. 2004]

- For the remaining lecture: We use a linear approximation (see above).

Dynamic powerDynamic power Leakage powerLeakage power

TCLeak eTP /2~ −⋅

)()()( ttTtP ψφ +⋅= iii

aaa

tTtPtTtP

tPψφψφ

+⋅=+⋅=

=)()()()({)(

, for active processing

, for idle mode

Justleakage power

Including both dynamic and leakage power

Active processing Idle mode



Static Power / Dynamic Power Ratio



Static Power and Dynamic PowerDynamic power consumption:

Total capacity Supply voltage

Clock frequency

Between 0 and 1; quantifies switching activity

Static power consumption:- 20% or more in sub-micron era- Mostly leakage, i.e., the power dissipated by a transistor whose gate is

intended to be off



Single Power Source Model

Thermal conductance

Environment temperature

Power parameters

Silicon chip

Cooling

I ≅ P

V ≅ TCG

V0 ≅ Tamb

)()()( ttTtP ψφ +⋅=

Thermal capacity

Single power source



Solution of the Thermal EquationExplicit solution

Steady state temperature



Temperature ProfileActive state: dynamic and static (leakage) power

Temperature increase: based on linear thermal model

Task execution schedule



Temperature ProfileIdle state: static (leakage) power

Temperature decrease: based on linear thermal model




Temperature Profile

Peak temperature




Multi Source Models

Layout RC equivalent model[Barcella et. Al., U. Virginia ]

- A and B are matrixes- T is an N-dimensional temperature vector- u is the input vector



Multi Source Models – SolutionExplicit solution:

Hij(t) is the impulse response between power injected at source j and temperature variation at location i

Impulse response matrix

A, H, B, are matrixes

T is an N-dimensional temperature vector



Multi-Core Effect

tem

pera

ture

no delay

Self-heating effect

tem

pera

ture

delayed

Neighboring effect#3

tem

pera

ture

delayed

Neighboring effect#2

tem

pera

ture

delayed

Neighboring effect #1



The Impulse Response

Temperature rises with powerat same location (without delay)

Temperature rises with powerat some other location after delay



Multi-Core Effect – Heat Transfer (I)

u(t) =input vector

C = thermal capacitance matrixG =thermal conductance matrixK = thermal ground conductance matrixP = power dissipation vectorTamb = ambient temperature vectorTamb = Tamb [1, . . . , 1]’

Power dissipated by component l in ‘active’ (a) and ‘idle’ (i) processing modes

Thermal model



Multi-Core Effect – Heat Transfer (II)

closed-form solution of the temperature

= impulse response between nodes l and k

= self-impulse response



Multi-Core Effect – Heat Transfer (III)

Closed-form solution of the temperature

Temperature of node k Convolution between the impulse response Hkl and the input ul

Workload of component l



Multi-Core Effectse

lf-im

pulse

resp

onse

H k

k(τ-t)



Solving the Differential EquationsWhat’s happening in numerical simulations?

Simulators HotSpot http://lava.cs.virginia.edu/HotSpot/index.htm 3D-Ice http://esl.epfl.ch/3d-ice.html

)()()( tuBtTAdttdT ⋅+⋅= )()()(

11 −− ⋅+⋅=Δ

Δkk tuBtTA

ttT

[ ] ttuBtTAtTtT kkkk Δ⋅⋅+⋅+= −−− )()()()( 111

ambTtT =)( 0

Temperature of interest Constant time interval

With P(t) = P = const. for 0 ≤ t ≤ Δt, (and therefore u(t) = const.)

)()()( 1−−=Δ kk tTtTtT



Contents



Thermal simulation




Thermal Simulation Tool-Chain

Power / Performance Simulator


Temperature SimulatorTemperature Simulator

0 0.5 1 1.5 2 2.5300

302

304

306

Time [s]

Tem

pera

ture

[K]

Low-level power/performance simulation/emulation Software: [Benini’05], [Brooks’00]

Hardware: [Atienza’07]

Temperature simulation HotSpot: [Huang’06]

3DICE: [Sridhar’10]

There are other possibilities as well, e.g. model identification and reduction

Power modelsof HW components

Modelingof physical structure

Application



High-Level Power Simulation

Computing: Δt = 20ms, ΔP = 25mW

Reading: Δt = 45ms, ΔP = 32mW


Writing: Δt = 60ms, ΔP = 34mW


1 int fire () {2 float i = 0;3 float j = 0;4

5 read (PORT_IN, &i);6

7 j = i*i;8 j += 2;9

10 write (PORT_OUT, &j);11

12 printf(“Wrote: %f\n, j);13 return 0;14 }

How do we consider computation, communication, and memory?How do we link power consumption, time, and temperature?

How do we consider scheduling?



High-Level Power Simulation (I)

procedure FIRE(Process p)

read(INPUT, size, buf)

manipulatewrite(OUTPUT, size,

buf)

end procedure




buf)

end procedure

Process ModelProcess Model Power ConsumptionPower Consumption



High-Level Power Simulation (II)




buf)

end procedure




buf)

end procedure




High-Level Power Simulation (III)




buf)

end procedure




buf)

end procedure




High-Level Power Simulation (IV)



manipulatewrite(OUTPUT, size, buf)

end procedure



manipulatewrite(OUTPUT, size, buf)

end procedure




Thermal Evaluation

P(t) = P = const, 0 ≤ t ≤ ΔtΔt = const

Temperature of interest: T(Δt)

Calculate E, F once at the beginning

Power Annotation

Scheduling Creation

Time Tile 1 Tile 25ms

s1,p2 s1,p110ms15ms Idle20ms

s2,p2 s1,p325ms

Time Tile 1 Tile 25ms

26mW29mW10ms

15ms 5mW20ms

32mW 23mW25ms

Power ModelPower Model Thermal ModelThermal Model



Model Data

Entity Parameter [Unit] SourceCode segment Execution time [sec / iteration] Low-level sim.

Power consumption [W] Low-level sim.Communication queue

Token size [bytes / access] Functional sim.Write rate, Read rate

[1] Functional sim.

Processing unit Clock frequency [cycles / sec] Hardware data-sheet

Architecture floor-plan

Capacitance matrix [J/K] Low-level phy. sim.Conductivity matrix [W/K] Low-level phy. sim.



Calibration Tool Chain

Timing Parameters

Thermal Parameters

Execution traceTiming characterization

SoftwareSynthesisSoftwareSynthesis

Low-Level Power/Timing

Simulator

Low-Level Power/Timing

Simulator

Thermal ArchitectureAnalysis

Thermal ArchitectureAnalysis

SampleMappingsSample

Mappings

Power characterization

Thermal platform model: conductivity matrixcapacitance matrix



(High-Level) Abstract Thermal Simulation

Idle Task? Store? Restore?

ApplicationApplication Scheduling OverheadScheduling Overhead



Data for High-Level (Abstract) Thermal Simulation


Reading: Δt = 45ms, ΔP = 32mW


Writing: Δt = 60ms, ΔP = 34mW


1 int fire () {2 float i;3 float j;4

5 read (PORT_IN, &i);6

7 j = i*i;8 j += 2;9

10 write (PORT_OUT, &j);11

12 printf(“Wrote: %f\n, j);13 return 0;14 }

Thermal / Timing Parameters

Analyze hundreds of design alternatives very quickly!



Thermal Simulation Tool Chains

Black-BoxBlack-Box



Temperature Simulator

Temperature Simulator

0 0.5 1 1.5 2 2.5300

302

304

306

Time [s]

Tem

pera

ture

[K]

Power modelsof HW components

Modelingof physical structure

Application Application, Architecture, Mapping

0 0.5 1 1.5 2 2.5300

302

304

306

Time [s]

Tem

pera

ture

[K]



Contents



Thermal simulation




Multiple Power StatesPower states: trade-off between power consumption and performance

1. Mobile consumer devices 2. Server-grade hardware

Source: Dell Power Solutions, Feb. 2007

Source: Windows 7 power management

How to reduce chip temperature without sacrificing performance/timing requirements?



Thermal Control LoopReactive Speed Scaling (RSS)

Speed of processor feedback controlled based on temperatureHigher temperature ⇒ lower speedJoint analysis of temperatureand timing complex (but possible)Temperature sensor can bereplaced or extended by a loadsensor



Timely behavior is important in embedded systems, such as avionics, automotive, or media processing Tasks must finish execution within specified deadlines

Thermal wall is recognized as significant barrier to high performance High chip temperatures lead to reliability issues, even higher

power consumption, and lower performance.

System-level design solutions Use Dynamic Thermal Management (DTM) to reduce chip

temperatures, examples: speed scaling, stop-go scheduling, mapping and migration

But without sacrificing timing requirements

Summary

Documents

Hardware-Software Codesign 11. Thermal-Aware Design