Hardware Implementation of Droop

Control for Isolated AC Microgrid By:

Cristina Guzman Alben Cardenas Kodjo Agbossou

Université du Québec à Trois-Rivières

Québec-Canada

Introduction Droops control principle ADALINE estimation technique Hardware implementation of ADALINE and Droops control Co-simulation results Experimental results Conclusion

Outline

2

Smart Grid: Integration of DER privileging Renewable energy using Voltage Source Inverters (VSI)

Introduction

Power electronics interfaces

VSI

Energy storage system

VSI

VSI

3

Alternative and distributed energy source

G

WG

DC Link

Electrolyser

H2

H O

Fuel cell

PV

PCC AC Link

Voltage and frequency

control

Synchronization

Power Sharing

3

Literature propositions made around the stability of the isolated microgrids.

Techniques based on Communication control

Local control

Techniques

Combined Local control with communication

Introduction

Interfaces de puissance

VSI

VSI

VSI

PCC

Distortion currents

Line impedances

4

Droops control principle

jQPS

)cos(cos2

21

Z

V

Z

VVP

)sin(sin2

21

Z

V

Z

VVQ

sin21

Z

VVP

Z

V

Z

VVQ

221 cos

**

PPmww

**

QQnVV

21 VV

PX

121 V

QXVV

Basic representation of VSI power sharing

5

Basic representation of VSI power sharing

Droops control principle

V w

ΔV Δw

w0

n m

0 P0 Pmax P Q (W) (var) 0 –Qmax

Qmax Q0

V0

**

PPmww **

QQnVV

6

ADALINE estimation technique

)()()(ˆ kXkWky T

)()()()1( kXkeN

kWkW )(ˆ)()( kykyke

)cos(

)sin(

)cos(

)sin(

tN

tN

t

t

X

N

N

A

B

A

B

W 1

1

y(k)

Widrow-Hoff learning rule

Estimated signal

Measured signal

Estimation error

ADALINE :Adaptive Neural Network

Weight vector W

+

_

1

0 )]sin()cos([)(n

nnPCC tnBtnAAtVX pattern vector

Fourier decomposition

7

Hardware implementation of Droops

and ADALINE control

8

Voltage Control

PWM VSI

V_REF_Droops

I0

Droops Control Frequency Droop w/P

I1

V0

V1

s

kk i

p

V_REF_mod

Vdroop

fdroop

ADALINE

S&H x

Voltage Droop V/Q

P&Q calculus

- +

x - +

Imes

P

Q

VF DDS Sine wave generator

V_LD

Mn

Nn

wref

Vref

Vmes

Vmes

Vmes

Conventional V/f Droops and ADALINE based voltage control

IGBT VSI

VLD

VDC

8

Hardware implementation of Droops and

ADALINE control

9

dW

Qmes

powergui

Continuous

Wref

120 *pi

Vref

115 *sqrt(2)

Sat4

sel

d0

d1

z-1

Sat3

sel

d0

d1

z-1

Sat 2

sel

d0

d1

z-1

Sat1

sel

d0

d1

z-1

Relational 4

a

b

a<b

z-1

Relational 3

a

b

a>b

z-1

Relational 2

a

b

a<b

z-1

Relational 1

a

b

a>b

z-1

Q_estime

P_estime

N

0.0326 /2

Mult 2

a

b

(ab )z-3

Mult 1

a

b(ab )z

-3

Mult

a

b(ab )z

-3

M

0.0038 /2

Gain 3

1

Gain

1

FILTRE _8MS3

In18f7

h1ms

Out_18f 7

FILTRE _8MS2

In18f7

h1ms

Out_18f 7

E4_N

In

E3_M

In

E2_V_REF

In

E1_W_REF

In

Delay 3

z-1

Delay 2

z-1

Delay 14 z-1

Delay 13z-1

Delay 12

z-1

Delay 11

z-1

Delay 1

z-1

Delay

z-1

Convert 5

cast

Convert 4

cast

Convert 3

cast

Convert 2

cast

Convert 1

cast

Convert

cast

Constant 8

0.159149169921875

Constant 3

-8.4852294921875

Constant 2

8.4852294921875

Constant 1

-7.539794921875

Constant

7.539794921875

AddSub 1

a

ba - bz-1

AddSub

a

ba - bz

-1

System

Generator

Simulink functional blocks diagram of the

conventional Droops

System generator functional blocks

diagram of the conventional Droops

control

9

Real scenario /Simulation and experimental VSI characteristics

Hardware implementation of Droops and

ADALINE control

Description (units) VSI1 VSI2 Switching frequency (kHz) 12 12

IGBT max. current and voltage (A) (V) 16, 600 16, 600

Filter inductor (mH) 17 12

Filter capacitor (µF) 3 1

Resistive line value (mΩ) 21.8 38.6

Inductive line value (µH) 90 170

Coefficient m value 3.9035e-4 2.5466e-4

Coefficient n value 0.0066 0.0047

The inverters characteristics are similar but not identical; the inverters output filters local synchronization and control of inverters; different line impedances between VSI output and PCC; m and n are calculated as a function of the VSI powers.

10

Experimental set-up system

PC Windows Matlab/Simulink /Xilinx

User Interface

USB-JTAG Link

Xilinx FPGA XUP V2P Board xc2vp30-7ff896

Output filter

195V DC source

VSI control and

protection signals

Measurement board (ADC and isolation circuits)

LEM-LV25 LEM-LAH-50P

One VSI system

Current and voltage LEM Sensors

LOAD

11

Hardware implementation of Droops and

ADALINE control

Two VSI system Test bench

195 V DC source 195V DC source

FPGA measurement

control

FPGA measurement

control

Line emulators Line emulators

VSI 1 VSI 2

12

Two converters evaluation

Co-simulation results

0 0.1 0.2 0.3 0.4 0.5 0.659

59.5

60

60.5

61

Time(s)

Fre

quency (

Hz)

0 0.1 0.2 0.3 0.4 0.5 0.6150

155

160

165

170

Time(s)

Voltage (

V)

Droop Inv1

Estimated Inv1

Droop Inv2

Estimated Inv2

0 0.1 0.2 0.3 0.4 0.5 0.6-5

0

5

Time(s)

Curr

ent

(A)

Inverter 1

Inverter 2

0 0.1 0.2 0.3 0.4 0.5 0.6-200

-100

0

100

200

Time(s)

Voltage (

V)

Inverter 1

Inverter 2

Simulating the same characteristics physiques

Synchronization imposes of VSI is

made automatically

Negligible effects on voltage THD

The output voltage is not affected

Good power sharing

13

Test 1: one VSI experimental validation

Experimental results

Verification of the correct operation of the implemented droop/ADALINE control.

58 58.5 59 59.5 60 60.5 61 61.5 62-50

0

50

100

150

200

Time (s)

Pu

issan

ce

(W

)/ (

VA

R)

Active

Reactive

58 58.5 59 59.5 60 60.5 61 61.5 6259.6

59.7

59.8

59.9

60

60.1

60.2

Time (s)

Estim

ate

d fre

qu

en

cy

Droop

Estimated

58 58.5 59 59.5 60 60.5 61 61.5 62130

135

140

145

150

Time (s)

Pe

ak V

olta

ge

V droop

Vc estimated

Load variations Voltage

estimation is well achieved

Frequency inside the permitted

limits

14

Test 2: Two parallel VSI experimental results

Experimental results

VSI1

VSI2

Power

t1 t2 t3 t4 t5

15

Frequency

VSI2

Test 2: Two parallel VSI experimental results

Experimental results

VSI1

t1 t2 t3 t4 t5

16

Voltage

VSI2

Test 2: Two parallel VSI experimental results

Experimental results

VSI1

t1 t2 t3 t4 t5

17

Implementation cost of control algorithms for the Xilinx xc2vp30-7ff896 FPGA

Experimental results

Resource Used Available % Usage

Slices 7,122 13,696 52% 4 input LUTs 11,698 27,392 42% RAMB16s 66 136 48% MULT18X18s 76 136 55%

FPGA Slices

Used

Available

18

Real view of the Droops control / VF-ADALINE network for VSI synchronization and load sharing in a microgrid.

The FPGA implementation has permitted a real-time control and power analysis without communication between VSIs

Good steady and transient response using ADALINE based control.

Current and future works: advanced local control strategies going forward future smart microgrids.

Conclusion

19

Thank you! Question time!

Anexe

Experimental setup parameters: AC Power Source: 120VAC/60Hz. Signals sampling period: T s =10µs. FPGA clock period: T FPGA =10ns. Fundamental frequency: f 0 =60Hz ROM sine table length: 2P=215

Power electronics converter characteristics: Voltage Source Inverters: 16A, 600V IGBT full bridge (IRAMX16UP60A) DC source voltage: 195V.