Hardware Implementation of AES Encryption Algorithm Based on FPGA

Huanqing Xu1, a, Yuming Zhang2, b and Jun Yang3, c 1,2,3School of Information Science and Engineering, Yunnan university, Kunming, China

a907889351@qq.com, bzhangyuming0722@qq.com, cjunyang@ynu.edu.cn

Keywords: FPGA; AES encryption; Nios II; asymmetric encryption

Abstract: With the development of society, the information industry has attracted more and more attention by the state. Since the emergence of prism doors, it has made countries pay great attention to the direction of information security. The question about how to protect information security has become an increasingly concerned issue. This paper introduces a widely used algorithm based on FPGA of symmetric encryption algorithm AES, because its key has three kinds of length 128bit, 192bit, 256bit, which can guarantee its difficulty in the crack, so it is relatively safe, this design can include encryption path and decryption path, you can also shield the decryption path and only include the encrypted path to reduce the use of resources in order to apply to resources insufficiently when the data is encrypted. Besides, this article can also be used for the key and data transmission using 32bit bus, multi-clock transmission. Through the Jtag Uart module to achieve the computer and embedded system communication, you can use it in the IDE integrated environment to achieve the program window to debug and monitor.

1. Introduction

AES encryption and decryption has key length, anti-differential ability, which it is easy toachieve , Low cost, fast , which is to replace the traditional DES, 3DES encryption standards .On the other hand, Traditional software encryption method is to deal with slow, poor real-time , which is compared to the hardware encryption, it is easier to crack. The nios II which is processing system's peripheral configuration has great flexibility, which is depending on the user's specific needs and doing a variety of Peripherals upgrades, etc., rapid expansion, tailoring the corresponding IP CORE, thus it is ready to be a complete, powerful sopc system, not only can achieve flexible configuration, custom command, Remote hardware upgrades, etc., and the development cycle is Short, which it is not need to change the hardware layout design. Here the use of nios II processor is to achieve AES-based encryption and decryption system, AES algorithm is relative to some addition and multiplication, these addition and multiplication are defined in a specific field, which is characterized by the efficient use of hardware to achieve. The test data is used to encrypt and decrypt the system, the editor uses the random number generator to generate the key and the processed data is to increase the accuracy of the system test. The random number generator is designed by the editor according to the cellular automata theory Using FPGA independent design.

2. AES Algorithm Overview

AES algorithm includes encryption and decryption algorithm which is key expansion algorithm,because the AES algorithm is not completely symmetric, so encryption and decryption path has its own hardware. The encryption process consists of byte substitution transformations, row shift transformations, column mixed transformations, and round keys, and the resulting Nr rounds of the

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Journal of Electronics and Information Science(2017) 2: 93-97 Clausius Scientific Press, Canada

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