Hardware Design Using EDK

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Hardware Design Using EDK

EDK HW Design 2

Objectives

After completing this module, you will be able to:• Describe how to add hardware to an existing XPS project• Discuss the function of PlatGen• Utilize the integration between ISE™ and Xilinx Platform Studio

(XPS) to enhance the design flow• Utilize the Xflow in XPS• Describe the steps involved in creating a submodule with XPS and

integrating the submodule into a bigger system with ISE

EDK HW Design 3

Outline

• Adding Hardware to an Embedded System

• PlatGen• ISE: Project Navigator Integration

– Top Level– Submodule

• XPS: Xflow Integration

EDK HW Design 4

Adding IP to Design

• To add hardware in a new, empty project or to an existing project, select IP Catalog tab in XPS

• Expand group(s) of IP in the left window

• Select an IP and drag it to the System Assembly View window or double-click on the selected IP to be included into the system MHS file

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1

2

3

1

3

Embedded Design Progress(previously empty design)

Having placed the processor and peripherals, add the buses

PPC

PLBBus

PLB2OPB

PLB BRAM Cntlr

OPBBus

PLB BRAM

PLB BRAM Cntlr PLB BRAM

INTC

Timer

GPIO

GPIO

UART

MY IP

GPIO

Adding Bus(ses) and Bus Connections

Expand Bus and Bus bridge folders in IP Catalog

Select bus core and drag it to the System Assembly window

– Only bus is instantiated, connections to peripherals have not been made

Expand IP instance, click under Bus Connection column, and select a bus instance to which it needs to connect

– Similarly select memory controller and memory IPs and connect them

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3

1

3

2

1

EDK HW Design 7

Assigning Addresses

Lock addressesLock addressesAutomatically generate addresses for unlocked

components

Automatically generate addresses for unlocked

components

• Select Addresses filter

• Click on plus button to see addresses

• Click in the size column and select desired size

• Enter base address– XPS will calculate the high

address from base address and size entries

• Alternately, lock addresses for which you don’t want XPS to change address and then click Generate Addresses button

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3

1

4

12

345

5

Hardware Design Progress

Having assigned the bus connections and addresses, Connect the internal and external ports

PPC

PLBBus

PLB2OPB

PLB BRAM Cntlr

OPBBus

PLB BRAM

PLB BRAM Cntlr PLB BRAM

INTC

Timer

GPIO

GPIO

UART

MY IP

GPIO

Connecting Ports

1

2

3

4

5

Select Ports filter

Click on plus sign to see available ports

Click under the Net column and select appropriate signal

If the port is external in the design then make it external

For global ports, click on Add External Port and then assign a name

Specify net sizes6

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2 3

4

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5

Hardware Design Progress

RSTC405RESETCORERSTC405RESETSYS

C405RSTCHIPRESETREQ

RSTC405RESETCHIP

C405RSTCORERESETREQC405RSTSYSRESETREQ

PowerPC™ Processor System Reset

JTAG PPC

JTGC405TCKJTGC405TDI

JTGC405TMSJTGC405TDO

JTGC405TDOEN

JTGC405TCKJTGC405TDIJTGC405TMSJTGC405TDOJTGC405TDOEN

RSTC405RESETCORERSTC405RESETSYSCHIP_RESET_REQ

RSTC405RESETCHIP

CORE_RESET_REQSYSTEM_RESET_REQ

After the ports are connected, each device can be configured for specific functionality

Parameterize IP Instances

Double click the instance or right click on the instance and select Configure IP to list the configurable parameters

Default values are shown

Overriding values can be entered

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2

3

Default values

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2Overriding values3

EDK HW Design 12

Outline

• Adding Hardware to an Embedded System• PlatGen• ISE: Project Navigator Integration



EDK HW Design 13

Simulation Generator

Hardware Platform Generation

Library Generation

Embedded SoftwareDevelopment

ISETools

IP Library or User Repository

MSS

LibGen

.a

Compiler (GCC)

.o

Linker (GCC)

ELF

MHS

PlatGenDrivers,

MDDMPD, PAO

PCoreHDL System and

Wrapper VHDsystem.BMM

Synthesis (XST)

NGC

NGDBuildUCF

NGD

MAP

NCD, PCF

PAR

NCD

BitGensystem.BIT

BitInit

download.BIT

iMPACT

system_BD.BMM

SimGen

BehavioralVHD Model

SimGen

StructuralVHD Model

SimGen

TimingVHD Model

Simulation

IP Models ISE ModelsTestbenchStimulus

CompEDKLib CompXLib

ApplicationSource.c, .h, .s

EDK Tool Flow

download.CMD

EDK SWLibraries

Hardware Design

• After defining the system hardware and connectivity, the next step is to create hardware netlists with the Platform Generator (PlatGen)

• PlatGen inputs the following files:– Microprocessor Hardware Specification (MHS) file – Microprocessor Peripheral Definitions (MPD) file

• PlatGen constructs the embedded processor system in the form of hardware netlists (HDL and implementation netlist files)

• MHS file parameters override MPD parameters– MPD parameters are the defaults

Hardware Design Files

Microprocessor Peripheral Definitions (MPD) File

Microprocessor Hardware Specification (MHS) File

MHS overrides MPD

MPD contains all of the defaults

PlatGen

• HDL directory– system.[vhd|v] file (if top level)– system_stub.[vhd|v] file (if submodule)– peripheral_wrapper.[vhd|v] files

• Implementation directory– peripheral_wrapper.ngc files– system.ngc file– system.bmm file

• Synthesis directory– peripheral_wrapper.[prj|scr] files– system.[prj|scr] files

project_directory

hdl directory

implementation directory

PlatGen Generated Directories

synthesis directory

PlatGen Memory Generation

• Memory generation– Platform Generator generates the necessary banks of memory

and the initialization files for the block RAM block (bram_block). The block RAM block is coupled with a block RAM controller

– Current block RAM controllers include the following:• DSOCM block RAM controller (dsbram_if_cntlr)• ISOCM block RAM controller (isbram_if_cntlr)• PLB block RAM controller (plb_bram_if_cntlr)• OPB block RAM controller (opb_bram_if_cntlr)• LMB block RAM controller (lmb_bram_if_cntlr)

PlatGen Memory Sizes

• Memory sizes

• Memory must be built on 2n boundaries– Let I be the unsigned number formed by the starting address and S be the size of the

memory. If I/S is the integer, then the memory is built on the 2n boundary– 1-KB memory at $4000 is at the 2n boundary; whereas, 1 KB at $4100 is not

PLB BusOPB, LMB, OCM Buses

EDK HW Design 19

Block Memory Map

• A Block RAM Memory Map (BMM) file contains a syntactic description of how individual block RAMs constitute a contiguous logical data space

• PlatGen has the following policy for writing a BMM file:– If PORTA is connected and PORTB is not connected, the

generated BMM will be from PORTA point of reference– If PORTA is not connected and PORTB is connected, the

generated BMM will be from PORTB point of reference– If PORTA is connected and PORTB is connected, the

generated BMM will be from PORTA point of reference

EDK HW Design 20

Outline





EDK: ISE

Simulation Generator

Hardware Platform Generation

Library Generation

Embedded SoftwareDevelopment

ISETools

IP Library or User Repository

MSS

LibGen

.a

Compiler (GCC)

.o

Linker (GCC)

ELF

MHS

PlatGenDrivers,

MDDMPD, PAO

PCoreHDL System and

Wrapper VHDsystem.BMM

Synthesis (XST)

NGC

NGDBuildUCF

NGD

MAP

NCD, PCF

PAR

NCD

BitGensystem.BIT

BitInit

download.BIT

iMPACT

system_BD.BMM

SimGen

BehavioralVHD Model

SimGen

StructuralVHD Model

SimGen

TimingVHD Model

Simulation

IP Models ISE ModelsTestbenchStimulus

CompEDKLib CompXLib

ApplicationSource.c, .h, .s

download.CMD

EDK SWLibraries

EDK HW Design 22

ISEProject Navigator Integration

• The ISE/XPS flow provides integration of a processor system at two levels as a component in a FPGA design :

– The processor system is the top-level design– The processor system is a submodule

• Once the processor system is added in the ISE project, XPS can be invoked from ISE by selecting xmp file in Sources window and double-clicking Manage Processor System in the Processes window

• Add user constraint file in ISE• Implement design in ISE by selecting top-level module in Sources window and double-

clicking Implement Design in Processes window• Executable software can be merged by selecting top-level module in Sources window and

double-clicking Update Bitstream with Processor Data in Processes window– This will call XPS in background to update the bitstream and generate system.bit and download.bit files in

implementation directory as well as copy the file as system_stub.bit and system_stub_download.bit files in the ISE project directory

ISEProject Navigator Integration

• Benefits– Add additional logic to the FPGA design– Synthesize the design by utilizing ISE™-supported synthesis

tools– Control the FPGA implementation flow by using ISE

• Timing and constraints entry• Implementation tool flow control• Point tool control

– FPGA Editor tool– Constraints Editor tool– ChipScope Pro tool

Project OptionsHierarchy and Flow Tab

•Project → Project Options•Design Hierarchy

– Top level - uncheck– Submodule - check

• Top Instance• Must use ISE™ flow

•Synthesis Tool– ISE XST– Do not synthesize if third-party tools

are to be used•Implementation Tool Flow

– XPS (Xflow) - uncheck– ISE (ProjNav) - check

• Provide directory and file name in the NPL File field

Note: These settings are automatically selected when xmp file is added to the ISE project

EDK HW Design 25

Outline





EDK HW Design 26

Processor System Integration in ISE as Top Level Module

• Open ISE, create a new project or open an existing project

• In ISE, use Add Source and add an existing processor design xmp file or

• In ISE, create a new processor design using New Source and selecting Embedded Processor as a source type

• Generate instantiation template for the processor design

• Copy component declarations and instantiations of system and i/o buffers from the template

• Add user constraint file (ucf) from the XPS projects data directory

• Implement the design

EDK HW Design 27

Outline





EDK HW Design 28

Processor System as a Submodule

• Two ways to use the XPS and ISE tools to process embedded sub-module design:– Top-Down

• Invoke ISE and create a top-level project • Then create a new embedded processor source to include in the top-level

design. This automatically invokes XPS, where you develop your embedded sub-module

– Bottom-Up• Invoke XPS and develop your embedded processor design as a sub-module• Later, invoke ISE and add the embedded sub-module as a source to include in

your top-level ISE project.

• Note Only the XMP file must be added as the source file. The BMM file should not be added to the ISE project

EDK HW Design 29

Submodule: Top-Down Approach

• Open the ISE Project Navigator, and create or open an ISE project for your top-level FPGA design

• Select Project → New Source• In the New Source window, select Embedded Processor as the source type• In the File Name field, enter a name of XPS project

• A prompt appears in XPS, asking whether you wish to use the BSB

• Proceed with embedded hardware platform design development

• After returning to Project Navigator, instantiate and connect the embedded subsystem to the top-level FPGA design

– If you need to modify anything in your embedded sub-module design, you can run the Manage Processor Design process in Project Navigator to reopen XPS with the embedded project loaded

EDK HW Design 30

Submodule: Bottom-Up Approach

• Develop processor-based design in XPS• Add interacting signals between a processor system and user

logic as external ports in XPS• Open the ISE Project Navigator • Create or open an ISE project for the top-level FPGA design • Select the same Device Family for the ISE project as was

specified for the embedded sub-module in XPS• Select Project → Add Source

– This opens the Add Existing Sources window. You might or might not already have a top-level source added to your ISE project at this time

• In the Add Existing Sources dialog box, browse to and select the XPS project file (XMP) for the embedded sub-module– Make connection between the user logic and processor sub-module

EDK HW Design 31

Outline





Xflow

• Benefits:– Independent design of the processor system– One GUI for performing all design work

• Limitations:– No direct control of synthesis and implementation options– No point-tool support– The embedded system design must be the top level of the

design

Xflow

• Code/TestApp directory– <application>.c

• data directory– <system>.ucf

• etc directory– bitgen.opt– bitgen.ut– download.cmd– fast_runtime.opt– BSDL files

• pcores directory– User IP– Customized block RAM controllers

project_directory

Code/TestApp directory [optional]

data directory

etc directory

pcores

Required XPS Directory Structure

synthesis

Controlling Xflow

• A file called fast_runtime is in the etc directory• This is what it looks like:

# Options for Translator# Type "ngdbuild -h" for a detailed list of ngdbuild command line optionsProgram ngdbuild -p <partname>; # Partname to use — picked from xflow commandline-nt timestamp; # NGO File generation. Regenerate only when # source netlist is newer than existing NGO file (default)-bm <design>.bmm; # block RAM memory map file<userdesign>; # User design — pick from xflow command line<design>.ngd; # Name of NGD file. Filebase same as design filebaseEnd Program ngdbuild

EDK HW Design 35

Knowledge Check

• What are some of the advantages of using ISE™ and XPS integration?

• What are some of the advantages of using Xflow and XPS integration?

EDK HW Design 36

Answers

• What are some of the advantages of using ISE™ and XPS integration?– Add additional logic to the FPGA design– Synthesize the design by utilizing ISE-supported synthesis tools– Control the FPGA implementation flow by using ISE

• What are some of the advantages of using Xflow and XPS integration?– One GUI to perform all design work– Simple push-button flow

EDK HW Design 37

Knowledge Check

• What is the smallest memory size that PlatGen can generate for a Spartan™-IIE device?

• Why is the address 0xFFFF_B100 NOT a valid BASEADDR for a Local Memory Bus (LMB) block RAM controller?

• What will the BAUDRATE for the peripheral be:– If the MPD file has the following parameter: C_BAUDRATE = 9600– If the MHS file has the following parameter: C_BAUDRATE = 115200

EDK HW Design 38

Answers

• What is the smallest memory size that PlatGen can generate for a Spartan™-IIE device?– 2 KB

• Why is the address 0xFFFF_B100 NOT a valid BASEADDR for a Local Memory Bus (LMB) block RAM controller? – It is not on a 2n boundary

• What will the BAUDRATE for the peripheral be:– If the MPD file has the following parameter: C_BAUDRATE = 9600– If the MHS file has the following parameter: C_BAUDRATE = 115200

• The BAUDRATE will be 115200

Knowledge Check: Memory Space

• How do you build a 48-KB OPB BRAM memory space for a MicroBlaze processor in a Virtex™-II device?

? KB

? KB

0x

0x0000_0000

0x

0x

Answers:Memory Space

• How do you build a 48-KB OPB BRAM memory space for a MicroBlaze processor in a Virtex™-II device?

32 KB

16 KB

0x0000_7FFF

0x0000_0000

0x0000_8000

0x0000_BFFF

Knowledge Check: Memory Requirement

• How many block RAMs do you think will be used to build a 16-KB PLB memory space for a PowerPC processor in a Virtex-II Pro device? And why?

Answers:Memory Requirement

• How many block RAMs do you think will be used to build a 16-KB PLB memory space for a PowerPC processor in a Virtex-II Pro device? And why?– Eight block RAMs will be used– Because the PowerPC processor allows a byte write, the

memory is organized in a byte-wide mode. The Virtex-II Pro device block RAM has 18 KB; each block will be configured in 2K x 8. This will require eight block RAMs

Where Can I Learn More?

• Tool documentation– Embedded System Tools Guide Xilinx Platform

Studio

• Support Website– EDK Website: www.xilinx.com/edk

Documents

Hardware Design Using EDK