Hardware Design of a Digital Synthesizer

Hardware Design of a Digital SynthesizerAuthor(s): David ParksSource: Computer Music Journal, Vol. 7, No. 1 (Spring, 1983), pp. 44-65Published by: The MIT PressStable URL: http://www.jstor.org/stable/3679918 .

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David Parks Hewlett-Packard P.O. Box C-006 Vancouver, Washington 98668-C006

Hardware Design of a

Digital Synthesizer

Introduction

The synthesizer discussed here was designed as a means of generating time-variable spectra by evaluation of algebraic time-dependent functions. In addition to additive synthesis algorithms, many algebraic functions are known that efficiently yield such spectra. The functions themselves are often compact, and they are inherently hardware independent; accordingly, the design strives to reflect these attributes in a straightforward architecture that emphasizes hardware transparency.

Overview

Figure 1 shows the synthesizer architecture. From a system viewpoint, the synthesizer-shown within the dashed line-appears as a peripheral under control of a host computer.

The heart of the slave peripheral is a free-running circular queue that acts as a digital oscillator and synchronous controller. The queue issues real-time data and commands to a'programmable calculator that is general enough to accomplish additive synthesis, closed-form-expression, frequency modulation (FM) synthesis, and limited digital filtering. The calculator performs multiplication and division in standard adder logic by use of a logarithmic data representation; no special multiply or divide hardware is present. The host system's algebraic descriptions are targeted to the calculator. Compiler implementation at the host level is simplified by the calculator's stack architecture. The synthesizer's circular queue interfaces with the host system via a cache memory. This block allows the synthesizer to work effectively with a variety of host computer systems. The cache may be filled asynchronously at system speeds, then dumped synchronously to the high-speed circular queue.

This is the means whereby the host may achieve control of the parallel synthesizer processes.

The synthesizer's real-time capabilities are those of waveform generation, signal processing, and device control. These features may be utilized in any arbitrary fashion by the host computer. Total capability available to the host is limited by the length of the circular queue.

The rest of the article is organized into two parts: architecture and implementation. The architecture seems most accessible when discussed in terms of the circular queue. In order to utilize the queue as a fixed point of reference for what follows, a bottom- to-top development is presented, beginning with descriptions of elemental waveforms and their real- time synthesis in the circular queue. This is fol- lowed by the description of calculator architecture-the combining of elements to form complex waveforms. Finally, the scope widens to invoke a hypothetical host computer in the cache section and a hypothetical system or network in the input/ output (I/O) section. The article closes with a discussion of important implementation details and a feature summary.

Architecture: Waveform Synthesis by Evaluation of Time-Dependent Functions

Equations of Operation: The Ramp Waveform

This section will develop some of the equations of operation for sampled-time digital oscillators. The theory and terminology apply to later discussion of this design's circular queue.

A circular queue in this context means a sequentially linked list of writable locations, with the last location linked (circularly) back to the first. Sequen- tial access of the queue thus becomes a modulus counting process; one pass through the queue defines a sequence of activity that may subsequently be repeated ad infinitum. The queue can therefore be viewed as a digital oscillator.

Computer Music Journal, Vol. 7, No. 1, Spring 1983, 0148-9267/83/010044-22 $04.00/0, ? 1983 Massachusetts Institute of Technology.

44 Computer Music Journal



Fig. 1. Synthesizer architecture. The synthesizer is a real-time peripheral running under a host computer's control.

Host computer system

Cache

Circular queue

Input and output Calculator controls

Synthesized Sampled outputs inputs

The hardware of Fig. 2 is similar to that of other digital oscillators already described (Snell 1977; Buxton et al. 1978; Sasaki and Smith 1980). These designs all generate stairstep functions, which are actually sampled-data ramps, by addition of a constant to the instantaneous waveform value.

As an illustration, consider a continuous time ramp function

f(t) = mt + b. (1)

The initial (t = 0) condition is

f(0) = b, and the slope is

d/dt f(t) = m.

For any interval At, the change in f(t) is m At; a moment's contemplation of the graph of Eq. (1) will help reveal this. The same observation can also be

derived as follows. Equation (1) can be cast in difference-equation form by substituting t + At for t. Then

f(t + at) = m(t + at) + b (2)

and, subtracting Eq. (1) from Eq. (2),

f(t + At)- f(t) = m At (3)

or, in the limit as At approaches 0,

df(t) = m dt.

Finally, rewriting yields

f(t + At) = f(t) + m At. (4)

Equation (4) is the algorithm for ramp generation in the digital oscillator hardware. The equation is applied iteratively. Thus, for a sampled-time ramp, we have at various points in time

f(0) = b f(0 + At) = f(0)+ m At

f( + At) = f(-) + m at.

This iteration is really a summation process. Viewed another way, the oscillator acts like an integrator.

Af(t) = m t = m dt. (5)

0

Equation (5) is exact for both continuous and sampled time f(t) only because m is time invariant. This is because Eq. (5) is a special case of the fundamen- tal theorem of calculus,

m At = lim m(t) At = m(t)dt. (6) 0 At---> 0 0 Jo

Viewing the oscillator as an integrator can be en- lightening; Eq. (6) shows some benefits and pitfalls of this interpretation. Mainly, the quantity m must be time invariant. If this is so, then the oscillator will work for arbitrarily large At.

It is interesting to dream up specific applications for the general ramp waveform. Although the ramp itself is one candidate for synthesis, other possible

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Fig. 2. Circular queue and synthesis of time- dependent waveforms. A free-running circular queue is implemented us-

ing fast random-access memory (RAM) and a counter. A crystal oscillator (clock) establishes a stable time base. Time-

function-generator hardware synthesizes sampled data ramps. The instantaneous ramp value is over- written in the circular

queue; opcodes and increments are treated as constants and do not recirculate.

Circular queue

In

RAM RAM RAM Address Crystal 7 oscillator Address Address Address oslator

Out Out Out

Opcode

Increment Current

Time- Adder Sine function lookup generator

Recirculating data Sampled Sampled sinusoid ramp

representations include the logarithmic mapping of an exponential function, the argument of a sinusoidal function, or a segment of a piecewise envelope.

For the digital oscillator implemented as a ramp generator, it may be appropriate to extend the terminology of previous authors (phase angle increment, phase angle value). I propose to adopt a more general terminology for this article.

b is the initial condition. f(T) is the current or instantaneous value at t = 7. m At is the increment.

Exponential Waveform

An exponential function

g(t) = k R-Yt

may be represented logarithmically as

logR (k R-Wt) = -yt + logR (k),

which is a continuous function in the form of a ramp

f(t) = -m t + b.

Therefore, the sampled time process uses log, k as the initial condition and -Ayt as the increment. Note that amplitude scaling of an exponential for all positive time t thus is dependent only on the initial condition.

Synthesis of exponential waveforms must em- ploy underflow detection in the subtraction step. The ramp is clamped at its maximum negative value, which approximates an exponential con- verging to zero at time approaching infinity.

A figure of merit for an exponential waveform is




the time constant. In classic linear systems, the time constant is usually given in terms of the natural logarithm base e as

T = 1/y,

where

g(t) = Ke-'t

such that

g(T) = Ke-'.

Recalling the logarithmic representation of the exponential function, at the point in time where t = T,

f( T) = In g( T) = -1 for K = 1.

But from Eq. (5),

T

f(T) = m dt = m T. 0

Therefore, the time constant can be stated in terms of the increment and the sampling rate.

T= f(T) _ f(T) At At_ t m m At m At

This result is used in the section on implementation of the synthesizer.

Sinusoidal Waveform

A sawtooth waveform results when a ramp is generated with modulus addition. This sawtooth can represent a sinusoidal argument expressed modulo 2wr. To generate a sinusoid,

g(t) = sin (27rcot + q), note that again the argument takes the form of a ramp function. If a quarter-waveform sine lookup table of length L is employed, then L = 7r/2 and 4L = 2wr. The argument is normalized with respect to the table length; the initial condition is

(4 mod (4L) 27'

Fig. 3. Vector memory data structure. An independent list is maintained for each digital oscillator that generates a vector envelope. The list is sequential, with

a terminator bit to indicate the final entry. Note that the current word contains the final value of the current (kth) vector and the slope of the next.

Final valuekl m At, Previous

Final valuek m At,., Current

Final value ., m At,+2 Next

and the increment is 4L•At.

The addition step is performed modulo 4L; this is equivalent to stating

sin (x) = sin (x mod[2v7]). (8)

Frequency modulation is accomplished by adding a modulating (message) function M(t) to the argument (carrier):

gm(t) = sin (27rct + M[t]). (9) The 2urcot term is generated as described above, and its unmodulated instantaneous value recirculates. Therefore, the circular queue's current value can be interpreted as

f(7) = f(r) mod (4L) = (27rot)m, = mod (4L).

Then for FM the sinusoidal argument of Eq. (9) is calculated using modulus addition per Eq. (8):

x = (f[T] mod [4L] + M[T] mod [4L]) mod (4L). (10)

Piecewise Envelope

An arbitrary waveform may be constructed by link- ing piecewise "vectors" in series. The vectors are simply ramps of various slope and final value; an amplitude-versus-time plot of the waveform will show the successive, straight-line pieces linked head to tail. The waveform is described by an initial condition, a vector list, and an optional final condition (Fig. 3).

The vector list is maintained separately from digital oscillator (Eq. 4) data. To generate piecewise envelopes, the list value is compared to real-time values of f(7 + At). At the point where the generated ramp reaches the list value, the new increment (slope) is copied from the vector list to the digital oscillator.

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The vector-list pointer is then incremented to access the next list entry.

The Circular Queue and Time-Function Generator

Thus far, a general background has been sketched in terms of an idealized digital oscillator. The remaining sections will draw on that background as it applies to the actual synthesizer design. Figure 2 shows circular queue and time-function-generator hardware. This unit generates ramps by implementation of Eq. (4). Each circular queue location is composed of three fixed fields: an opcode plus the Eq. (4) increment and current value. The queue can be viewed as a recirculating shift register. Its opcode and increment fields automatically recirculate, while the current value is overlaid at each access by a new value, per Eq. (4).

The queue is free running; that is, all queue locations are accessed sequentially with no branching allowed, and each access requires an equal amount of time. Each queue location will therefore find itself being updated according to Eq. (4) at a fixed interval At = QC, where Q is the queue length and C is the minor-cycle clock period or time-slice interval. In other words, At is time invariant. Because it is a hardwired constant, At is the global pitch and duration reference for synthesized waveforms. At is also the sampling rate for synthesized waveforms, and this rate is fixed regardless of synthesis algorithm or relative level of queue activity.

Because the queue is free running, a constraint is placed on other synthesizer units: to be synchronous with the circular queue, no single hardware operation may require more time than a single queue access C. This constraint forces a pipeline implementation of synthesizer units.

Because At is the smallest packet of synthesizer real time visible to the outside world, all activity defined by a single pass through the queue is apparently simultaneous. Synchronization with the free- running circular queue thus provides the key to parallel control of the individual queue locations.

Figure 4 shows the time-function generator in its role as a vector-envelope generator. Vector lists are

Fig. 4. Piecewise envelope generator. The circular queue and time-function generator synthesize piecewise envelopes from straight-line vector seg- ments. Comparison logic activates the synchronous overlay of a new ramp slope (increment); vector- memory mapping, necessary for access of multiple

independent vector lists, is also updated at a TRUE compare. Update and overlay logic has been deleted for clarity; also, the vector-memory interface to an external controller is substantially simplified. Data paths to the circular queue are in addition to the cache data paths of Fig. 11.

Controller data

In In Vector memory RAM RAM Address (Q, K)

Address Address

out Out Map

Final value (K) Next Out slope

RAM Compare Overlay

at true Address compare

IIn In

Address (Q,K+1) RAM RAM

Out Address Address (Q) Circular

Out queue Current Increment

Time-function generator

Recirculating dataj

stored in a block of synthesizer RAM, which is shared with the host computer. Hardware is mapped to the currently active (kth) vector in the sequential list associated with the current circular queue location q. Comparator logic activates the overlay of a new vector slope; it also updates the vector-mapping hardware.

Figure 5 shows hardware for modification of the sinusoidal argument by evaluation of Eq. (10). The modulating input may be an FM term (Chowning




Fig. 5. Frequency modulation of a sinusoid. The sinusoidal argument may be modified to produce FM effects. The addition

step is carried out by an adder unit that is separate from the time-function- generator adder.

Fig. 6. Calculator. An arithmetic unit algebra- ically manipulates sinusoids, ramps, envelopes, exponentials, constants, and sampled-time inputs as directed by commands from the circular queue. Additive synthesis, FM by

evaluation of closed-form expressions, and digital filtering may all be performed at the sample rate 1/At. The complexity of calculations is limited by the number of arithmetic operations (opcodes) stored in the circular queue.

RAM

Circular Address Address

queue Out FM

Current term

Modulator Adder

Sine lookup

1973) such as

M(t) = I(t) sin (2vwot), or it may be any arbitrary function generated by the calculator hardware, a sampled real-time input, pseudorandom signal, and so on. For a pure sinusoid, the modulating function is zero. Frequency modulation inputs are selected under control of the circular queue opcode.

In the overall architectural scheme, generation of time-dependent waveforms is reserved for the circular queue and time-function generator. Other hardware units may manipulate these waveforms, but they do not alter the implicit value of the sampled real-time parameter 7.

The waveform repertoire of the circular queue is limited to ramps, vector envelopes, exponentials, and sinusoids. These waveforms constitute the time-dependent building blocks used by the calculator hardware.

The Calculator

The calculator portion of the design, shown in Fig. 6, is a programmed arithmetic unit whose control consists of a stream of data and commands issuing from the circular queue. Using the standard four

RAM RAM RAM

Address Address Address Address

ut Circular queue

Out Out

Opcode Current ,

FM

Sampled inputs

Sine Exponential, ramp,

Sinusoid , piecewise +

Input Micro control 4 - Arithmetic unit

Output

Calculator

Synthesized outputs

arithmetic functions-add, subtract, multiply, and divide-the calculator arrives at the instantaneous value of a waveform, which is a composite of numerous, independent, sampled-time elements.

Opcode sequences residing in the circular queue direct the activity of the calculator. An individual opcode is linked to the particular elemental waveform with which it is stored. For example, once the hardware structure of the calculator is defined, a sequence of opcodes can be derived for an additive synthesis function such as

f(t) = Ke-at (1 - e-t) 1 Ki (1 - e-it) sin

(21r•it) or for a frequency-modulated function expressed in closed form (Moorer 1977), such as

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Fig. 7. Stack-oriented (RPN) arithmetic unit. Data are written into register 1 (R1). At the command ENTER, a push

operation is performed. At the command OPERATE, the result is written to R1 and the stack is popped to register 2 (R2).

Arithmetic unit

R1 RI2 Stack

Data in

Command Resulting Action

DATA (DATA) --> R1 ENTER (R2) --- Top of Stack; (RI) -- R2 OPERATE (R2) OPERATOR (R1) -- R1; (Top of Stack)

-- R2

DATA/ENTER (R2) --> Top of Stack; (RI) -- R2; (DATA) -- Ri OPERATE/ENTER (R2) OPERATOR (R1) -- R2

t) (1 - a2) sin (Ot) ft) = 1 + a2 - 2a cos (Pt)

(see the section on implementation of the synthesizer for examples of opcode sequences).

The push-down stack architecture of the calculator, as shown in Fig. 7, is elegant but not original; it will be familiar to users of calculators based on Re- verse Polish Notation (RPN). The present design is novel in that it evolved, from a starting point represented by Fig. 7, with the goal of optimizing real- time performance. The first step in this process was crucial: to implement multiplication and division in standard adder circuitry by use of logarithms. This decision has advantages that will be summa- rized later.

The resulting adder-only equivalent of Fig. 7 is shown in Fig. 8. The twin adders are derived from the original arithmetic unit. The registers and stack are retained as before to emphasize the lockstep equivalence of their separate data representations. Multiplication and division steps are performed by

the upper adder, while addition and subtraction are performed by the lower adder. Each intermediate result is available to either unit. Functionally, the diagram of Fig. 8 comes very close to the actual design.

Figure 9 shows the registers and stack in a phys- ically realizable configuration. One of the stacks is redundant; that is, half the total information in the stacks will be unused. However, the redundant stack makes the right-hand data-conversion unit superfluous (either the converter or one of the stacks could be eliminated). Thus, evolution leads to the final structure of Fig. 10. Here, the conversion units are physical systems with finite delay. In effect, the arithmetic unit acts as a pipeline, with multiplication steps occurring before additions.

Table 1 compares the parent design of Fig. 7 and resultant calculator structure. (The zero-delay version is used for clarity.) The two are equivalent because they obtain identical results given identical inputs.




Fig. 8. Equivalent-data adder-only arithmetic unit. Commands and data flow are the same as for Fig. 7. However, two equivalent data types are now present. Multiplication and division operations are performed by addition and subtraction of logarithms.

Fig. 9. Redundant-stack arithmetic unit. Data converters are ideal zero-delay bidirectional units.

Fig. 10. Pipelined arithmetic unit. This is a block diagram of the calculator as implemented. It is log- ically equivalent to the

calculator of Figs. 7-9. Data converters are real units with finite delay. STO = storage; RCL = recall.

Multiply Adder Divide

Log (data)

R1 R2 Stack Data in

Data

Add Adder Subtract

Adder

Log (data)

MStack

converter converter

Al A2 Stack

Data

Adder

MM,,Stack

RCL Adder

Log Alog converter converter

Al A2 Stack

Data

Adder

C

A penalty is paid because of the calculator unit's pipeline nature. The major drawback from a computational and throughput standpoint occurs with product-of-sums calculations. An intermediate result that is an accumulated sum must waste both cycles and opcode locations in the free-running queue while feeding back through the pipelined, log data converter for multiplication. However, sum-of- products synthesis is optimally pipelined with this structure. A second, related penalty occurs with FM of sinusoids. In this case the M(t) (modulator) term must be calculated some number of cycles prior to the appearance of the sinusoid that is to be frequency modulated. The intervening cycles allow for pipelining of the M(t) term. Although these cycles may be used for independent calculations, this

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Table 1. Comparison of two calculator architectures

Redundant-Stack Design (zero delay) Original Design

COMMAND M1 M2 TOS Al A2 TOS R1 R2 TOS

(initial) x y z q r s I m n DATA A logA y z A r s A m n ENTER logA logA y A A r A A m DATA B logB logA y B A r B A m MULTIPLY log C y z C r s C m n

ENTER logC logC y C C r C C m DATA D logD logC y D C r D C m ADD logE y z E r s E m n

Note: Evaluation of E = C + D = AB + D. Variables may be instantaneous values of time-dependent functions. In the architecture of Fig. 9, at the multiply step log C = log B + log A, and C = ALOG (log C); at the add step log E = LOG (D + C). The uppercase LOG and ALOG indicate log and alog conversion of data respectively.

is a complication that must be resolved by the programmer.

Advantages of the Calculator Design

The calculator design has several advantages. It is fast: a multiply or divide takes no more time than a fixed-point add or subtract. Any arithmetic operation executes within a single clock period. This allows the circular queue to be free running at a constant rate, thereby establishing pitch and duration independently of the synthesis algorithm and opcode sequence. An additional benefit related to speed is high throughput. Pipelining of the arithmetic unit, discussed in the section on implementation, allows concatenation of multiply and add operations within a single opcode. Such concatenation frequently occurs in sum-of-products calculations. This compression increases the total number of calculation steps that can be described within the fixed length of the circular queue.

The calculator design is general. Adders are common digital hardware items, as are the read-only memories (ROMs) and multiplexers that comprise the data converters. Division is accomplished cleanly and quickly by the same hardware that executes multiplication.

Also, logarithmic (log) data have computational

advantages. It is a pseudo-floating-point representation combining wide dynamic range with high resolution near zero. For multiplication and division, however, log data may be considered as a fixed-point representation, because the binary point placement is fixed. Numerically, a multiplication operation is equivalent to a fixed-point addition. Thus, log data enjoy the best features of fixed and floating-point, at least in this small area of application. (The antilog calculator, however, must maintain equivalent precision and dynamic range; this requires large fixed-point representations to balance the log data representation.)

It should be mentioned in passing that digital filtering can be accomplished by appending a store and recall register array in parallel with register 1 (Rl). The depth of the array defines the total number of poles and zeros possible for a filter. Use of the register array for intermediate storage requires nonstack opcodes. At the host level, this constitutes a special- case hardware-dependent application.

Cache Memory Structure

Host-computer access of synthesizer functions occurs solely via the cache memory. This structure (Fig. 11) is the means of synchronous, controllable in- terfacing between the high-speed (100-nsec) synthe-




Fig. 11. Cache memory. The host computer fills cache memory with overlay data: initial conditions, increment values,

opcodes, and constants. Transfer occurs during a single sampling period, At, and is synchronous with normal synthesizer ac-

tivity. During the transfer period, synthesizer locations are selectively overlaid (selection logic has been deleted for clarity).

Nonoverlaid locations are updated with recirculating values in the usual man- ner of Fig. 2.

Cache Controller data

In In In In Controller address

RAM RAM RAM SI Address -

! Overlay Transfer 4Jcontrol enable

0 Out Out Out

Recirculating Overlay data Overlay control

Icontroller Select

In In In Select Write controls controls

RAM RAM RAM Synthesizer Addres address

Out Out Out Circular queue

Opcode Increment Current

sizer and the relatively lower speed host-computer system.

Cache is RAM from the host-system standpoint. From the synthesizer's vantage, it is a serial buffer synchronized with the circular queue. Cache memory locations map one-to-one into corresponding circular queue locations, and cache length equals circular queue length. Cache contains essentially a static image of the initial-condition (transfer-time) state of the dynamic circular queue.

Normally the cache and circular queue are de- coupled. In this mode, cache is continuously available to host-computer access. During transfer, cache and circular queue mesh, and a high-speed synchronous transfer of data ensues.

A requirement imposed by the cache architecture is that of preloading data to be transferred. To begin this process, a synthesizer event is scheduled. As the coordinating entity, the host computer will pre- calculate the necessary RPN opcodes and initial conditions, load the cache at leisure, and initiate a

transfer at the correct real-time instant. While this precalculation burden is still substantial, time lim- its fall in the millisecond range. The host system must only be fast enough to coordinate events as perceived by the listener. (Where phase relation- ships are important, the transfer can be "armed" by the host and triggered in real time at sampling-rate resolution by an internal ramp timer.)

The synchronous transfer is transparent to circular queue and calculator activity. The circular queue issues data and opcodes as usual during a transfer; recirculating data are overlaid from cache rather than from the queue or time-function generator. The overlay is selective; only those fields within words that were changed by the host computer since the last transfer are written into their corresponding circular queue destinations. Other locations and fields are unaffected by the transfer. For example, an increment can be selectively overlaid to produce a step change in the pitch of a sinusoid or to damp an exponential quickly to zero.

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Fig. 12. Synthesizer I/O. The synthesizer is a peripheral device under the control of a host computer (not shown). Simple waveform synthesis may be accomplished by the

synthesizer in conjunction with DAC ports. Addi- tional system capability can be achieved by hardware running in real time under synthesizer control.

MINIMUM SYSTEM Controller address OPTIONS

-I I Controller data I I

Shared ••Zc0

ADC Analog inputs DM moryProcess c memory

Output Synthesizer data in driver (optional)

Input Data in 0 controls4

Cache and Circular Calculator • DM vector DMu Output

, Oupcontrols Data out

Digital Synthesizer data out synthesizer

DAC Analog outputs

Transfers occur during a single pass through the circular queue; therefore, changes precipitated by the transfer are essentially instantaneous. Synchro- nization with the circular queue provides a means for control of the independent queue locations, which apparently operate as parallel processes. In this way, all parameters of a complex waveform may be updated simultaneously and without glitches. Perhaps these features of the cache architecture are a step toward resolving controllability and real-time scheduling problems encountered with other designs (Loy 1981; Moorer 1981).

Input/Output Operation

So far, the synthesizer has been described primarily as a waveform generator. In this mode, circular queue opcodes control the action of the calculator. The opcode may alternatively be directed toward external devices, however. If only one reference to a particular device is present in the queue, that de-

vice will be accessed at the sampling rate 1/At within a single-time slice C.

In general, external devices are expected to be fast, special-purpose, and memory-intensive in operation. Addressing of device data is not allowed. By implication, data are read or written serially from or to a first-in, first-out (FIFO) structure. Examples of external devices are direct memory access (DMA) and digital reverberation units. The "no- addressing" constraint does not preclude output data being treated purely as an address. Examples of this include waveshaping synthesis units or table lookups. Finally, I/O may interact synchronously with real-time processes. Examples of synchronous I/O include analog-to-digital and digital-to-analog converter (ADC and DAC) and channels, or even other synthesizer units.

Most external devices will be initialized by the host computer. Real-time control may then pass to the synthesizer at the instant of a cache transfer.

In this design, input may be concurrent with output, and both may be merged with time-function-




Fig. 13. Synthesizer data representations. Time- dependent calculator inputs are derived from the circular queue, current- value field. Once a nu-

meric value is present in the calculator, it may be "interconverted" between equivalent log and alog representations.

Sinusoidal Lookup argument Quadrant Arg L

. 2 10

Opcode Increment [

Current 9 18 27

Log data word ----S Char Mantissa < Log/Alog 1 4 11

conversion

Alog data word ---S Fixed-point binary

1 26

generator and calculator activity. This sort of compression is only a ruse for conservation of circular queue locations.

Figure 12 shows a possible configuration of pe- ripherals under synthesizer control. Such a scheme is similar to the highway previously described by Cody (1982). No such system has yet been implemented with this particular synthesizer, but it is possible to speculate about this and numerous variations.

Implementation of the Synthesizer

The purpose of this section is to fill in certain gaps in the preceding discussion of architecture. The in- tent is not to dwell on the minutiae of digital design. In the design of the circular queue, say, a great deal of complicated timing and control detail is necessary to ensure congruent operation of normal data recirculation, cache transfer, vector overlay, and vector overlay during transfer. We shall not deal with such wearisome complexities here.

Many possible implementation paths exist for a given architecture. Some would argue that this constitutes the charter for engineering creativity. This particular implementation is no paradigm; it is merely an illustration.

Data Representations

Figure 13 shows the internal synthesizer word as- signments. The circular queue word is composed of read-only opcode and increment fields and a read/ write current-value field. The remaining Fig. 13 words derive from the circular queue, current-value field. The alog data word and the log data word both represent the same numerical quantity. These equivalent representations can be converted by calculator hardware.

Two opcode subfields are shown in Fig. 14. Wave- form manipulation is directed by the calculator- control field. The data-type field divides the synthesizer operation into the two major modes of signal generator and controller (special and extended hardware opcodes). Controller operations were discussed in the section on I/O operation.

The Circular Queue and Cache

Static RAM and a counter are used in the circular queue implementation. This structure emulates a recirculating shift register (a fast, two-port register about 256-by-9 is an ideal piece of hardware in this application). Cache is best implemented as RAM for general access by the host computer.

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Fig. 14. Circular queue opcode fields. The data-type truth table is a function of bits 9, 8, and 7. Possible identifications of the current-value data are modulated and nonmodu- lated sinusoids, exponential, vector, and ramp/

constant. Controller functions also encoded in the data-type field are "special hardware," "extended hardware," and a reserved (unused) encoding. The calculator-control field is defined only for the non- hardware data types.

Fig. 15. Current-value pipelining. D flip-flop registers in this and other di- agrams indicate levels of pipeline delay This hardware implements the timing of Fig. 16. Data path FTAU is the current value.

Subscripts indicate the pipelining level (number of minor cycles delay with respect to the minor cycle in which the opcode is originally accessed). MPX = multiplexer; WR = write.

987654321

S ! I Opcode

Reserved

Calculator control

Data type

The circular queue is time-multiplexed, read N/write M, within the minor-cycle period C. This is only one way of emulating a two-port data path; two parallel memory blocks could be interleaved instead. Figure 15 shows four levels of delay (pipelining) in calculation of the recirculating instantaneous value; therefore, N = (M = 3) mod(Q), where Q is the queue length.

Figure 16 illustrates memory timing. A current value is read from location N. Three minor cycles later, the new value is written to N.

The Time-Function Generator

The time-function-generator hardware consists of a floating-to-fixed-point converter and an adder. It is responsible for synthesis of sinusoids, ramps and vectors, and exponentials, each of which differs slightly in implementation detail. Quantitative fig- ures of merit for these waveforms are related to the circular queue word lengths and the synthesizer sampling rate. The use of the same hardware for all types involved some trade-offs.

The increment (Fig. 17) is a floating-point quantity; therefore, its precision is a percentage rather than an absolute value. For sinusoids, the floating- point converter adds a most significant one during normalization. This yields a 15-bit quantity with a frequency precision of 0.00305%, best case. (Preci- sion is less at low frequencies because of the finite length of the current-value field, which forces truncation of the normalized-increment least significant bits.)

FTAU3

D MPX

FTAU4 NDin Din

M Address---- Address---- P

Dout NDout

FTAUo L3 D

FTAU1 Floating to fixed point

D Q Q

Read FTAU2 address

Write Adder address

Exponential and ramp increments explicitly sup- ply their own most significant one, allowing an extended low-end range. The resulting best-case ramp precision is therefore 0.0061%.

The dynamic range of the increment may be derived from Fig. 17. This increment is normalized with respect to the current-value register's binary point. This normalization is reflected in the relative values of M and N in Fig. 17. Normalized-increment values lie in the ranges

2-N+I > m At > 2-N ; 15 > N > 1 for sine 2-M+l > m Atzero ; 23 >M 5for exp 2-NL > m At zero ; 27 > N > 9 for ramp

The minimum sinusoidal increment is 2-15. The minimum frequency is therefore




Fig. 16. Circular queue memory cycle timing. Memory is time-division- multiplexed read/written at twice the minor-cycle rate. Underflow/overflow

detection "clamps" a current value by inhibiting the write control. C = minor-cycle period; RD = read; WR = write.

Fig. 17. Normalization of the circular queue increment. A hardware unit in the time-function generator converts the floating- point increment into a normalized fixed-point representation. For sinusoids only, the converter appends a most significant one. The increment as il-

lustrated lies in the range 2-"4 < increment < 2-1"

with respect to the sinusoidal current-value register. The increment is shown shifted one bit position to the right of the maximum. Its least significant bit is truncated due to current- value register limitations.

C Circular 7RD WR RD WR RD WR RD WR queue adr

At ACC

FTAUo FTAU4j

FTAU

.FTAU3 FTAU2

-H -t ADD Overflow Underflow

. Nwrite FTAU

Fig. 17

Binary point

Sinusoid and ramp current-value register

N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

0 01 Normalized increment

M 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Log exponential current-value register

Binary point

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Fig. 18. Calculator registers and data paths. Data flow through this unit is illustrated in Fig. 19. All data

paths are multiplexed; or- tied input busses are shown for clarity only. MPY = multiply.

Log Log,

Lo ,M PY/M 1

4

4 0STO O = Pipeline level

RCL Log, LogRCLI Log

RMCL

.MPY 7

M1

D AlogAlog Q M1 MP DQ Add

MPY o - Al D

Log4 POP... POP M

M2 D I

Add A

Push A2

POP

PTush 9 POP

Add < D

Add < -----------

•Q

27r radians 1 increment 215 increments 25.6

/sec 2rr radians

0.84 sec 1.19 Hz. 0.84 sec

Full frequency coverage is provided up to the sampling rate of the synthesizer. Note that frequency precision for the case above is only 13 bits or 0.0122% due to truncation.

For ramps, the minimum nonzero increment is 2-27. The resulting ramp duration is

25.6 /tsec 227 increments

increment ramp

This is a relatively useless case, however, because precision is only 50%; the next available ramp duration is one-half of this, or 1717 sec. The precision

of the ramp varies inversely with duration by multi- ples of 2 up to the best-case value of 0.0061%. This occurs at m At > 2-14 with a duration of 0.42 sec.

For exponentials, the appropriate figure of merit is the time constant T. Since the circular queue uses log2 data, the following logarithmic relation- ships are useful for conversion of base e to base 2.

log, U In=

nu In u log2u ln 2

2u = e(n 2)u

To apply Eq. (7), correction must be made for the change to base 2. Thus, for an exponential waveform g(t) = e-vt, the equivalent waveform represented, radix two is g'(t) = 2-'"y/2)t. At the time constant t = T = 1/y, the current-value register




Table 2. Calculator Opcodes

Opcode Virtual Results

ENTER (DATA) -> R1 PUSH R2

(RI) -- R2

* MPY (DATA) --> R1

(R1)*(R2) -- R1 POP R2

+ ADD (DATA) --> RI (R1)+(R2) --> R1 POP R2

*. MPY ENTER (DATA) --> Ri

(R1)*(R2) --> R2

+. ADD ENTER (DATA) --> R1 (R1)+(R2) --> R2

?+ MPY ADD (DATA) --> Ri

(R1)*(R2) --> Ri POP R2

(R1)+(R2) -- R1 POP R2

*+. MPY ADD ENTER (DATA) --> R1 (R1)*(R2) --> R1 POP R2

(R1)+(R2) --> R2

Note: For the five major opcode classes, resulting calculator activity is shown in terms of the simplest calculator structure (Fig. 7). A total of 17 opcodes is defined; divide may be substituted for multiply, subtract may be substituted for add. Setting R1 equivalent to M1/Al, and R2 equivalent to M2/A2, this table may be used to derive a pipelined version as in Fig. 19.

contains f(T) = log2 g'(T) = -1 /In 2. As an example, suppose that m At = -2-1". Thus, the time constant, by Eq. (7), is

At 25.6 psec m = t f(T) = 2-1 In 2 =0.076 sec.

The Calculator

Figure 18 shows the redundant stack calculator as it is implemented. Extra data paths have been added to aid in compressing opcode sequences (that is, to reduce the number of discrete circular queue locations required for common arithmetic operations).

The principal challenge represented by the calculator was implementation of the necessary pipelining. Table 2 lists waveform generating opcodes. Figure 19 shows sequential activity for the major opcode classes by pipeline level within the calculator. (Pipeline level means the number of minor-cycle delays with respect to the minor cycle in which the opcode was originally issued.) The rule for derivation of Fig. 19 is simple: data in the register pairs Mi/Al M2/A2 are kept equivalent, allowing for pipelining.

To visualize calculator response to a series of opcodes, the Fig. 19 entries may be arranged as in Fig. 20. This example shows calculation of E = A + BCD. The opcode sequence as illustrated is as

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Fig. 19. Calculator pipeline chart. The sequence of activity set off by an opcode may be traced through each pipeline level. Time

increases to the right in discrete steps (minor cycles). Blank time at levels 6 and 9 allows pipelining of the ALOG and LOG

converters. Operations such as (Ml)*(M2) occur during the interval shown. Transfers such as (Ml) -- ALOG or PUSH M2 are

scheduled in the interval and occur at the instant of transition into the next interval.

<Ml> -+ ALOG;

<DATA>. <DATA> - Ml; PUSH M2; <ALOG> - Al; PUSH A2;

<Ml> + M2; <Al> - A2;

<0l> x <t12>

<DATA>* <DATA> - Ml; + Ml1 - ALOG; <ALOG> Al; POP A2

POP M2;

<DATA>*. <DATA> - Ml; <Ml> x <M2> <ALOG> Al; <Al> + A2; + M2 + ALOG;

<Al> + <A2>

<DATA>+ <DATA> Ml; <Ml> + ALOG; <ALOG> 4 Al; + Al - LOG; <LOG> + M1;

POP M2; POP A2;

<DATA>+. <DATA> + Ml; <Ml> + ALOG; <ALOG> + Al; <Al> + <A2> <LOG> + M2;

+ A2 + LOG;

<Ml> x <M2> <Al> + <A2>

<DATA>*+ <DATA> Ml; -+ ALOG; <ALOG> - Al; - Al LOG; <LOG> + Ml;

POP2 M2; POP A2; POP A2;

<Ml> x <M2>

<DATA>*+. <DATA> -M Ml; 4 ALOG; <ALOG> ?

Al; <Al> + <A2> <LOG> + M2;

POP M2; POP A2; A A2 > LOG;

follows:

A ENTER B ENTER C MPY ENTER D MPY ADD

Since the variables may represent instantaneous values of synthesized waveforms, one of many possible interpretations of the result is

E(t) = Kaat + Kbe-Pt (sin [wot]) (sin [oDIt + 0D).

For this interpretation, cache would contain the the data in Table 3. Additionally, the variable D opcode might possibly be a special hardware command; as such it could incorporate

OUTPUT to DAC Channel E

with the synthesis and control activity.

This particular example was chosen to point out a subtle problem of the equivalent data architecture: conflicting data transfers at register A2 and the adding unit stack. This problem can be side- stepped by observing that conflicts arise when data are forwarded to the adding unit without regard to their eventual role as an addition or subtraction operand. If data are conditionally forwarded only at an addition or subtraction reference, the scheduling problems do not arise.

The forwarding rule is complex. It involves in- struction "lookahead" to enable Al, A2, and adding stack transfers conditionally. The forwarding rule also eliminates level 7 POP A2 activity. Figure 19 entries are accordingly modified by this rule.

Calculator inputs (Fig. 21) are selected under control of the circular queue opcode, specifically the "data" field. Notice that all inputs occur at the highest possible pipeline level; this includes data from the adding unit via the LOG converter. A sec-




Fig. 20. Example opcode sequence. Pipeline-chart entries are staggered to il- lustrate simultaneous ac- tivities throughout the pipelined calculator levels.

This example illustrates the scheduling problem that arises from uncondi- tional forwarding of data to the adding unit.

<Ml> A

ALOG; <DATA>. <DATA> M 1; PUSH M2; <ALOG> + Al; PUSH A2;

<Ml> + M2; <Al> -+ A2;

<Ml> - ALOG;

<DATA>. <DATA> -+ M; PUSH M2; <ALOG> - Al; PUSH A2;

<Ml> + M2; <Al> + A2;

<DATA>*. <DATA> -+ Ml; <Ml> x <M2> <ALOG> + Al; <Al> 4 A2; SM2 - ALOG;

<Ml> x <M2> <Al> + <A2> <DATA>*+ <DATA> - Ml; I ALOG; <ALOG> + Al; + Al -+ LOG; <LOG> HMt;

POP2 M2; POP A2; POP A2;

f

Table 3.

Variable Data Type Control Increment Initial Condition

A Ramp ENTER KaAt 0

B Exp ENTER -()3/ln[2])At logKb

C Sine MPY ENTER wcAt 0

D Sine MPY ADD oDLAt (4L/274r)oDmod(4L)

ond rule is therefore applied to Fig. 19 sequences: (LOG) -- M1 transfer must be explicitly enabled by an opcode at the proper time-slice. An opcode sequence illustrating feedback via the LOG converter is shown in Fig. 22. The unused minor cycles will be wasted unless they are intelligently interleaved with independent calculations. (This complication was mentioned earlier.)

Certain "clever" tricks are possible given the data paths shown. These do not necessarily involve hardware dependencies; rather, they can be legitimate ways of compressing opcode sequences into single commands. For example, extra data paths allow calculation of at 2-t with a single opcode in a single time-slice. The ramp at is applied to register Ml; by convention it is taken as representing log(2-at). LOG(at) arrives simultaneously at M2. The sum M1 + M2 therefore represents log,(at(2-at)).

LOG/ALOG Conversion

For the purposes of multiplication and division, base two logarithms are used. Numbers in registers M1/M2 are of the form CHARACTERISTIC. MAN- TISSA; therefore, the number L represents the quantity X, where

X = 2 = 21og2X = 2-CHARACTERISTIC.MANTISSA

Since the sign of the logarithm is negative by convention, numbers greater than 1 may not be represented. The sign of the number L corresponds to the sign of X, not to that of log X.

The log, value (see Fig. 13) lies in the range 0.0 through -15.99. Its binary point placement is fixed. Equivalent dynamic range and precision are maintained by the fixed-point binary word. Since the log characteristic defines a 0- through 15-bit range to

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Fig. 21. Calculator data- input pipelining. Input from external devices is not available until level 3; accordingly, all internal data paths are delayed un-

til they are synchronous with input data. Feedback from the adding unit to the LOG converter occurs at level 3.

Opcode,

D

I/O

Decoded tdecode input 0 controls

External input L taccess

control2

e

Input0 data

Internal input,

FTAU, Input3 FTAU3 Raud Add9 FTAU3

MPX ~Select3

Shift Adder

FM

D D D Q E :Q Q1 Q

Log Log sine MPY encode RCL

Sine Log EXP

Select4




Fig. 22. LOG feedback example. Explicit enabling of (LOG) --- M2 is required at the highest pipeline level. Note the five wasted opcode time-slices.

<Ml> - ALOG; <DATA>. <DATA> + M1; PUSH M2; <ALOG> - Al; PUSH A2;

<Ml> + M2; <Al> -o A2;

<DATA>+. <DATA> - Ml; <MM> l ALOG; <ALOG> -, Al; <Al> + <A2> <LOG> M2; 1 A2 + LOG;

<DATA>*. <DATA> - M1; <Ml> x <M2>

SHM2 + ALOG;

which the 11-bit mantissa is appended, 26 bits of precision are required for the alog word.

The ALOG conversion algorithm for changing log data into fixed-point representation is

1. Take the antilog of the mantissa by means of table lookup.

2. Append a most significant one to the table value.

3. Shift to the right the antilog value C bits where C is the characteristic; fill in zeros to the left.

4. Transmit the sign of the log representation to the alog fixed-point sign bit.

5. Encode the 26-bit fixed-point value in a ones-complement representation.

Conversion can be represented symbolically by the equation

2 -CHARACTERISTIC.MANTISSA = 2 -CHARACTERISTIC 2 -0.MANTISSA

In hardware terms, the mantissa conversion is a table-lookup operation, while the multiplication by an integer power-of-two is simply a shift of the table result. Note that for a nonzero mantissa, the quantity 2-0.MANTISSA represents a value in the range 1 > value > 0.5. In binary representation, this value always has a most significant one imme- diately to the right of the binary point; that is,

1 > 2-0.001 -0.1111 ... 1 0.5 >

2-0.999 - 0.1000 . . . 12.

Thus, the characteristic can be said to locate the most significant one of the fixed-point binary values. This one need not occupy table-lookup space.

The shift/most-significant-one algorithm is im- precise for the singular case of mantissa equal to

zero. In this case, an approximation is used. For example,

2-10 = 0.100 .. 02 -2-1.0001 = 0.011 ... 12;

that is, 2-1?0 is converted to its approximate equivalent value of 0.011 ... 12.

LOG conversion is the inverse case. The algorithm is

1. Decode the ones-complement data. 2. Find the bit position of the most significant

one in the fixed-point word. This position value is the log characteristic.

3. Shift the fixed-point word to the left until the most significant one is shifted out (shift to the left characteristic + 1 bits).

4. Encode in the log representation the shifted quantity by means of table lookup. This value is the mantissa.

5. Transmit the sign of the original fixed- point representation along with the mantissa and characteristic.

6. Round up values less than 2-16 to the minimum (all ones) log value.

Input/Output and Hardware-Specific Opcode

Hardware-specific opcodes are used to augment the standard signal-generation and RPN-calculation opcode set. At the hardware-independent end of the spectrum, such opcodes are required for sequence compression (a single opcode for at 2-"t, for example). In the gray area of hardware dependence are the I/O control codes, store/recall commands and LOG feedback commands specific to each channel. Finally, synthesizer-dependent codes enable the

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Table 4. Implementation summary

Technology of implementation TTL 74S where speed critical, 74LS otherwise 82S09 64-by-9 RAM for circular queue and cache, upgradable to 82S212 256-by-9 RAM (no change of

sample rate) Bipolar PROM for table lookup (60 nsec maximum)

Timing data Minor-cycle time 100 nsec Read/modify/write memory-cycle time 100 nsec maximum Multiply or divide time 100 nsec I/O-device response time 75 nsec maximum Sampling rate 25.6 1/sec

Waveform characteristics at 25.6-lpsec sampling rate Sinusoid

Frequency range 1.19 Hz- 19.5 KHz Frequency precision 0.00305% above 4.77 Hz

Ramp Duration range 3435 sec-6.55 msec Duration precision Better than 1% below 35 sec

Exponential Time-constant range 309 sec-0.59 msec Time-constant precision Better than 1% below 3.1 sec

Capabilities for a circular queue length of 64 Independent, synthesized waveforms Up to 64 Arithmetic operations on synthesized Up to 64 multiplications or divisions plus

or sampled data 64 additions or subtractions I/O operations Up to 64

user to define explicitly the state of each internal microcontrol line.,

Hardware-specific opcodes are of two types, special and extended. Special codes use the calculator- control opcode field as an index into predefined microcontrol states. The current value field remains read/write; therefore, waveform generation can be merged with I/O or other device-dependent activi- ties. The drawback here is the limited number of available codes. For example, complete generality of I/O channel access is not possible because there are more I/O permutations than special opcodes. Ex- tended hardware opcodes provide generality by sac- rificing concurrent waveform generation. Here the current value field is read only. Each of the 51 available circular queue bits corresponds to the state of a unique, synthesizer control signal. This allows complete generality in routing of data and inter-

mediate results, subject only to limitations of the hardware implementation. (For example, or-tied data paths may have only one source enabled, or not every intermediate result may be available on every data path.) Such generality is also useful for hardware debugging and checkout.

Acknowledgments

My thanks to Jon Garman for many interesting dis- cussions concerning the synthesizer design. Jon originally proposed the use of a logarithmic data representation. J. R. Hill, Jim Burrus, John Rhodes, and many others contributed helpful criticisms. David Seamans, William Brandt, and Carl Hovey were all crucial early instigators. And thanks to Joyce for her encouragement and support.




References

Buxton, W. et al. 1978. "An Introduction to the SSSP Digital Synthesizer." Computer Music Journal 2(4): 28-38.

Chowning, J. 1973. "The Synthesis of Complex Audio Spectra by Means of Frequency Modulation." Journal of the Audio Engineering Society 21(7):524-536. (Re- printed in Computer Music Journal 1[2]:46-54, 1977.)

Cody, D. W. 1982. "The RTM5 Signal Processing Archi- tecture." Computer Music Journal 6(2): 52-60.

Loy, D. G. 1981. "Notes on the Implementation of MUS- BOX: A Compiler for the Systems Concepts Digital Synthesizer." Computer Music Journal 5(1):39.

Moorer, J. A. 1977. "Signal Processing Aspects of Com- puter Music-A Survey." Computer Music Journal 1(1) :20-22.

Moorer, J. A. 1981. "Synthesizers I Have Known and Loved." Computer Music Journal 5(1):4-12.

Sasaki, L., and K. C. Smith. 1980. "A Simple Data Reduc- tion Scheme for Additive Synthesis." Computer Music Journal 4(1): 22-24.

Snell, J. 1977. "Design of a Digital Oscillator Which Will Generate up to 256 Low Distortion Sine Waves in Real Time." Computer Music Journal 1(2): 4-25.

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Hardware Design of a Digital Synthesizer