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Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities and architectural bodies behavioral, structural, and dataflow views examples. - PowerPoint PPT Presentation
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Hardware description languages: introduction
• intellectual property (IP)
• introduction to VHDL and Verilog
• entities and architectural bodies
• behavioral, structural, and dataflow views
• examples
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hardware description languages (HDL's): HDL is a language to describe hardware, just like it says; typically a HDL tries to use programming-language-type syntax and constructs to describe hardware, allowing the user to avoid the use of schematics
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Some things HDL's must deal with:
parallel activity (e.g., in a half adder, both the XOR and AND gates receive inputs simultaneously)
vector inputs (e.g., in an 8-bit adder, the inputs are each 8 bits and the output is 9 bits)
timing--both sequential and combinational logic (e.g., in a register the interaction between the clock input and the state changes must be described)
levels of abstraction
ideally will support both analysis and synthesis for hardware components/systems
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intellectual property (IP): HDL's are an effective way to describe components in which the internal workings ("intellectual property") are proprietary but the interface to other components must be public
"popular" HDL's: VHDL, VerilogBoth have “AMS” (Analog and Mixed Signal) extensions
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Two main HDLs: VHDL / Verilog
VHDL--Very High Speed Integrated Circuit (VHSIC) Hardware Description LanguageStandards--IEEE 1076-1987;1076-1993; Ada-like languageAdditions--VHDL-AMS--Analog & Mixed Signal
Verilog—1985; proprietary to Cadence until 1990 (“open Verilog”)C-like languageAdditions—Verilog-AMS—Analog & Mixed Signal
NOTE: this course is NOT designed to make you a VHDL or Verilog expert! The Altera tools (as well as other synthesis tools) work best with simpler HDL constructs (e.g., structural representations, modest levels of nesting)
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VHDL and Verilog:
Behavioral, Structural, and “Dataflow" views supported
Physical views generally not supported--descriptions do not encompass the low-level physical details of a design--in particular descriptions can be "technology independent"; this supports REUSABILITY--for simulation, may add details of a particular technology[this quarter—HDL designs are tied to the specific technology of the chosen Altera device]
Both languages allow for “testbenches” to aid simulaton(altera does not support the testbench concept; best-supported simulation is through graphical waveforms)
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what can HDLs be used for?
design entry
simulation ("analysis"): simulators are examples of "discrete event simulators"
E1 E11 E2 E12 E22 E3 E4 E111 E41
synthesis: HDL description can be turned into a circuit layout by powerful "silicon compilers"
time
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ex: half-adder
a
s
b
c
Inputs: a,b--"bits"
Outputs: s,c--"bits"
"boxes" sum and carry work concurrently to perform a transformation. Within each there is a delay which depends on the physical implementation chosen.
"sum"
"carry"
"higher level of abstraction":
a s
b c
"combining modules":
a s
b c a1 s1
b1 c1
"connecting signal"
"half adder"
(h.a.)
h.a.h.a.
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VHDL
*entity—interface to the outside world
*architectural body—functionality
*one entity can be paired with several architectural bodies, for example a structural body and a behavioral body
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VHDL example:
entity: a sum
b carry
entity half_adder is
port (a,b,: in std_logic; --alternative type "bit"
sum,carry: out std_logic);
end half_adder;
"half adder"
(h.a.)
Note: keywords, comment, “entity” syntax
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type: "std_logic" –used for VHDL and Verilog in Altera
0:forcing 0; 1: forcing 1; -:don't care;
(U:unitialized;x:forcing unknown;z:high imped.
W:weak unknown;L:weak 0;H:weak 1)
requires (in Altera):
LIBRARY IEEE;
USE IEEE STD_LOGIC_1164.ALL;
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"architecture": what's inside
some sample VHDL architectures: architecture concurrent_behavior of half_adder is
--this is a behavioral description ("delay" = 5 ns here)
--it does NOT imply that XOR or AND gates will be used
-- in the implementation
begin
sum <= (a xor b) after 5 ns;
carry <= (a and b) after 5 ns;
end concurrent_behavior;
architecture structural of half_adder is
--this is a structural description
component XOR
port (X1,X2: in std_logic; O: out std_logic);
end component;
component AND
port (X1,X2: in std_logic; O: out std_logic);
end component;
begin
G1: XOR
port map (A,B,SUM);
G2: AND
port map (A,B,CARRY);
end structural;
a b
sum
carry
???
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another example: "process" models:
architecture behavior of half_adder isbeginsum_proc: process(a,b)
begin if (a = b) then
sum <= '0' after 5 ns; else
sum <= (a or b) after 5 ns; end if;end process sum_proc;
carry_proc: process (a,b)begin
case a iswhen '0' =>
carry <= a after 5 ns;when '1' =>
carry <= b after 5 ns;when others =>
carry <= 'X' after 5 ns;end case;
end process carry_proc;end behavior;
a b
sum
carry
???
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entity full_adder is
port(in1,in2,c_in: in std_logic;
sum,c_out: out std_logic);
end full_adder;
architecture dataflow of full_adder is
signal s1,s2,s3: std_logic;
constant gate_delay: Time := 5 ns;
begin
L1: s1 <= (in1 xor in2) after gate_delay;
L2: s2 <= (c_in and s1) after gate_delay;
L3: s3 <= (in1 and in2) after gate_delay);
L4: sum <= (s1 xor c_in) after gate_delay;
L5: c_out <= (s2 or s3) after gate_delay;
end dataflow;
Full adder example:
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using two half addersfor a full adder:
architecture behavioral of full_adder issignal s1,s2,s3: std_logic;constant delay :Time:= 5 ns;
begin
HA1: process(in1,in2)--first half adderbegins1 <= (in1 xor in2) after delay;s3 <= (in1 and in2) after delay;end process HA1;
HA2: process(s1,c_in)--second half adderbeginsum <= (s1 xor c_in) after delay;s2 <= (s1 and c_in) after delay;end process HA2;
OR1: process(s2,s3) --compute carry-outbeginc_out <= (s2 or s3) after delay;end process OR1;
end behavioral;
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example: multiplexor ENTITY my_mux IS
PORT (sel: IN BIT_VECTOR (0 TO 1);
a,b,c,d: IN BIT_VECTOR (0 TO 3);
y: OUT BIT_VECTOR (0 TO 3);
END my_mux;
ARCHITECTURE mux1 OF my_mux IS
BEGIN
y <= a WHEN sel="00" ELSE
b WHEN sel="01" ELSE
c WHEN sel ="10" ELSE
d WHEN OTHERS;
END mux1;
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Some sequential logic examples:
--flip-flop:
--DFF (positive edge triggered,
--asynchronous --reset and enable):
entity DFF isport (D, clock, reset, enable:in std_logic; Q1: out std_logic);
end DFF;
architecture behavior of DFF is begin
process (reset, clock)begin if reset = '1' then
Q1 <= '0'; elseif (clock 'event and clock='1') then
if enable='1' thenQ1 <= D;
end if; end if;
end process;end behavior;
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example of state machine:
reset 1X X0
X1
0X
output: 1 from state B, 0 from A and C
entity st_mach is
port (clock, reset, in1, in2:in std_logic;
out1: out std_logic);
end st_mach;
B
CA
architecture A of st_mach istype state_type is (state_a,state_b,state_c);signal state: state_type;
beginprocess (reset, clock)
begin if reset = '1' then
state <= state_a; elseif (clock 'event and clock='1') then
case state iswhen state_a =>
if in1='0' thenstate <= state_b;
elsestate <= state_c;
end if;when state_b =>
state <= state_c;when state_c =>
if in2 ='1' thenstate <= state_a;
end if;when others =>
state <= state_a; end case;
end if;end process;
with state selectout1 <= '0' when state_a;
'1' when state_b;'0' when state_c;
end A;
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an example of a counter (Ashenden):
library ieee;
use ieee.std_logic_1164.all; entity count2 is generic (prop_delay : Time := 10 ns); port (clock : in bit; q1, q0 : out bit); end count2; --"generic": allows parameterization --in this case the "default" value is 10 ns
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--behavioral description:
architecture behaviour of count2 is
begin count_up: process (clock) --process is sensitive to changes in --the input "clock" variable count_value : natural := 0; begin if clock = '1' then --"level-triggered" count_value := (count_value + 1)
mod 4; q0 <= bit'val(count_value mod 2)
after prop_delay; q1 <= bit'val(count_value / 2) after
prop_delay; end if; end process count_up; end behaviour;
--structural description: architecture structure of count2 is --define components component t_flipflop port (ck : in bit; q : out bit); end component; component inverter port (a : in bit; y : out bit); end component; --define connecting signals signal ff0, ff1, inv_ff0 : bit; begin --instantiate copies of components and --connect them bit_0 : t_flipflop port map(ck => clock, q => ff0); inv : inverter port map (a => ff0, y => inv_ff0); bit_1 : t_flipflop port map(ck=>inv_ff0,q => ff1); q0 <= ff0; q1 <= ff1; end structure;
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more examples: Max+2--max2work--VHDLsubdirectory contains many useful VHDL examples
register example (from Altera--uses "lpm" library):
library ieee;
use ieee std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
entity reg24lpm is
port(d: in std_logic_vector(23 downto 0);
clk: in std_logic;
q: out std_logic_vector(23 downto 0);
end reg24lpm;
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--architecture uses 2 12-bit components;
--other choices are also possible ( 3 8-bit
--components, e.g.)
--to see all options for "lpm_ff", search for
--lpm_ff in the Altera help
architecture a of reg24lpm is
begin
reg12a: lpm_ff
generic map (lpm_width => 12)
port map(data=>d(11downto 0),
clock=>clk, q => q(11 downto 0);
reg12b: lpm_ff
generic map (lpm_width => 12)
port map(data=>d(23 downto12),
clock=>clk,
q=> q(23 downto 12);
end a;
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example of ram:ram256x8.vhd
library ieee;
use ieee std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library work;
use work.ram_constants.all;
entity ram256x8 is
port(data:in std_logic_vector(7 downto 0);
address: in std_logic_vector(7 downto 0):
we, inclock, outclock: in std_logic;
q: out std_logic_vector(7 downto 0));
end ram256x8;
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architecture example of ram256x8 is
begin
inst_l: lpm_ram_dq
generic map (lpm_widthad => 8,
lpm_width => 8)
port map (data => data, address =>
address, we => we,
inclock => inclock, outclock
=> outclock, q => q);
end example;
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Verilog:
Much of the following is taken from the introduction by Dan Hyde at:
http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html
Other references can be found at:
http://www.verilog.net/docs.html
Architectural, behavioral, gate, and switch levels supported
Gate level: logic elements (structural)
Switch level: transistor level
Verilog program can be used for design, simulation, synthesis
Basic construct: module
Verilog program consists of interconnected modules
Usually a “top” module encapsulates all the others
NOTE: Altera does not allow simulation statements
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fig_A1_01
Verilog: a C-like language
Basic parts of a Verilog module:
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Example: a simple structural module in Verilog
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fig_A1_09
Another example of a structural module in Verilog:
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Some simple examples of combinational logic:
// NAND gate (behavioral model)module NAND(in1, in2, out);
input in1, in2; output out; assign out = ~(in1 & in2);
endmodule
//AND gate (structural module)module AND(in1, in2, out);
input in1, in2; output out; wire w1; NAND NAND1(in1, in2, w1); NAND NAND2(w1, w1, out);
endmodule
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fig_A1_02
Typical declarations (“vectors”):
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fig_A1_03
Verilog computation and initialization examples:
(myWires[2] is output, and gate is named a1)
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fig_A1_07
Verilog combinational functions-structural primitives:
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table_A1_00
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table_A1_01
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fig_A1_10
Modeling delays:
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fig_A1_11
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fig_A1_12
38
fig_A1_13
39
fig_A1_14
40
fig_A1_15
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Dataflow: continuous assignment
Syntax:
Assign destination = source
*Destination cannot be a register or a function
*any change in rhs forces a change in lhs—assignment is “always active”
Examples:
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fig_A1_16
(delays added)
Inputs / outputs:
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fig_A1_19
Rise and fall times can also be added
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fig_A
1_21
Dataflow models of sequential logic can be constructed:
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Behavioral level:
In C or C++, execution is sequential
In Verilog execution is concurrent
*Program is a collection of initial or always blocks;*Each block is a separate flow of control, independent of the others*Each block is defined by begin and end statements*Blocks cannot be nested
Two types of procedural assignment:Blocking: sequential: A = B;Nonblocking: parallel: A <= B;
Both can have delays added
Example:
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47
fig_A
1_24
Additional examples from text:
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fig_A1_25
49
fig_A
1_26
50
fig_A1_27
51
fig_A1_28
52
fig_A
1_29