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Hardik Trivedi
M.S (VLSI Design)
Email : [email protected]
Mobile : +91-982-566-5563
Profile Summary
Currently Working as Technical Associate (ASIC Verification) at E-Infochips Training and
Research Academy Ahmedabad.
Master in VLSI Design and experience in ASIC Verification Domain.
In-depth knowledge on ASIC Verification with Verilog and System Verilog.
Excellent communication and presentation skills.
Self-motivated, Responsible, Ability to adapt and willingness to learn.
Professional Experience:
Organization: E-Infochips Training and Research Academy, Ahmedabad.
Duration : July 2015 to till date
Designation : Technical Associate
Description:
To Train graduates and professionals in ASIC Verification Domain.
Project Details:
Current Projects:
Development of Verification IP (VIP) for AMBA AXI3 Protocol based on UVM in System Verilog. Verification IP (VIP) is designed based on suitable UVC (Universal Verification Component) structure for AMBA
AXI protocol specified interface. This Bus base VIP acts as mater or slave to validate IP and user can configure
multiple master or slave without testbench modification. All basic UVC components like driver, sequencer, monitor,
agent, scoreboard, env etc. are designed. Various test cases are generated that provide satisfactory functional coverage
using constraint random verification.
VIP development of AMBA-APB Slave:
I have developed AMBA-APB slave environment in which the whole verification Environment with Layer Test bench
Architecture with different component like Packet class, driver, monitor scoreboard etc. Various test cases are
generated that provide satisfactory functional coverage using constraint random verification using VCS EDA tool.
Develop VIP of USB 3.0 SuperSpeed Physical Layer:
The project aimed at to manage transfer data either on 2.5 GT/s or 5.0 GT/s depends upon the mode and rate. In
Design I manage to capture the data that are coming asynchronously and lock the receiver clock with incoming
asynchronous serial data.
Verify the complete design of USB 3.0 SuperSpeed Physical Layer using System Verilog. I wrote an exhaustive
verification plan from the specifications. I created Verification Environment in System Verilog.
M-Tech Project:
HDLC CONTROLLER DESIGN:
Designed HDLC transmitter using Verilog HDL, HDLC protocol was implemented with transmission of 8bit flag,
followed by data transmission by synchronous FIFO which was further processed by zero stuffing in order to
differentiate data from flag bit during reception. HDLC Receiver received data bit by bit. Reception begins with
recognition of flag register, which indicates the reception of new HDLC frame, followed by zero unstuffing
process, and after that data is received by secondary station.
Academic Profile
Master in Science (VLSI Design)
Manipal University
CGPA 8.43
2012 – 2014
Bachelor of Technology (Electronics & communication)
Rajasthan Technical University
58.31 %
2007-2011
HSC 71.20 %
SSC 72 %
Technical Skills:
HDLs & HVLs Verilog, System Verilog
Verification
Methodology
UVM
Bus Protocols AMBA AXI3, AMBA APB
Serial Protocol USB 3.0 (PHY)
Scripting PERL, Shell Scripting
Tools Synopsys VCS, Cadence NCSim, ModelSim 10.2, QuestaSim 10.2b, DVE
Skills Functional Verification, Constrained-random verification, UVM, Coverage Analysis
Certification:
SOC Verification using System Verilog by Udemy.
Learn OVM & UVM Testbenches from Scratch by Udemy
Achievements:
Secured Runners-up position in Inter Collegiate Volleyball Tournament in Feb 13-14.
Played State Level Volleyball Tournament in 2010.
Secured 4th position in National Level Youth Parliament in 2006.
Paper Represented:
Published paper on “Implementation of USB 3.0 Super Speed Physical Layer Using Verilog HDL” at
International Journal of Computer Applications (IJCA) 95(24):1-5. Published by Foundation of Computer
Science, New York, USA
Published paper on “Design and Verification of USB 3.0 Link Layer (LTSSM)” at International Journal
of Computer Science and Information Technologies (IJCSIT), Vol. 5 (4), 2014, 4916-4921
