HallA DAQ - University of New Hampshirenuclear.unh.edu/~ryan/Doc/HallA_DAQ.pdf · Hall$A$DAQ$Status$ And$Performance$Update$ Ryan$Zielinski$ Hall$A$Collaboraon$Mee>ng$–June$7,$2012$

Hall A DAQ Status And Performance Update

Ryan Zielinski

Hall A Collabora>on Mee>ng – June 7, 2012

Outline • g2p/gep DAQ Setup • Single Arm HRS DAQ • HAPPEX DAQ

• Improving Performance – Lower Dead>me • Addi>onal HRS FASTBUS crate • SFI Sequencer • Intel/Linux CPU

• g2p/gep DAQ performance

Hall A Collabora>on Mee>ng June 7, 2012

Trigger Supervisor

Scalers

HRS DAQ


CAMAC/NIM Logic Ring

Buffer�Fastbus Crate

1881M ADC

1877 TDC VX

WORKS CPU

CODA�

Event Builder�

Event Recorder�

TM RT

*.dat �

• LHRS and RHRS DAQ operate independently (singles) • 3 fastbus crates, TS scaler crate and HAPPEX crate on each arm

• Main triggers S1.AND.S2m • Efficiency triggers 2/3 of S1/S2m/Cer

ADC gate

TDC Stop

Triggers

Detector Signals

Strobe

L1A

• TS running ring buffer server • Main Triggers, Helicity, BCM scalers added into ring

HAPPEX ADC�

FLEXIO � VXWORKS CPU

yes �

Ring Buffer Server

TCP-‐ IP Server�

Ring Buffer�

HAPPEX DAQ


Happex Crate

Timing Board �

Trigger �

Timing Board �

HAPPEX ADC�

FLEXIO �

MPS �

VXWORKS CPU

Gate�

Pair Sync�

QRT �

Helicity yes �

Ring Buffer Server


Ring Buffer�

Trigger �

HAPPEX DAQ


BCM, BPM, Raster�

Timing Board �

HAPPEX ADC�

FLEXIO �

MPS �

VXWORKS CPU

Trigger �

Gate�

Pair Sync�

QRT �

Helicity yes �

Ring Buffer Server

Read ADC,Flexio�

Write to Ring Buffer�


Ring Buffer�

Trigger �Trigger �

HAPPEX DAQ


BCM, BPM, Raster�

Timing Board �

HAPPEX ADC�

FLEXIO �

MPS �

VXWORKS CPU

Trigger �

Gate�

Pair Sync�

QRT �

Helicity yes �

Ring Buffer Server

Read ADC,Flexio�

Write to Ring Buffer�


Ring Buffer�

Linux �

TI�

HRS Trigger

Supervisor

T1,…,T8 �Trigger(s) �

CODA�

Event Builder�

Event Recorder�

control �

Read �

*.dat �

Other ROCs & TIs �

Trigger �Trigger �

HAPPEX DAQ


BCM, BPM, Raster�

DAQ Dead>me


Trigger Supervisor

HAPPEX CRATE

• Maintains system busy • 8 event buffer • Checks buffer status

Front End Module

ROC

• Readout >me • Module #/Single Mul>-‐block reads • If buffer not full readout occurs with conversion Conversion Times:

1881M ADC -‐ 12μs 1877 TDC -‐ 1.6 μs

• ADC/TDC • Conversion Time • Must occur for every event

• Minimal dead>me contribu>on • Ring buffer

Fastbus Crate

Front End Busy

Buffering separates front end >me from readout >me Scaler readout is >ed to “sync events”

Sync events are unbuffered and check sync status of crates

Improving Dead>me THIRD FASTBUS CRATE

• Third Fastbus crate added to each arm • Redistribu>on of modules lowers readout >me

• Slowest crate dominates – ADCs add most to readout

• Fastbus transfer rate 20Mb/s


Readout Time Module Distribu2on

Roc 3 50.4 μs 8 TDCs (block read), 1 ADC

Roc 4 52.0 μs 8 TDCs (block read), 1 ADC

Roc 5 90.4 μs 2TDC, 4 ADC (3 are in block read)

ROC Busy Times – Measured with cosmics

• Implemented on sooware level

• Preprogram into SFI RAM Fastbus calls • Up to 40% improvement in execu>on >me

• CRL code exists but only briefly tested • Was not implemented for g2p


Thanks to Dav

id Abbor for

his help!

Improving Dead>me SFI SEQUENCER

Improving Dead>me INTEL/LINUX CPU

• Intel CPU successfully integrated into DAQ – Libraries now exist for 1877 TDC and 1881M ADC

• Did not see definite improvement in readout – Was not used in g2p

• SFI Sequencer not yet implemented for Intel


DAQ Performance LHRS RESULTS


Produc>on running 6.5 kHz with ~25% dead2me with PS3 = 1!

T3 (kHz) PS3 DT (%)

6.5 1 25

15 2 20

22 3 20

30 4 20

0 10000 20000 30000 40000 50000Raw T3 Trigger Rate (Hz)

0

10

20

30

40

50

60

70

80

90

Dea

dtim

e (%

)

Produc2on Running

0 10000 20000 30000 40000Raw T1 Trigger Rate (Hz)

0

10

20

30

40

50

60

70

80

90

Dea

dtim

e (%

)


DAQ Performance RHRS RESULTS

Produc>on running 6.1 kHz with ~25% dead2me with PS1 = 1!

T1 (kHz) PS1 DT (%)

6.1 1 25

15 2 25

22 3 20

30 4 21

Produc2on Running

CONCLUSION

• Successfully integrated Happex DAQ into HRS DAQ • Addi>onal (third) Fastbus crate improved DAQ DT – Ran at 6.1 kHz (R) and 6.5 kHz (L) with 25% DT – Even higher if you prescale

• In the future… – Fully integrate SFI Sequencer – Replace VXWorks CPUs with Intel CPUs


THANKS!

• I would like to thank the following people who helped contribute to the DAQ success! – Bob Michaels – Alexandre Camsonne – Jack Segal – Vince Sulkosky – Melissa Cummings – Pengjia Zhu


ADDITIONAL SLIDES

DAQ Performance DEADTIME MODEL


If the expected number of occurrences in a given interval is lambda, then the probability that there are exactly k occurrences (k = 0,1,2…) is

€

f (k;λ) =λke−λ

k! Can break down dead>me components into two infinite sums

€

Dc =µcne−µc

n!n=1

∞

∑

€

DR =µR(n+b )e−µ R

(n + b)!n=1

∞

∑

b is the buffer factor, R is rate, μC = RTC, μR = R(TR –TC), TC is conversion >me, and TR is the readout >me

DAQ Performance LHRS RESULTS!


!

!

!

!

!!

0 5000 10000 150000.0

0.1

0.2

0.3

0.4

0.5

Rate !Hz"

Deadtime

Model

Comm.

Crate Tc (μs) TR (μs)

Happex/TS 36

Fastbus 12 90

December commissioning data compares favorably to model

December Commissioning


!

!

!

!

0 5000 10000 15000 200000.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

Rate !Hz"

Deadtime

Model

Comm.

Crate Tc (μs) TR (μs)

Happex/TS 44

Fastbus 12 100

DAQ Performance RHRS RESULTS!

December Commissioning

Documents

HallA DAQ - University of New Hampshirenuclear.unh.edu/~ryan/Doc/HallA_DAQ.pdf · Hall$A$DAQ$Status$ And$Performance$Update$ Ryan$Zielinski$ Hall$A$Collaboraon$Mee>ng$–June$7,$2012$