Hack Into a Stopwatch to Make a Phototimer PDF

7/30/2019 Hack Into a Stopwatch to Make a Phototimer PDF

1/5

Detecting a rapidly falling signalover some threshold is important

for ultrasonic or location equipment aswell as for seismology systems. You cancombine a rail-to-rail operational ampli-fier with a Schmitt-trigger logic gate toperform this function (Figure 1). Thisexample works well in an ultrasoundmachine. It controls a sample-and-holdamplifier that sets the gain of an AGC(automatic-gain-control) system.

The circuit works only with positivesignals, so the signal must pass througha full-wave rectifier before it is appliedto the circuit input. You configure themain part of the circuit, op amp IC

1,

as a comparator with hysteresis. It

produces a high-level output when aninput signal is higher than the specifiedthreshold. The output goes to a lowlevel when the input signal begins to fall

but only when the input falls faster thanan established rate of change or if thelevel of the input signal will be lowerthan the established threshold of sensi-tivity. This circuit detects the momentwhen a signal is above the establishedthreshold and the falling signalor amix of the signal and noisehas higher-than-specified speed.

R1

and C1

form an input lowpassfilter to smooth the input signal. Youset the values of R

1and C

1to create a

filter roll-off for the input signal you areprocessing. Resistors R

3and R

4establish

a small hysteresis, which is necessaryso that slow signals with noise dontcause the output to change state. You set

the threshold level with voltage dividerR6

and R7. D

1, R

5, and C

2form a peak

detector. R5

establishes a time constantof the discharge of C

2and provides

sensitivity to a falling signals rate. Youestablish the circuits sensitivity to afalling signals rate of change using thetime constant, which the values of C

2

and R5set. Hysteresis resistor R

4is more

than a decade larger than R5, so the

effect of resistors R3and R

4is negligible.

A rising input signal greater than thethreshold charges C2

to approximatelythe level of the input signal. The outputamplifier is at a high level because the

Crcut etects rap fag sgasa rejects oseVamr Retu, Zaporozhe, Urae

DIs Inside

42 Hac to a stopwatchto mae a phototmer

44 Comparator rect cotrospower-MOSFET gate

46 AGC crcut usesa aaog mutper

To see all ofEDNs DesignIdeas, visit www.edn.com/designideas.

IC1LMC7101BIM5

IN

V

IN+

V+

OUTR33.3k

R23.3k D2

BAS40-04

IC274HC132

R111k

R510k

R6150

C222 F16V

C110 F

C3100 nF

R4150k

D1BAS58

+

4

3

5

R71k

C4100 nF

1

2

2

5V

+

1

2

INPUT

5V 1

3

4

3

OUTPUT

3

2

1

5V

Fgure 1 Ths crcut etects sga excursos hgher tha a set thresho a rejects ose a recogzes fast fag sgas.

readerS SOLVe deSIGN PrOBLeMS

EdiTEd By PAUl RAkOAnd FRAn GRAnVillE

designideas

NOVEMBER 3, 2011 | EDN 41[www.edn.com]


2/5

voltage on C2

is always lower than thevalue of the rising input signal due toD

1s voltage drop. When the input drops

faster than C2

can discharge through R5,

the output level of the device changes toa low level because the voltage on C

2

ishigher than the value of the falling inputsignal. If the input signal falls more slowlythan the discharge of C

2through resistor

R5, the output remains high. Schottky

diode D1

prevents the discharge of C2

through the input. R2and D

2clamp the

amplifiers output to positive values. Feedthe clamped signal to Schmitt-triggerlogic gate IC

2to give a logic-level output

with fast transitions (Figure 2).EDN

The exposure tester in thisDesign Idea measures the on time

of a light source, whether an LED, anincandescent lamp, a halogen lamp, oranother source. It can be made with anordinary stopwatch and a few simple

components (figures 1 and 2). An elec-tronic stopwatch needs two pulses tooperate; one starts the internal counter,and another one stops it. A light sourceprovides only one pulse, corresponding

to the time the light is illuminated. Thiscircuit generates a short trigger pulsewhenever the luminous intensitychanges.

When the photodiode is not illu-minated, capacitor C

1charges to 1.5V

(Figure 3). The charge initially comesthrough the base-emitter junction of Q1

with a time constant that R1C

1sets.

Once C1charges to 1.5V minus the base-

to-emitter voltage, R3tops off the charge

on C1

until it reaches 1.5V. Because R3

and R1are in series during this time, this

topping off occurs with a slower timeconstant that (R

1+R

3)C

1sets.

When the photodiode is illuminated,photocurrent flows through R

1, raising

its voltage to more than 0V, which drivesthe right side of C

1above the 1.5V rail.

The base of Q1is reverse-biased and has

no effect. However, Q2s emitter is now

forward-biased because R4holds the base

near 1.5V. As Q2turns on, the charge in

C1 dissipates across R2, raising its voltageand creating a positive pulse. You con-vey this pulse to the stopwatch throughR

5, which is necessary in the case of

extreme illumination of the photo-

Hac to a stopwatchto mae a phototmerRaf kez, Seefe, Germa

OUTPUT SIGNAL

THRESHOLD OF

SENSIBILITY

INPUT SIGNAL

Fgure 2 The crcut recogzes a puse whe t fas; ose s exaggerate for cart.

Fgure 1 you bu the crcut o a sma prototpe boar

that coects to the CG-501 stopwatch.

Fgure 2 you ca soer pgtas to brg power, grou, a the

trgger crcut to the prototpe.

designideas

42 EDN | NOVEMBER 3, 2011 [www.edn.com]


3/5

diode. It limits the current into thestopwatch circuitry so that a large pulsecannot latch or overpower the internalstopwatch circuitry. The photocurrentcreates a difference between 1.5V andthe voltage of R

1

; this difference causesC

1, under illumination, to enter a final

voltage.When the photodiode is not illumi-

nated, no photocurrent goes through R1,

so C1

can charge back up as its left sidegoes to ground and its right side goes firstto a base-emitter drop below 1.5V andsubsequently all the way to 1.5V. Becausethe initial charge conducts through thebase-emitter junction of Q

1, that tran-

sistor again turns on, delivering a pulseacross R

2and halting the stopwatch.

Your selection of the value ofC

1depends on the exposure time

to be measured and on the photo-

diode used. The response rate of thiscircuit is approximately 500 msec. Thisexample uses an Everlight PD333-3C/

HO/L2 photodiode with a large spectralbandwidth, but any other photodiode oreven a photoresistor will also work.EDN

It is common practice to power aMOSFET with a comparator and

with an unregulated voltage and to

power the comparator driving it from aregulated one (Figure 1). Many loads areinsensitive to driving voltage, so it wouldbe a waste of money and power to use aregulated supply to drive the FET. It isalso common practice to add resistors R

1

and R2

to the comparator to put hyster-esis in the operation, making the circuitless susceptible to noise, especially withslowly changing signals.

This circuits comparator changeswith changes in the unregulated powersupply. You can correct this problem

by adding diode D2 and resistor R5 tothe circuit (Figure 2). This approachisolates the hysteresis circuit from theunregulated output and instead drivesit from the same regulated supply thatdrives the comparator. When the com-parator is on, it drives the FET just asthe original circuit does, pulling theP-channel FET gate toward ground. Inboth cases, you connect zener diode D

1

to the FET gate to avoid exceeding thegate-to-source voltage. The improve-ments in the circuit inFigure 2 become

Comparator rect cotros power-MOSFET gatePeter demcheo, Vus, lthuaa

Q1BC557B

Q2BC557B

R310k

R410k

R515k

C122 F

R110k

R256k

CG-501STOPWATCH

START/STOP

1.5V

SPLIT/RESET

GND

i

+ R11k

R21M

R48.2k

R3560

RLOADVTHRESHOLD

AD8230

LM193

+

781515V

C1

D1

20V UNREGULATED

+ R11k

R21M D2

1N4448

R48.2k

R515k

R3560

RLOADVTHRESHOLD

AD8230

LM193

+

781515V

C1

D1

20V UNREGULATED

Fgure 3 Ths smpe crcut tmes a ght source. Whe ou umate the photooe,Q

2creates a puse. Whe ou remove the umato, Q

1creates a puse.

Fgure 2 Resstor R5

a a ORg oe soate the hsteress crcut from the

power supp a eep the swtchg pot costat o matter how the power sup-

p chages.

Fgure 1 Hsteress compoets R1

a R2

te to the ureguate supp, causg the

comparators swtchg pot to var wth the power supp.

designideas



4/5

apparent when the comparator turns off.In either case, R

4pulls the comparators

open-collector output up to the positivepower supply. InFigure 2, however, thediode isolates the hysteresis circuit fromthe power supply so that R

4

pulls up R5

to the regulated 15V, no matter how thepower supply changes.

With a legacy comparator suchas Texas Instruments LM193, thecommon mode of the inputs muststay well below the power-supply rail(Figure 3). The circuit requires 1.5Vhead room at 25C and 2V head roomover temperature. Thus, for the circuitsin figures 1 and 2, you cannot set thethreshold voltage higher than 13V. Ifyour circuit requires a threshold voltagecloser to the power rail, consider usingnewer parts with rail-to-rail inputs. Youmust use an open-collector or open-drain comparator for this hysteresis-isolation circuit to work. It would beincompatible with a totem-pole-outputIC.EDN

IN+

10 A 60 A 10 A

80 A

80-ACURRENT REGULATOR

IN

OUT

VCC

Fgure 3 The tera esg of the lM193 comparator requres that ou eep the

put ps 2V beow the postve ra (courtes Texas istrumets).

NOVEMBER 3, 2011 | EDN 45[www.edn.com]


5/5

In the AGC circuit ofFig 1, a4-quadrant analog multiplier

(IC1), an amplifier stage (IC

2), an

active, full-wave rectifier (D1, D

2, R

4-R

7,

and IC3), and an integrator (IC

4)

accomplish automatic gain control ofV

INs amplitude variations in the audio-

frequency range.The multipliers output is V

INV

Y/10,

where VY

is a negative voltage gener-ated by the integrator IC

4. Together,

the integrator and the rectifier extractthe dc component (V

Y) of V

OUTfor use

as a feedback signal to the multiplier.The integrator sums signal current fromthe rectifier and control current from

potentiometer R9, which lets you adjust

VOUT

s signal level.Circuit analysis yields the frequency-

response equation

VOUTK1AVC10RC3

,=1

10As+RC3

or, in the time domain,

VOUTK1AV

C10RC3

.= 10AtRC3exp

In both equations, K1

is the gain ofamplifier IC

2, A is the peak amplitude

of VIN

, and R is the resistance between

AGC crcut uses a aaog mutperSteve lubs, departmet of defese, Washgto, dC

Originally published in the September 4, 1986, issue of EDN

CLASSICS

Fgure 1Aaog mutper iC1

combes Vin

wth a feebac sga Vy

to acheve automatc ga cotro.

Want to

see more

of the

classics?

Revisit 50 of the

best Design Ideas

from the Golden

Age of electrical

engineering.

http://bit.ly/DesignIdeasClassics

the integrator input and the rectifieroutput. (For this circuit, R equals R

6in

parallel with R7.)

This AGC circuit is suitable forcontrolling the long-term variationsof amplitude within a limited range. Itdoesnt respond uniformly over a widedynamic range, however, because thetime response is inversely proportionalto input-signal amplitude.EDN

designideas


Documents

Hack Into a Stopwatch to Make a Phototimer PDF