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Communications R&D Center

Status and Trends of SiGe BiCMOS Technology

David HarameManager SiGe BiCMOS Simulation,

Modeling, Design Automation,Verification, and Release Department

IBM Communications Research and Development CenterEssex Junction, VT

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Outline - Introduction

Introduction

IBM Technology overview

Total Technology SupportSiGe BiCMOS production circuits

Summary

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Graded Base SiGe HBT

Narrow bandgap baseBase "quasi-electric field"Small EG at E-B jct.

G e r m a n i u m

C o n

t e n t

Emitter Base Collector

E n e r g y ( e v

)

N P N

Si

SiGe

EF

EV

EC

e -

e -e -

High emitter dopingMedium base dopingPolysilicon emitter

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Key Technology Enablers and Issues

Key Enablers: CMOS integration + PassivesHigh Level Integration differentiates BiCMOS from III-V

CMOS in BiCMOS must exactly match base CMOS

HIgh Q passives differentiate technology providersMonolithic circuits require high Q passives

Key issues: Process IntegrationConflicting CMOS / HBT thermal budget requirements

Addressed with integration methodology

Shrinking CMOS interconnects non-optimal for RFSpecialized metal systems for RF

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Outline - SiGe Technology

Introduction

Technology overview

SiGe HBT BiCMOS integrationSiGe HBT DifferentiatorsPassives


Summary

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"Base-after-gate" integration flow

Major thermal cycles prior to base depositionLow thermal-cycle HBT module

CMOS / Common Bipolar/Analog

Ref: S. St Onge, BCTM 99

Shallow Trench Isolation

FET Well ImplantsDual Gate Oxide & Gate Formation

LDD Implants & AnnealsSpacer Formation

Silicide & ContactsStandard 2 to 6 Metal Layers

Includes MIM Capacitor

Subcollector & n-EPI Deep Trench Isolation

Collector Plug Implant

Thick Metal Add-On Module

pFET S/D/G Implants nFET S/D/G Implants

HBT Module: Bipolar Window Open SiGe Epi Base Growth Extrinsic Base, Collector & Emitter Formation

Source/Drain and Emitter Anneal

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Process Flow for 0.25 m SiGe BiCMOS

Poly Resistor

N-N+NWellN+

P-

N

N+

P-

N+

P-

N- EpiN+

P-

N+

N- Epi

Single Crystal UHV/CVD SiGe Window Poly protect

P-

N-N+NN+

P-

NWELLN+

Gate Poly

P-

N-N+N

N+

P-

NWELL

N+

P P

NPN PFET

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Poly ResistorNPN PFET

P-

N-N+N

N+

P-

NWELL

N+

P P

P-

N-N+N

N+P-

NWELL

N+

P P

P-

N-N+N

N+

P-

NWELLN+

P P

P P

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P-

N-N+N

N+

P-

NWELL

N+

P P

P P

P-

N-N+N

N+

P-

NWELL

N+

P P

P P

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P-

N-N+N

N+

P-

NWELL

N+

P P

P P

P-

N-N+N

N+

P-

NWELL

N+

P P

P P

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SiGe HBT Cross Section ( 0.25 m SiGe BiCMOS)

Deep Trench

ExtrinsicBase

Collector

EmitterIntrinsic

Base

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f T comparison

0.18 m generation performance increase 2.5XVertical + lateral scaling gives higher performance atlower power

1E-5 0.0001 0.001 0.01 0.1

Ic (Amps)

0

20

40

60

80

100

120

140

f T ,

G H z

0.5 mgeneration1m2

VCB = 1V0.18umgeneration1m2

0.16 m2

0.25 mgeneration0.35 m2

Lateralscaling

Verticalscaling

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HBT MAG and h21

120 GHz f T

100 GHz f MAX (fit to MAG @ 40-70GHz)

h212

MAG

0.18x4 junction areaVBE=0.90V V CB=1V

10 100

Freq (GHz)

1

10

100

M

A G

, h 2 1 * * 2

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SiGe Bipolar/BiCMOS Roadmap

3 generations of SiGe Production

Production

1997 1998 1999 2000 2001 2002 2003

Main Technology DerivativeHigh Speed NPN Ft / BVceo

High Breakdown NPN Ft / BVceo

Bipolar

CMOS

0.5um3.3v

0.5um3.3, 5v

0.25um2.5v

0.18um1.8v

0.13um1.2v

45 GHz / 3.3v25 GHz / 5.5v

19971996

50 GHz / 3.3v19 GHz / 7.8v

5B0

5MR20 GHz / 9.5v

50 GHz / 3.3v

29 GHz / 5.5v5HP

6HP50 GHz / 3.3v29 GHz / 5.5v

7HP120 GHz / 2.0v50 GHz / 3.3v25 GHz / 5.5v

> 150 GHz / 2.0Vtbd / tbd

8T

BiCMOS Production

5HE Bipolar Production

Base DuringGateIntegration

Base AfterGateIntegration

End OfLife

BiCMOS Production

BiCMOS Production

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Technology Summary Table

Lithography m 0.5 0.25 0.18NPN fT (Hi BV/HP) GHz 28/45 28/45 30/120

NPN fMAX GHz 50/60 50/60 50/100NPN BVCEO V 5.5/3.3 5.5/3.3 5.0/2.1

NPN Density relative 1x 1.15x 1.52x

Emitter Width m 0.42 0.3 0.18

NFMIN dB 0.8 0.8 0.4CMOS Supply V 3.3 2.5/ 3.3 1.8/ 3.3

CMOS Pwr mW/MHz/gt 0.3 0.1 0.03CMOS Gate Delay ps 90 50 33

CMOS Density relative 1x 4x 7.5x

BEOL M1 CurrentDensity

relative 1x 0.94x 1.5x

BEOL Metal Material Al Al Cu

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Differentiator: Performance - f T Range

Epi base and SiGe grading enable 150-200Ghz. HBT performance.Generations of HBT's are selected by market needs, eg.BVceo.

f T & f max alone provide no information as to technology advancement.

Johnson Limit

Peak F (Ghz)0 20 40 60 80 100 120

0

2

4

6

8

10

B

V c e o

( V o

l t s )

t

Gen 5&6 HBT

SiGe HBT'sSi BJT's

Gen 7 HBT

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Differentiator: Linearity

Linearity efficiency = OIP3 / PDC

Technology OIP 3 (dBm) P DC (mW) Linearity Eff.

IBM SiGe HBT 25 16.2 19.5GaAs HBT 25 29.1 11GaAs HEMT 23 20 10GaAs MESFET 20 60 2Si BJT (max.linearity) 27 46 11

Si BJT (max. f T) 22 40 4

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Differentiator: Noise Performance

Excellent NF MINNoise improvements into 0.18 m generation

0 1 2 3 4 5 6 7 8 9 10 110.00.20.4

0.60.81.01.21.4

1.61.82.02.22.4

2.62.8

Present (34 m2, 3 mA, 3 V)

Next (56 m2, 10.7 mA, 2 V)

M i n

. N o

i s e

F i g u r e

( d B )

Frequency (GHz)

0

2

4

6

810

12

14

16

18

20

solid lines = model

A s s o c i a

t e d G ai n

( d B

)

Ref: D.R.Greenberg IMS 2000GGF 12/8/99


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Passives DevelopmentTwo Modes of Development

New Technology DevelopmentEnhancements on existing technologies

Device Type Issues Solutions

Inductors Spiral Q Thick dielectric moduleThick metal10-20 -cm substrates

Capacitors Poly-Ins-Single xtalPoly-Ins-PolyMetal-Ins-Metal

DensityReliability(Voltage rating)

VCCQ

Optimize processesOffer variety

Resistors PolysiliconBEOL thin filmSingle-crystal diff'n

ToleranceTCRParasitic C

Current rating

Process controlOffer varietyLayout options for low C

Varactor JunctionMOS accumulation

Tuning rangeQLinearity

Offer varietyLayout tradeoffscaptured in models

Interconnect Transmission line

Local interconnect

CMOS compat.

ElectromigrationLoss

Low levels - CMOS

Upper levels - thickCopper

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Metal Layer Stack Comparison0.25 mBiCMOS

DTSTI

M1

MT

M2

M3

AM

0.5 mBiCMOS

M1

M2

LM

DTSTI DT

LY

M1

M2

M3

M4

STI

AM

0.18 m

BiCMOS

"Analog" metallevels

CMOS ASIC

compatiblelevels

CMOSscaling

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Typical spiral cross-section and model topology

Silicon

Inductor Spiral

Via

Underpass

Si02dielectricheight

(P-)

SPICEmodel

L1: spiral inductance

R1: spiral series resistanceC3: spiral to underpass +turn-to-turn capacitance

C1&C2: spiral to substratecapacitance

R2&R3: substrate resistance

C4&C5: substrate capacitance

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Thick metal/dielectric add-on module100% increase in metal thickness (2 m to 4 m)

75% increase in dielectric thickness (5 m to 8.7 m)

4m

3m

P- substrate (15 -cm)

Standardmetal

Achieves inductor Q values approaching 20GGF 12/8/99

MOM simulation of multi-turn spiral


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pcurrent flow

Current crowding more pronounced in multi-turn coils

Additional metal thickness

allows more "sidewall" forcurrent flow, reducingeffective resistance

Edge Current

More even distribution

Edge current

Spiral line with current crowding

Expected areaof sidewallcurrent flow

4m

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Outline - Total Technology Support

IntroductionTechnology overview

Total Technology SupportOverviewModels

Design AutomationSiGe BiCMOS production circuits

Future directions

Summary

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Total technology supportFoundry and internal designs supported by IBM

ModelsAccurate, scalable & statistical RF models includingmatching, temperature, frequency, & bias

Cadence and ADS based design environmentsTime Domain and Frequency Domaing simulation

Application support organizationsTechnical specialists for analog and CMOS ASICTraining in technology & design environment

Product engineering organizationSupports customer through manufacturing environment

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IBM BiCMOS Model Methodology

AdvancedAdvancedModels forModels forAdvancedAdvanced

DesignDesign

Process Based Statistics!"Optimal Prediction of ManufacturingLine"

Scalable Models!"Optimal DesignFlexibility"

ScalableScalableStatisticalStatistical

ModelModel

PhysicalPhysicalLayoutLayout

Device ScalingDevice ScalingEquationsEquations

In-lineIn-lineElectricalElectrical

DataData

StatisticalStatisticalProcessProcess

DescriptionDescription

Nominal LotNominal LotCharacterizationCharacterization

Split LotSplit LotCharacterizationCharacterization

DesignDesignRulesRules

DeviceDevice

PhysicsPhysics

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Characterization Data Inputs to Final Model

Physical &Physical &ProcessProcess

SimulationSimulationDataData

FinalFinalModelModel

In-LineIn-LineElectricalElectrical

DataData

Test SiteTest SiteHardwareHardware

DataData

Rc

W/2 XATAN

Arc Edge

Body

L d r a w n

L e f f

1E-4 1E-3 1E-2 1E-1Ic (A)

0

50

100

150

200

f T ( G H z

)

0.25x5 m2

0.5V V CB

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Important Modeling Aspects

Physics/process based models simplify development of newfeatures or extensionsUse of industry standard models allows support for multiple vendorsimulators

e.g. HSPICE, SPECTRE, HP-ADS

Model GenerationParameter extraction using near-nominal hardwar

Nominal models re-centered

Salability across range of device geometriesStatistical tolerances based on in-line data and process splitlots

Model Verification

Device /Model across bias, temperature conditionsReview parameter correlations with process splitsEnsure corner definitions maintain proper physical relationsVerify Monte Carlo analysis results against process specs

Ensure Kit Integration correct

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General

Define Gaussian distributions to representprocess/lithography variations/some extracted parametersFirst order correlations based on physical relationships orcommon/shared process steps

e.g. NPN Ic and Va correlated with base pinch resistanceDevice models include localized device mis-matchMonte Carlo

Random variation of all defined process distributionsModel parameters recalculated for each combination ("case")Each "case" represents one point of expected process rangeGives best approximation of manufacturing process variationMost time consuming but best analysis

Corner Models

Specific skew of dominant parameters assumedRepresents typical "up" / "down" device performanceDefault "up" / "down" may not be valid for all bias,temperature conditions or circuit applications

Statistical Philosophy - Monte Carlo/Corners

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RF CMOS (MOSFETs) Models

Current MOSFET models:AC characterized to 50 GHzExtrinsic gate and substrate resistance elements added to

BSIM3v3.2 core for improved frequency responseScalable width, length and multiple gate finger geometriesUse of the BSIM3v3 thermal and 1/f noise equationsNon-quasi-static (NQS) model, device temperature differences,and adjacent Vth mis-match f(W,L)

Future Enhancements:Migration from BSIM3 to BSIM4 modelNoise figure / large signal measurements & correlation g

Rgate Rsub Simplest Case

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Resistor Model Topology


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Distributed R-C subcircuit improves accuracy athigher frequencies over single lumped R-C elements

Typical resistance model accuracy within 5% across-55C to +125C range (body and end R separate T coef)

Additional parasitic diiode element included forresistor within NWELL or NS, as needed

Scalable width and length geometries

Rend/2 Rbody/2 Rbody/2 Rend/2

Cpar/6 2Cpar/3 Cpar/6

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Ad d SiG HBT VBIC M d l


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Advanced SiGe HBT VBIC Models

Advanced VBIC modeltopology includes separateelements:

Current source for impactionizationSelf-heating networkFixed oxide capacitances(E-B, C-B)Extrinsic seriesresistancesParasitic PNP to substrate

Separate impact ionizationcurrent source required toproperly modelhigh-breakdown type NPN

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SiG HBT F M d l G h


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SiGe HBT Future Model Growth

Evaluation / extraction for other advanced BJT models:

HiCUM (Schroter)MEXTRAM (Phillips)

Extend model and measurement correlation for:Noise figure data and Large signal data

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SiGe Design Methodology


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SiGe Design Methodology

Frequency Domain SimulationAgilent ADS

Harmonic Balance/HF SpiceCircuit Envelope

Schematic CaptureCadence Composer

LayoutParameterized Cells (PCells)Virtuoso-XL/DLE LayoutEditor

ID F

R e s

i m u

l a t i o n

IBM SiGe Design KitScaleable VBIC HBT ModelPFET, NFETSpiral inductors, StackedMIM, Resistors, Varactor,ESD

Parasitic ExtractionCoeffgen, PRE, LPESequence Columbus RF (1Q01)Cadence RCX (2Q01)

Time Domain SimulationCadence Analog ArtistSpectre Direct

Design VerificationLVS/DRCHierarchical CheckingDIVA & Assura

R e s

i m u

l a t i o n

GDS II

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Outline SiGe Production Circuits


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Outline - SiGe Production Circuits



Wireless

WiredStorage

Future directions

Summary

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Tri-Band LNA/Image Reject Mixer


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Tri Band LNA/Image Reject Mixer

ProductTri-band GSM Image Reject Mixer with LNA

Features900MHz, 1.8GHz and 1.9GHz operationLow power with sleep mode and singlesupply (3.0V) operationFully integrated differential design includingLNA for improved performance

Integrated IF phase shifter/combiner and LOquadrature generator which simplifies useFlexible design with external low sensitivitymatching

CMOS compatible band select logic control

RCpoly-phasefilter

IF+IF-

DCSLO

GSMLO

LOQuadGen.

4:1RF+

4:1

RF-

RF-

RF+

Band Control

Band sel.

Bias Control

VccLNA

VccMix

Sleep

LO LO LO LO

Frequency (MHz) 935-960 MHz (GSM)1.8-2.0GHz(DCS/PCS)

Cascade Gain 22 dB

NF 3.5 dBRF Input VSWR < 2:1

LO Input VSWR < 2:1

IIP3 -14 dBm

LO Power 200mVp ECLSupply Voltage 2.7-3.3 V

Supply Current < 30 mA

Port Isolation (min) 20 dB (all ports)

Image Rejection > 30 dB

IF Frequency 400 MHzIF Load Impedance 600

Package TSSOP24Temperature -40 to +85C

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TDMA Power Amp


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IBM

Measured"Typical"

GaAs Data

SheetTypical

AMPSP OUT 31 32

Gain 27 26PAE 53% 50%NADCP OUT 29.5 30

Gain 29.5 28PAE 48 45ACPR -26 -28ALT -48 -48Ruggedness 10:1@5V 10:1@5

V

TDMA Power Amp

Competitive specs to GaAsIntegration potential, lower cost

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2 5 GHz Frequency Synthesizer


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2.5 GHz Frequency SynthesizerExample of non scaling in Analog & RF chips

Wirebond pad counts and passives do not scale withreducing lithography dimensions

Pad count detemining peripheral chip dimensionsLarge passives dominate space consumption

40% of space determined by two capacitorsLarge area inductors

3.8x2.0 mm2

M. Soyuer, IBMYorktown Hts., NY

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Intersil Wireless LAN Chipset


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Intersil Wireless LAN Chipset

Commercial product2.4 GHz (ISM Band)3 SiGe BICMOS + 1 CMOS chipsReplaces 8 chips (some GaAs) +board components

> 2 Million chip sets shipped

Block Diagram, I/Q Modulator/ Demodulator

CAL ENABLE

IF DETECTOR OUTRECEIVE AGCBASEBAND RXI

BASEBAND RXQ

OFFSETCAL

I

Q

TRANSMIT IF AGC

BASEBAND TXQ

BASEBAND TXI

IF_IN

IF_OUT

0/ 90 PLL MODULE IF 2X LO/VCO INCHARGE PUMP OUT3-WIRE INTERFACEREF IN

O

Specification HFA 3726 (old) HFA 3783 (new-SiGe)Pin Count 80 48Radio Bit Rate 2 MBit/ s 11 MBit/ sReceiver Icc 70 mA 36 mA

2x Loc. Osc. Freq. 20-800 MHz 160-1200 MHzGain Control Limiter Tx and Rx AGCRX Phase Balance +/- 4 degrees +/- 2 degreesTx Carrier Suppression -28 dBc max -30 dBc maxPhase detector Icc 0.8 mA 0.1 mA

Baseband Coupling AC DC w/ internal offsetcorrection

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Digital Network Switch


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Digital Network Switch

Highest level of HBT integration published (1997)(highest integration today > 150K - not published)

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Production PRML Read Channel


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First SiGe product at 0.25 m1200 SiGe HBT's300K Gates 0.25 m CMOS Logic (>1,000,000 Transistors)>75 200mm wafers/day in production at IBM Burlington

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Alcatel 10Gbit/sec SONET

10 and 40 Gbps Circuits with IBM SiGe

First Experimental Multi Chip Reticle 18 x 18 mm All 10 Gbps circuits were first time right The chips have been moved to production directly The average circuit yield is > 90%

10 Gbps Clock and Data Recovery Multi Chip Module

8:1 MUX13 Gbps5 V, 2.5 W2000 Tr.

3 x 3 mm

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68x69 Cross-Point Switch


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68 x 69 differential crosspoint switch

NRZ data rates up to 3.2 GbpsRise/fall times of 85 picoseconds1.8 picoseconds typical RMS jitter accumulationBandwidth-to-power ratio over 30 gigabits per watt

SAN DIEGO, August 22, 2000 - Applied Micro Circuits Corp. (AMCC) [NASDAQ:AMCC], a leader inhigh-bandwidth silicon connectivity solutions for the world's optical networks, today announced theS2090, the industry's first very high-speed Silicon Germanium (SiGe) 68 x 69 differential crosspointswitch with full broadcast switching capability. Ideal for use in high-speed applications such as DenseWavelength Division Multiplexing (DWDM) switching, digital video, high-speed automatic testequipment (ATE), and datacom or telecom switches, the S2090 can handle NRZ data rates up to 3.2Gbps per channel with corresponding output rise/fall times of 85 picoseconds. Furthermore, the S2090also demonstrates and unprecedented 1.8 picoseconds typical Root Mean Square (RMS) jitteraccumulation and sports power optimization features, which can achieve typical power dissipation aslow as 7 Watts.

AMCC Introduces Industry's First Silicon Germanium 68 x 69Differential Crosspoint Switch with over 200 Gbps SwitchingCapacity

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POS/ATM SONET Mapper


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pp

Single chip OC-48c SONET/SDH Mapper with integratedserializer / deserializer, integrated clock recovery (CDR),clock synthesis (CSU)Highly integrated HBT and

ASIC methodology1.2M CMOS devices6K SiGe HBTsDie size 10.84x10.84 mm 2

65 percent reduction inboard real estate comparedto existing solutions

3.3V technology with 3.4Wof typical power

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Outline - Introduction


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Total Technology SolutionSiGe BiCMOS production circuits

Summary

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Summary


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SiGe HBT BiCMOS is integrated into a wide rangemainstream products today

Key differentiators for the SiGe HBThigh integration : HBT count and CMOS

power, linearity, noiseVolume products in wired, wireless, storage, test andother applications

Two generations of SiGe BiCMOS in production

Highly integrated parts with > 1.6 M FETs, 150K HBTsRoadmap to continuous improvements

Passives and interonnect improvements are central

Models and Design Kits -> tools for circuit designersAccurate statistical models across T, Freq., BiasRobust design platforms with state of the art point tools

GGF 12/8/99

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