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H. Huang Transparency No.5-1
The 68HC11 Microcontroller
Chapter 5: Operation Modes and Memory Expansion
The 68HC11 Microcontroller
Han-Way Huang
Minnesota State University, Mankato
H. Huang Transparency No.5-2
The 68HC11 Microcontroller
The 68HC11 Operation Modes
- Single chip mode: a mode in which the 68HC11 functions without external addressand data buses. The 68HC11 has 5 I/O ports (A, B, C, D, and E) to use in this mode.
- Expanded mode: a mode in which the 68HC11 has the capability to access a 64KBaddress space. In this mode, port B is used as the upper address signals (A15-A8) and port C is used as time-multiplexed address/data bus (A7/D7-A0/D0). Only threeI/O ports are available for direct use.
- Special test mode: mainly used by Motorola in fabrication testing.- Special Bootstrap mode: a mode in which a bootstrap ROM is enabled. The
bootstrap ROM contains a loader program that will be executed after the RESET signal is going high and this program will load in a 256-byte program from the SCI subsystem to the on-chip SRAM and then transfer the CPU control to that loaded program.
Establishment of the operation mode
On the rising edge of the RESET, the voltage levels on pins MODA and MODB are latched into the HPRIO register, which determines the operation mode of the 68HC11.
H. Huang Transparency No.5-3
The 68HC11 Microcontroller
Memory Technologies and Terminology
1. Nonvolatile and volatile memories: differentiated by whether a memory
component will lose its contents when the power is removed.
2. ROMs and RAMs: differentiated by whether a a memory component can be
read/write from/into for roughly the same amount of time.
3. Dynamic and Static RAMs: differentiated by whether a RAM requires periodic
refresh operation in order to maintain its stored information.
4. Memory capacity: the total number of bits that a memory chip contains.
5. Memory organization: describes the number of bits that can be accessed from a
memory chip in one operation. The organization is specified as m n, where m
is the total number of locations and n is the number of bits in each location.
H. Huang Transparency No.5-4
The 68HC11 Microcontroller
Example 5.1 Using the following memory chips, how many SRAM chips will be needed to build a 512KB, 16-bit memory system for a 16-bit microprocessor?
a. 256K × 1 SRAMb. 256K × 4 SRAMc. 256K × 8 SRAMd. 64K × 8 SRAM
Solution:
a. Sixteen SRAM chips with × 1 organization are needed to construct a 16-bit memory system. 16 256K × 1 chips are required to build a 512KB 16-bit memory system.
b. Four SRAM chips with × 4 organization are needed to construct a 16-bit memory system. Four 256K × 4 SRAM chips are needed to construct a 512 KB 16-bit memory system.
c. Two SRAM chips with × 8 organization are needed to construct a 16-bit memorysystem. Two 256K × 8 SRAM chips are needed to construct a 512 KB 16-bit memory system.
d. Two SRAM chips with × 8 organization are needed to construct a 16-bit memorysystem. Eight 64K × 8 SRAM chips are needed to construct a 512 KB 16-bit memory system.
H. Huang Transparency No.5-5
The 68HC11 Microcontroller
Reposition 68HC11 on-chip SRAM and I/O registers
- The upper four bits of the INIT register reposition the on-chip SRAM to thebeginning of any 4KB page
- The lower four bits of the INIT register reposition the I/O registers to thebeginning of any 4KB page.
- The repositioning of SRAM and I/O registers can only be done within 64 Eclock cycles after reset.
Example 5.2 Reposition the 68HC11 on-chip SRAM to $2000-$20FF and remap I/Oregisters to $3000-$303F.Solution: Set the upper four bits and lower four bits of the INIT register to $2 and$3, respectively.
SRAM equ $20 ; value to remap SRAM to $2000-$20FFIOREG equ $03 ; value to remap I/O registers to $3000-$303Fremap equ SRAM+IOREGINIT equ $1030
ldab #remapstaa INIT…
H. Huang Transparency No.5-6
The 68HC11 Microcontroller
External Memory Expansion Issues
• address space assignment• address decoding• timing consideration
Address space assignment
- only unallocated memory space should be assigned to external memory components
- memory space is often allocated in the unit of 2n KB (n is an integer) for 8-bit microcontrollers
- address decoder can be simplified if memory space is divided into blocks of the same size.
Allocated space for the 68HC11A8
$0000-$00FF: SRAM$1000-$103F: I/O registers$B600-B7FF: EEPROM$E000-$FFFF: ROM
H. Huang Transparency No.5-7
The 68HC11 Microcontroller
Example 5.3 Assign the 68HC11 memory space using a block size of 4KB.Solution: The 64KB memory space can be divided into 16 4KB blocks.
Block number Address range
0123456789
101112131415
$0000-$0FFF$1000-$1FFF$2000-$2FFF$3000-$3FFF$4000-$4FFF$5000-$5FFF$6000-$6FFF$7000-$7FFF$8000-$8FFF$9000-$9FFF$A000-$AFFF$B000-$BFFF$C000-$CFFF$D000-$DFFF$E000-$EFFF$F000-$FFFF
H. Huang Transparency No.5-8
The 68HC11 Microcontroller
Example 5.4 Assign the 68HC11 memory space using a block size of 8KB.Solution: The 64 KB space can be divided into eight 8KB blocks.
Block number Address range
01234567
$0000-$1FFF$2000-$3FFF$4000-$5FFF$6000-$7FFF$8000-$9FFF$A000-$BFFF$C000-$DFFF$E000-$FFFF
Address decoding methods
- partial-decoding: each addressable location responds to more than one address on the system bus
- full-decoding: each addressable location responds only to one specific address on the system bus
H. Huang Transparency No.5-9
The 68HC11 Microcontroller
TTL Decoder Chips
- 74138: a 3-to-8 decoder- 74139: dual 2-to-4 decoder
O0O1O2O3
O4O5O6O7
E1
E2
E3
A2
A1
A0
74138
1Y0
1Y11Y21Y3
E1
A1
A0
E2
B1
B0
74139 2Y0
2Y12Y22Y3
Figure 5.1 The 74138 and 74139 decoder chips
H. Huang Transparency No.5-10
The 68HC11 Microcontroller
Example 5.5 Use a full decoding scheme to design an address decoder for a computer that has the following address space assignments:
SRAM1: $2000-$3FFFROM1: $4000-$5FFFE2PROM: $6000-$7FFFSRAM2: $A000-$BFFFROM2: $C000-$DFFF
Solution: Each memory component is 8KB. A 3-to-8 decoder 74LS138 can be used asthe address decoder. The highest 3 address bits will be used as the address inputs to thedecoder.
The highest three address bitsfor each component are:
SRAM1: 001ROM1: 010E2PROM: 011SRAM2: 101ROM2: 110
The decoder circuit is:
O0O1O2O3
O4O5O6O7
E1
E2
E3
A2
A1
A0
74LS138
Figure 5.2 Address decoder design for Example 5.5
A15
A14
A13
SRAM1_CSROM1_CSEEPROM_CS
SRAM2_CS
ROM2_CS
E
H. Huang Transparency No.5-11
The 68HC11 Microcontroller
Example 5.6 Design an address decoder for a 68HC11-based product that has 2KB ofexternal E2PROM and 2KB of external SRAM using partial decoding method.Solution:
- Use the dual 2-to-4 decoder 74139 as the address decoder. - Divide the 64KB address space of the 68HC11 into four 16 KB blocks. - Use the two highest address signals A15A14 as the address inputs to the decoder.
- Assign the address space $4000-$7FFF to E2PROM.- Assign the address space $8000-$BFFF to SRAM.
unused
EEPROM_CS
SRAM_CS
unused
1Y0
1Y1
1Y2
1Y3
E1
A1
A0
A15
A14
E
74LS139
Figure 5.3 Address decoder for Example 5.6
H. Huang Transparency No.5-12
The 68HC11 Microcontroller
Example 5.7 Make space assignment for an 8-bit microcontroller-based systemwith 2 external 8KB SRAM chips, 2 8KB EPROM chips, 1 8KB flash memory chip,and 8 I/O devices. After making space assignment, design a decoder for it.Solution: Use a two-level space assignment and two 74138 to perform addressingdecoding. The level one and level two space assignments are:
(a) Level-one memory space assignment
Block number Address range Assigned to
01234567
0000H~1FFFH2000H~3FFFH4000H~5FFFH6000H~7FFFH8000H~9FFFHA000H~BFFFHC000H~DFFFHE000H~FFFFH
not assignedEPROM2I/Osflash memorySRAM1SRAM2not assignedEPROM1
(b) Level-two memory space assignment
Block number Address range Assigned to
01234567
4000H~43FFH4400H~47FFH4800H~4BFFH4C00H~4FFFH5000H~53FFH5400H~57FFH5800H~5BFFH5C00H~5FFFH
I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7I/O 8
Table 5.5 Two-level memory space assignment for Example 5.7
H. Huang Transparency No.5-13
The 68HC11 Microcontroller
The decoding circuitry is as follows:
O1
O2
O3
O4
O5
O6
O0
O7
V CC
E3
E2
E1
A2
A1A0
74138
O1
O2
O3
O4
O5
O6
O0
O7
V CC
E3
E2
E1
A2
A1A0
74138
EPROM1_CS
EPROM2_CS
SRAM1_CS
SRAM2_CS
not used
not used
A12A11A10
I/O1_CS
I/O2_CS
I/O3_CS
I/O4_CS
I/O5_CS
I/O6_CSA15
A14A13
ALE
Figure 5.4 An example of two-level decoding
flash_CS
I/O7_CS
I/O8_CS
H. Huang Transparency No.5-14
The 68HC11 Microcontroller
Conventions of Timing Diagrams
- Ideal signals have 0 rise and fall times
- A real signal has nonzero rise and fall times
1
0
Figure 5.5 Ideal logic level
90% V DD
10% V DD
1
0
t rise t fall
Figure 5.6 Real signal
H. Huang Transparency No.5-15
The 68HC11 Microcontroller
- Normal signal representation
- Unknown signals (when they are changing) representation
Figure 5.7 Single-signal waveform
1
0
1
0
Figure 5.8 Multiple-signal waveform
(a) Single signal
unknown
unknown
(b) multiple signals
Figure 5.9 Unknown signals
H. Huang Transparency No.5-16
The 68HC11 Microcontroller
Floating signal representation
- A floating signal is represented by a level half way between logic high and low.
Signalfloating
(a) Single signal
Signalsfloating
(b) multiple signals
Figure 5.10 Floating signals
H. Huang Transparency No.5-17
The 68HC11 Microcontroller
Signal causal relationships
signal A
signal B
(a) single cause and single result
Signal A
Signal B
Signal C
Signal D
(b) multiple causes and single result
Signal A
signal B
Signal C
(c) single cause and multiple results
Signal A
Signal B
Signal C
Signal D
(d) multiple causes and multiple results
Causes
Cause
Results
Causes
Results
Result
Cause
Result
Figure 5.11 Causal relationships between signals
H. Huang Transparency No.5-18
The 68HC11 Microcontroller
The 68HC11 Bus Cycle Timing Diagrams
- A 68HC11 external bus cycle can only be performed in expanded mode and controlledby the E clock signal.
- All read and write bus cycles take one E clock cycles to complete.- All timing parameters use 20% and 70% of the power supply voltage as reference points.
(Motorola is using this convention)- Most timing parameters are measured relative to the rising and falling edges of the
E clock signal.- The phrase before the rising edge of the E clock uses the time when the magnitude of
the E clock signal is 0.2VDD as a reference point.
- The phrase after the rising edge of the E clock uses the time when the magnitude ofthe E clock signal is 0.7VDD as a reference point.
- The phrase before the falling edge of the E clock uses the time when the magnitude ofthe E clock signal is 0.7VDD as a reference point.
- The phrase after the falling edge of the E clock uses the time when the magnitude ofthe E clock signal is 0.2VDD as a reference point.
H. Huang Transparency No.5-19
The 68HC11 Microcontroller
PW ELPW EH
tcyc
t r
t f
E
R/W
A15-A8
tMAD
tASL
PW ASHtASD tASED
A7/D7-A0/D0 ADDRESS DATA
tAVM tACCA
tACCE tDSR
tDHR
tAH
tAH
tAV
AS
Figure 5.12 MC68HC11 read bus cycle timing diagram
MC68HC11 Read Bus Cycle Timing Diagram
H. Huang Transparency No.5-20
The 68HC11 Microcontroller
For the 2 MHz E clock signal and the 68HC11 read bus cycle timing diagram
- PWEL is the E clock low pulse width (227 ns)- PWEH is the E clock high pulse width (222 ns)- A15-A8 and R/W signals are valid tAV (94ns) before the rising edge of E clock- A15-A8 and R/W signal remain valid for tAH (30 ns) after the falling edge of E
clock- A7-A0 and D7-D0 are multiplexed on the same PC7-PC0 pins- PC7-PC0 are used as A7-A0 when E clock is low- PC7-PC0 are used as D7-D0 when E clock is high- A7-A0 are valid tAVM (86 ns) before the rising edge of E clock- Read data must be valid for tDSR (30 ns) before the falling edge of E clock so that 68HC11 can read it correctly- Read data must remain valid for tDHR (0-83ns) after the falling edge of E clock so
that 68HC11 can read it correctly- The falling edge of the AS signal is often used by the address latch to latch A7-A0
and A7-A0 remain valid for tAHL (26 ns) after AS falls- Multiplexed address delay is tMAD (83 ns) after the falling edge of E clock.
H. Huang Transparency No.5-21
The 68HC11 Microcontroller
PW ELPW EH
tcyc
t r
t f
E
R/W
A15-A8
tMAD
tASL
PW ASHtASD tASED
A7/D7-A0/D0 ADDRESS DATA
tAVM tDHW
tAH
tAV
AS
Figure 5.13 MC68HC11 write bus cycle timing diagram
tAHL
tDDW
68HC11 Write Bus Cycle Timing Diagram
H. Huang Transparency No.5-22
The 68HC11 Microcontroller
For the 2 MHz E clock and the 68HC11 Write bus cycle timing diagram, most signals are identical to those in read bus cycle timing diagram except
- the 68HC11 drives the data bus when E clock is high- the 68HC11 drives D7-D0 tDDW (128 ns) after the rising edge of the E clock until
tDHW (33 ns) after the falling edge of the E clock
H. Huang Transparency No.5-23
The 68HC11 Microcontroller
Adding an 8KB SRAM HM6264A to the 68HC11
- The HM6264A has 13 address pins to address each of the 8192 locations on the chip.- The HM6264A uses × 8 organization.- There are two chip enable signals: one (CS1) is active low, the other (CS2) is active
high. - The active low signals WE and OE control the data in and out from the chip.
NC
A12A7
A6
A5A4
A3
A2
A1
A0I/O1
I/O2
I/O3V SS
V CC
WE
CS2
A8A9A11
OE
A10
CS1
I/O8I/O7
I/O6
I/O5
I/O4
Figure 5.14 Hitachi HM6264A pin assignment
H. Huang Transparency No.5-24
The 68HC11 Microcontroller
The HM6264A Read Cycle Timing Diagrams
There are four access times:
1. Address access time (tAA)2. CS1 access time (tCO1)3. CS2 access time (tCO2)4. OE access time (tOE)
tRC
tAA
tOLZ
tOE
tLZ2
tCO2
tCO1tLZ1
Address
CS1
CS2
OE
D OUT
tHZ1
tHZ2
tOHZ
tOH
Data valid
Figure 5.15 HM6264A read cycle timing diagram
H. Huang Transparency No.5-25
The 68HC11 Microcontroller
HM6264A Write Cycle Timing diagram
- Write data must be valid for tDW before WE goes highand remain valid for at least tDH after WE goes high
- the pulse width of WE must be at least tWP
Address
CS1
CS2
WE
D IN
D OUT
tWC
tAW
tCW
tCW
tWR
tWP
tDW tDH
tOW
tWHZ
tAS
Figure 5.16 HM6264A write cycle timing diagram (OE low)
H. Huang Transparency No.5-26
The 68HC11 Microcontroller
Interfacing the HM6264A-12 with the 2 MHz 68HC11
- Address space assigned to the HM6264A-12 is $4000-$5FFF- The 74F138, having a propagation delay of 8 ns, is used as the address decoder- The 74F373, having a propagation delay of 11.5 ns, is used as the low address
latch- The WE signal is generated by NANDing the E clock and the inverting copy of
R/W.- The NAND gate has a propagation delay of 15 ns.- The inverter that is used to invert the R/W signal has a propagation delay of 15 ns- The circuit connection is in Figure 5.17 of the next slide
H. Huang Transparency No.5-27
The 68HC11 Microcontroller
A2
A1
A0
E3
E2 E1
PB7/A15
PB6/A14
PB5/A13
E
R/W
PB4/A12 - PB0/A8
AS
AD7-AD0
LE
D7-D0
O7-O0
OE
I/O8 - I/O1
WE
CS1 CS2
V DD
O2
A12-A0
OE
HM6264A
Figure 5.17 Interfacing an 8KB HM6264A to the 68HC11
74F138
68HC11
74F373
74LS00
74LS04
H. Huang Transparency No.5-28
The 68HC11 Microcontroller
Read Access Timing Analysis
- Timing verification is illustrated using an overlapped 68HC11 and HM6264A timing diagram in Figure 5.18.
- The time when the data outputs from the HM6264A become valid is determined by thelast asserted input signal -- CS1 in this example
- A15-A8 are valid 94 ns before E rises- A7-A0 are latched into the 74F373 at 41.5 ns before the rising edge of E clock
The lower address signals A7-A0 are latched by the AS signalThe AS signal falls to 0.7 VDD at 53 ns before the rising edge of E clockThe 74F373 has a propagation of 11.5 nsA7-A0 is valid at 41.5 ns (53 - 11.5) before E rises
- WE is high for a read cycle- E3 is the last asserted input signal for 74F138 and hence dictates the output valid time- O2 is asserted 8 ns after the rising edge of E clock- Data output from the HM6264A is valid 128 ns after the rising edge of the E clock or 94 ns
(222 - 128) before the rising edge of the E clock -- this satisfies the 68HC11 read data setuptime (30 ns)
H. Huang Transparency No.5-29
The 68HC11 Microcontroller
94 ns120 ns8-48 ns
0-40 ns
8 ns
0-83 ns30 ns
E
R/W
A15-A8
AD7-AD0
AS
A12-A0
CS1
CS2
OE
WE
I/O8 - I/O0
0
1
1
HM6264A-12timing
Figure 5.18 Overlapped 68HC11 and HM6264A-12 read timing diagrams
227 ns
222 ns
11.5 ns41.5 ns
8 ns
68HC11timing
A7 - A0 D7 - D0
H. Huang Transparency No.5-30
The 68HC11 Microcontroller
- The data hold time is the smaller one (8ns - 43ns) of the following two values:
1. The output hold time from address change (tOH = 10 ns). Address inputs become invalid 33 ns after the E clock falls. Therefore, it holds up to 43 ns after E falls.
2. Chip selection CS1 to output in high impedance time tHZ1: 8 - 48 ns.
- The data hold time requirement (0 to 83 ns) is violated. However, the data is held valid by the capacitance of the printed circuit board until other component drives the multiplexed address/data bus -- the earliest time is 138 ns after the falling edge of the E clock (or 53 ns before the rising edge of the next E clock cycle).
- Both the read data setup and hold times are satisfied for the 68HC11.
- The analysis about the PCB capacitance holds data valid follows:
H. Huang Transparency No.5-31
The 68HC11 Microcontroller
Analysis on the duration of the data holding time by PCB capacitance
- Each data pin (D7-D0) and the PCB ground plane form a capacitor- After memory chip stops driving data pins, the charge across the capacitor leaks away via
1. input leakage current into the 68HC11 data pin (on the order of 10 A)2. input leakage current into the memory chip (on the order of 2 A)3. other leakage paths on the printed circuit board
- Let
V = voltage change required for a data bus signal to change from 1 to 0 and is 2.5V for a 5V power supply
t = the time that it takes the voltage across the capacitor to drop by VI = total leakage currentC = the capacitance on the PCB. C is 20 pF/ft for a typical PCB
Assume the data bus signal path is 1 foot long
Then t = CV ÷ I = 20 pF × 2.5 V ÷ 12 A = 4 s
Even if the leakage current is ten times larger, the PCB capacitance can still hold the data for up to 400 ns.
H. Huang Transparency No.5-32
The 68HC11 Microcontroller
Write Bus Cycle Timing Analysis
- Timing verification is illustrated using an overlapped 68HC11 and HM6264A timing diagram in Figure 5.19.
- The following timing parameters must be satisfied:
1. write cycle time (120 ns min.)2. write pulse width (70 ns min.)3. address setup time (0 ns min.)4. address valid to end of write (85 ns min.)5. data valid to end of write (50 ns min.)6. data hold time (0 ns min.)7. write recovery time (0 ns min.)
H. Huang Transparency No.5-33
The 68HC11 Microcontroller
227 ns
53 ns
11.5 ns
41.5 ns
56.5 ns
8 ns
E
R/W
A15-A8
AD7-AD0
AS
A12-A0
WE
CS1
CS2 1
OE 0
I/O8-I/O0
Figure 5.19 Overlapped 68HC11 and HM6264A-12 write cycle timing diagram
128 ns
50 ns0 ns
8 ns
25 ns
222 ns
109 ns 18 ns
33 ns
33 ns
D7-D0
336.5 ns
15 ns
222 ns
required
HM6264A-12timing
68HC11timing
2-MHz
H. Huang Transparency No.5-34
The 68HC11 Microcontroller
Calculation of Write Cycle Time
Write cycle time is the period during which the address inputs to the HM6264A are valid andis equal to the sum of the following parameters:
- Address inputs (A12-A0) to the HM6264A valid time before the rising edge of the E clock (A7-A0 become valid later than A12-A8).- E clock rise time (20 ns at 2 MHz)- Pulse width when the E clock is high- E clock fall time- Address inputs hold time after the E clock falls (33 ns). (A12-A8 become invalid earlier
than A7-A0).
tWC = 41.5 ns + tr + PWEH + tf + tAH = 336.5 ns (120 ns min. required)
94 ns
41.5 ns
PW EHt r t f
33 ns
174 ns
Write cycle time
E
A12-A8
A7-A0
Figure 5.20 Calculation of write cycle time
H. Huang Transparency No.5-35
The 68HC11 Microcontroller
Calculation of Write Pulse Width (WE)
Since the WE signal is the NAND function of the R/W and E clock, the width is equal to the high pulse width of the E clock and is equal to 222 ns (70 ns is required).
H. Huang Transparency No.5-36
The 68HC11 Microcontroller
Calculation of Address Setup Time
The address setup time is measured from the moment that all address inputs are valid untilthe write enable signal goes low. A12-A8 become valid 94 ns before the rising edge of Eclock and A7-A0 become valid 41.5 ns before the rising edge of the E clock. The WE signalbecomes valid 15 ns after the rising edge of the E clock due to the propagation delay of the NAND gate. The address setup time is calculated as follows:
tAS = 41.5 ns + tr + 15 ns = 76.5 ns
The calculated value satisfies the requirement (0 ns min.).
15 ns
t r
41.5 ns
Addresssetup time
E
WE
A12-A0
Figure 5.21 Calculation of the address setup time
H. Huang Transparency No.5-37
The 68HC11 Microcontroller
Time from Address Valid till the End of Write
This parameter is measured from the moment when all address inputs are valid until the writeenable signal becomes invalid. This parameter is the sum of the following terms:
1. the lead time from address signals become valid to the rising edge of the E clock (41.5 ns)2. the E clock rise time (20 ns)3. the E clock high pulse width (222 ns)4. the E clock fall time (20 ns)5. the propagation delay of the NAND gate (15 ns)
tAW = 41.5 ns + 20 ns + 222 ns + 20 ns + 15 ns = 318.5 ns (85 ns min. required)
E
WE
A12-A0
Address valid to end of write
PW EH t f
15 ns
41.5 ns
Figure 5.22 Calculation of address valid to end of write
H. Huang Transparency No.5-38
The 68HC11 Microcontroller
Calculation of Write Data Setup Times
The write data setup time (tDW) is measured from the moment that the 68HC11 drives the data on the data bus until the WE signal goes high (50 ns min. required).
tDW = PWEH - t DDW + delay of the NAND gate = 222 ns - 128 ns + 15 ns = 109 ns
ED7-D0
WE
tDDW
write datasetup time
15 ns
222 ns
H. Huang Transparency No.5-39
The 68HC11 Microcontroller
Write Data Hold Time (tDH)Calculation
- tDH is measured from the moment when WE becomes invalid until D7-D0 become invalid.
tDH = tDHW - NAND delay = 33 ns - 15 ns = 18 ns (> 0 ns)
15 ns
tDHW = 33 ns
tDH
E
WE
D7-D0
H. Huang Transparency No.5-40
The 68HC11 Microcontroller
Calculation of Write Recovery Time
Write recovery time (tWR) is measured from the moment that the earliest chip select signal (CS1 in this example) becomes invalid until the moment that the address signals are invalid. The calculation of tWR is illustrated in Figure 5.23.
All timing parameters have been verified to satisfy the requirements.
E
CS1
A12-A0
Write recoverytime
33 ns
8 ns
Figure 5.23 Calculation of write recovery time