GSM BTS Development

&

GSM/EDGE Receiver based on FDE

Dinakar. P

dinakarp@tenet.res.in

Dept. of Electrical Engineering

Indian Institute of Technology - Madras

ComNet - 2007

Introduction: GSM

Based on FDD – TDMA

Raw bit rate: 270.83 kbps

Each physical channel is shared (TDMA) by 8 users

Data service: HSCSD (Circuit-Switched) & GPRS (Packet-Switched)

Global System for Mobile Communication (GSM)

Air Interface

Currently ~ 670 networks in 213 countries and territories

Frequency bands (MHz) – 450, 850, 900, 1800, 1900

Very rapid growth in subscribers (1275M-2/05, 1600M-12/05, 2000M-12/06)

Aggressive evolution to 3G – EDGE, Wideband CDMA

GSM Cellular Network

GSM BTS Specification

Single TRX (Single carrier)

Low power

Supports multiple bands – GSM 900, 1800 and 1900

Standard compliant

Remote monitoring capability

Low cost

Base Station Unit

RF SectionBaseband

Section

Processor

Section

POE

BSC Antenna

GSM Receiver - Equalizer

GSM Receiver – Equalizer…Cont

MLSE based receiver

Generates soft-bit (SOVA)

Implemented on DSP

Processor loading: ~60 % (MIPS)

Standards compliant

Transparent to GPRS reception

1 2 3 4 5 6 7 8

GSM TDMA frame

4.615 ms

GSM time-slot (normal burst)

577 µs

guard

spacetail user data TrainingS S user data tail

3 bits 57 bits 26 bits 57 bits1 1 3

GSM: Time Division Multiple Access

Raw Bit Rate per Slot: 270.8*(114/156)*(12/13)/8 = 22.8 kbps

General Packet Radio Service (GPRS) = 14.4 kbps / Slot

High Speed Circuit-Switched Data (HSCSD) = 64 kbps / 4 Slot

Need higher date rate ? Use higher order modulation !!!

EDGE – Enhanced Data rate for Global Evolution

Enhancement of GPRS is EGPRS and HSCSD is ECSD

Retains GSM characteristics:

Symbol duration

Frame structure

Spectral characteristics

Constellation: GMSK (1bit/sym) and 8PSK (3bit/sym)

Symbol duration: 3.69 μS. Delay Spread as high as 17 μS

Memory Length (L):5 No. of State in MLSE: GSM – 2L (32) EDGE – 8L (32768)

** Number of Channel Taps: L + 1

Traditional GSM Equalizer: MLSE

Evolution of GSM: EDGE

Is Frequency Domain Equalization Techniques are feasible for EDGE ?

Delay Decision Feedback Sequence Estimation (DDFSE)

Reduced-State Sequence Estimation (RSSE)

DFE combined with nearest-neighbor symbol perturbation

Turbo Equalization with a core low complexity equalizer

Equalizers like MAP-DFE, Zero-forcing filter . . .

Traditional Equalization Techniques:

Equalization Techniques for EDGE

EDGE: Simulation Model

A quick glance at Frequency Domain Equalization

v samples

CP CP

copy copy

N samples

B l o c k i B l o c k (i+1)

Time-Domain Convolution Frequency-Domain Multiplication

Tail

Symbols

(3)

Tail

Symbols

(3)

Data

Pre-Amble

(58)

Data

Post-Amble

(58)

Training

Sequence

(26)

Unique

Word-1

(3)

Unique

Word - 2

(3)

Data & Training Sequence (58+26+58)

Block (Length N= 145)

(i)

Guard

IntervalGuard

Interval

Interfering Block

(i-1)

IBI Removal and CP Construction

A different look on Burst Structure

BER Performance: Proposed FDE vs MMSE Equalizer

** Ideal Channel Estimation

Static Channel

Tail

Symbols

(3)

Tail

Symbols

(3)

Data

Pre-Amble

(58)

Data

Post-Amble

(58)

Training Sequence

(26)

Efficient Frequency-Domain Equalizer

64-Pt Block 64-Pt Block

• Training Sequence is used as known pattern and the cyclic prefix is

constructed accordingly

• Separate FDE for Post-Amble and Pre-Amble

• Same channel values are used for both the FDE

BER Performance: Full Block FDE and Modified 64 Pt FDE

** Ideal Channel Estimation

Static Channel

Tail

Symbols

(3)

Post-Amble (58)Training Sequence

(26)

64-Pt Block

FDE for longer channels

Equalization of Post-Amble

Cyclic Prefix Reconstruction

FDE for longer channels

Equalization of Pre-Amble

Tail

Symbols

(3)

Tail

Symbols

(3)

Data

Pre-Amble

(58)

Data

Post-Amble

(58)

Training Sequence

(26)

Guard

Interval

Tail

Symbols

(3)

Pre-Amble (58)Training Sequence

(26)

64-Pt Block

BER Performance with proposed CP reconstruction procedure

** Ideal Channel Estimation

Hilly Terrain: Slow fading channel

CP Reconstruction: 2 Iterations

EDGE: System Model

Summary

MIPS Memory

Cycles/ Burst

Mega Cycles/ Second

BF 537

600 MIPSkBytes

BF 537

64 kBytes

Best Case(Shorter Channel)

13622 24 4% 7.4 11%

Worst Case(Longer Channel)

25114 45 8% 7.6 11%

Compared with Time-Domain MMSE – Much better

Implemented on DSP

Standards compliant

Possible enhancement: Over-sampling & receive diversity