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Group 6 Anuj GroverPuneet Sharma. Successfully added two AES core modules into the top level design No syntactic errors found by DC Synthesized the design successfully Clock period = 5ns, all timings met No scan FFs being added to design Cell area reported = 513413.218750. - PowerPoint PPT Presentation
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CSE241 Project updates.1 Cichy, UCSD ©2003
Group 6 Anuj Grover Puneet Sharma
Successfully added two AES core modules into the top level design
No syntactic errors found by DC
Synthesized the design successfully Clock period = 5ns, all timings met
No scan FFs being added to design
Cell area reported = 513413.218750
