Grant WillsonDepartment of Chemical Engineering

Department of ChemistryThe University of Texas

Austin, Texas 78712

http://willson.cm.utexas.edu

Dual Damascene using Step and Flash Imprint Lithography

S-FIL fluid dispenser – 126 ink jet system

Planarization layerSubstrateStep 1: Dispense drops

Step 2: Lower template and fill pattern

Step 3: Polymerize S-FIL fluid with UV exposure

Step 4: Separate template from substrate

Template

Substrate

Substrate

Template Step & Repeat or

whole wafer imprint

SubstratePlanarization layer

Planarization layer

Planarization layer

Photomask 6025 template, coated with release layer

Step and Flash Imprint Lithography

Template filling driven by capillary action – low imprint pressure and room temperature process

Template

The First SFIL Tool

“Step and Flash Imprint Lithography: A New Approach to High-Resolution Patterning,” Proc. SPIE 3676 379-389 (1999)

SFIL tool today

Resolution:  Sub-32 nanometer half pitch Alignment:  < 10nm, 3 sigma (single point, X,Y) Automation:  Fully automated wafer and mask loadingFlexibility:   200mm and 300mm substrates (SEMI standard) Field size:   26mm x 32mm (step-and-scan compatible)

Resolution of Imprint Lithography2nm Replication

(Rogers et al, Illinois)

20nm Replication

25nm vias

22nm logic (M1)

SFILSFIL

~130 atoms wide

Imprints from the Imprio 250

32nm Logic

32nm half-pitch 24nm half-pitch

32nm Metal 1 25nm Contacts

22nm half-pitch

Thanks to Toshiba

38 nm HP

Flash Memory Imprints Thanks to Samsung

Non-CMOS Applications

Photonic Crystals

Patterned

Media

100nm 20 nm

Multitiered Templates

Fabricated with alternating layers of ITO and PECVD Oxide

S. Johnson, et.al. Microelectron. Eng. (2003) 67, 221

SFIL Imprint

Our Job!

Moore

You?

Egyptian Damascene

ATDF Dual Damascene Processresist

etch stop

substrate

ILD

ILD

initial stack trench litho trench etch

resist ashBARC / resistvia litho

via etch resist Ash plate

CMP

23 unit process steps/layer =184 steps for 8 layers of metal

Direct Etch or Direct Imprint

Previous Metal Layer

Dielectric Layer

Sacrificial Imprint Material

Imprint Template

SIM

Previous Metal Layer

Imprint Template

DPD

DirectlyPatternableDielectric

SIM Process DPD Process

SIM Damascene Process

M1

Copper Barrier

# of process steps: 0

◄ CVD ILD

12SFIL IMPRINT

PressFlashRelease

◄ Dispense SIM◄ Cured SIM

Multi-Tier Template

3

3

SIM Damascene Process

M1

# of process steps: 4

Etch transfer

56x 8

64

184 – 64 = 120steps

Savings of

7

Barrier EtchCopper SeedCopper PlateCMP

8

BEOL Multilevel Imprint Cost Saving

20% overall wafer cost saving at 30 wph Cost analysis by Sergei V. Postnikov, Infineon Technologies;

presented at Semicon Europa 2007, Stuttgart, Germany

0%

20%

40%

60%

80%

100%

120%

140%

wph = 5 wph = 10 wph = 20 wph = 30 wph = 40 wph = 50

V1/M2base line

DD:44steps

V1/M2 Dual Damascene by NIL in resist: 27 steps

rela

tiv

e c

os

t (%

)

20%

Lloyd Litt, et. Al NNT 08

Multi-level Templates

Vias

Lines

240 nm

360 nm

120 nm

125 nm

Features HeightCD

1 μm vias

Vias

Lines

125 nm

313 nm

50 nm

125 nm

Features HeightCD

Courtesy of Toppan Photomask

Courtesy of IMS Chips

Multi-Level S-FIL Test Vehicle

M2 by SFIL M1 by Photolithography

IN OUT

Dummy lines

IN OUT

Dummy lines

Comb

CombSerpIN Serp

OUTComb

CombSerpIN Serp

OUT

Serp/CombSerp/Comb

Dense LinesDense LinesVia ChainsVia Chains

IN OUTIN OUT

Isolated LinesIsolated Lines

Comb 1

Comb 2

Comb 1

Comb 2

CombCombSerpSerp

IN OUTIN OUT

IN OUT

Dummy lines

IN OUT

Dummy lines

Comb

CombSerpIN Serp

OUTComb

CombSerpIN Serp

OUT

Serp/CombSerp/Comb

Dense LinesDense LinesVia ChainsVia Chains

IN OUTIN OUT

Isolated LinesIsolated Lines

Comb 1

Comb 2

Comb 1

Comb 2

CombCombSerpSerp

IN OUTIN OUT

Test StructuresTest Structures

Via chain

SIM Via Chain StructuresSIM Via Chain Structures

100nm vias 100nm via100nm vias

M2 by SFIL M1 by Photolithography

Via chain

Pattern Transfer Demonstration

TrenchDescum

N2/H2

TrenchDescum

N2/H2

Via EtchAr/C4F8/N 2

Via EtchAr/C4F8/N 2

SIM Material

ILD Material

Pattern Transfer Demonstration

TrenchEtch

CF4/C4F8/N 2

TrenchEtch

CF4/C4F8/N 2

AshN2/H2

AshN2/H2

Both Coral® and Black Diamond® were processed

Via Chain – 120 nm 1000 Contacts

Yield statistics (6 valid and identical chains tested)

• Overall yield of 1000-contact chains with via CD 120 nm (nominal) / 115 nm (final) – 96.83%

• Individual contact yield – 99.9968%

Template CD = 120 nm Final CD = 115 nm

Template CD = 120 nm Final CD = 115 nm

0

20

40

60

80

100

0 2 4 6 8 10 12 14 16

Via Chain Resistance (Ohm per contact)C

um

ula

tive

Pro

bab

ilit

y (%

)

Chain #1

Chain #2

Chain #3

Chain #4

Chain #5

Chain #6

Cu (M2)

CoralCu (M1)

Ta

Directly Patternable Dielectric

Previous Metal Layer

Imprint Template

DPD

DPD Property Requirements

Property

Viscosity

Photocurable

Cure shrinkage

Dielectric Constant

Thermal Stability

Mechanical Properties

CTE

Water Sorption

Requirement

Less than 20 cP

Chain reaction polymerization

Less than 15%

≤ 3

Less than 1% wt loss/hr @

400oC

Young’s Modulus ≥ 4 GPa

Less than 30 ppm/oC

Less than 1% wt

SiOO

O

SiSi

OSi

O

OO

O

O

Sol-gel Design/Formulation

Sol-Gel

SiOO

O

SiOO

O

O

O

Si

O

O

O Si

OH2O, H+

Alkoxysilanes

ultrasonication, vacuum

Sol-gel DPD Characterization

Property

Viscosity

Acrlyate conversion

Vertical shrinkage a

Dielectric Constant

Thermal Stability b

Mechanical Properties c

CTE

Measurement

9-17 cP

93% @ 1.2 J/cm2

~ 30%

≤ 2.3

364 °C

3-7 GPa

23.4 ppm/°Ca. Shrinkage is composite of UV cure bake at 300 °Cb. Measured after bake at 350 °C.c. Measured by both nanoindentation and SAWS.

??

Metal Patterns (via chains) in Sol-gel DPD

Wires (M2)

“Dummy“ metal fill

Via chain

Sol-Gel DPD Integration Study

Defect SourcesM1 defects (not expected)Particle defects (expected)

Imprintuniformityalignmenttemplate

BEOLetchmetalCMP

Sol-Gel Via Chain Yield

120nm Via ChainsPoor Yield

Cause of FailureOpen at via bottom

Co

urt

esy

of

Bro

ok

Ch

ao

O Si O Si

O Si O Si O

O

x

y

x+y=8

O Si O Si

O Si O Si O

O

x

y

x+y=8h

O Si O Si

O Si O Si O

Oy

x+y=8

x

POSS Design/Synthesis for DPD

O

SiO Si

O

SiOSi

O

SiO

Si

O

SiO

SiO O

OO

R

R

R

R

R

R

R

POSS Characterization

a. Measured after bake at 250 °C.b. Measured by both nanoindentation and SAWS.

Property

Viscosity

Exposure

UV shrinkage

Thermal shrinkage a

Dielectric Constant

Thermal Stability a

Mechanical Properties b

CTE

Measurement

~640 cP

89 mJ/cm2 @ 80% conv.

17 ± 4%

5 ± 3%

2.84

344 oC

2-5 GPa ?

32 ppm/oC

Issue: inkjet requires < 20 cP Solution: new viscous fluid dispense

technology is being implemented

Viscous Dispense System

POSS Design/SynthesisPolyhedral Oligomeric Silsesquioxane (POSS)

Si

O

Si

O

O

O

O

Si SiO

SiO

Si

O

Si

O

O

SiO

O

OSi

OSi

OSi

OSi

n

O

O

8-n

Benzocyclobutane(BCB)

(Meth)acrylate

A

B

B

A

B

B B

A

O

O

Pt(dvs), Toluene

O

SiO Si

O

SiOSi

O

SiO

Si

O

SiO

SiO O

OO

O Si O SiH

8

Hydrosilylation chemistry

Conclusions Multi-level S-FIL is a viable approach for Cu /

low-k dual damascene processing

• SIM Process has been demonstrated by good electrical yield in various via and line test structures

• Implementation does not involve reliability testing

• Lower cost DPD Process is making progress• Opportunity for materials design

• Some processing challenges remain

• Implementation of DPD requires reliability testing

Brook H. Chao, Frank Palmieri, Wei-Lun Jen, and D. Hale McMichael

The University of Texas at Austin

Jordan Owens, Rich Berger, Ken Sotoodeh, Bruce Wilks, Joseph Pham, Ronald Carpio,

Ed LaBelle, and Jeff WetzelAdvanced Technology Development Facility, Inc.

These people did the work

These people paid for the work