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CAREER OBJECTIVE To secure a challenging career in ASIC Design and Verification of VLSI Domain, leveraging a strong background in ASIC Verification and work at an organization where I can put my knowledge to best use as well as help in development of the Organization. WORK EXPERIENCE LANGUAGES(HDL/HVL) Verilog, System Verilog, UVM. CAD TOOLS USED Cadence (Encounter), QuestaSim, Xilinx, Tanner PROJECTS DONE Goutam Padhy Mail: [email protected] Phone: +91-8093611841 ADDRESS S/o: Santunu Padhy, ChokadolaCloth Store, Girls High School Road, Paralakhemundi, Gajapati, Orissa, Pin 761200. PERSONAL INFORMATION Fathers Name: Santunu Padhy Sex : Male Marital status: Single DOB: 13 th June 1992 EDUATIONAL EXPERIENCE COLLEGE- (Domain) BOARD- (Score) NIST(B.tech)- ECE BPUT- 7.5/10 JITM +2 SCIENCE(12 th ) CHSE 67% St.Ann,S convent School(10 th ) ICSE-65% DEPARTMENT DESIGNATION PLACE WORK PERIOD VLSI DESIGN AND VERIFICATION ENGINEER(Intern) AsicZen Technology, BBSR(Orisa) 5 th April 2015 - Present ECE(VLSI) Cadence Trainer(Faculty) NIST College, BAM(Orissa) 16 th April 2014 - 30 th March 2015 PROJECT DETAILS MY WORK IN THE PROJECT Arbiter Design and Verification Deign of Arbiter (Verilog). Verify the Arbiter (SV.) Understand the Arbiter specification. A feature list of Arbiter was made. The RTL of Arbiter was made. A verification environment was made for Arbiter in SV. Different test-case was made to test the RTL. The RTL of Arbiter was Verified Later on a UVM environment was made to verify the Arbiter Design UART VERIFICATION IP To make UART verification IP (UVM) Make master and slave UVC (UVM) Connect them and check whether the UART IP is working fine Understand the UART Protocol specification. Architecture of the project was made. A feature list of UART was made. To make master and slave UVC. Verification Plan was made. Different test cases were made according to the feature List. AMBA3_APB To make AMBA3_APB Design(Verilog) To verify AMBA3_APB(SV) Check using Test-Cases Understand the AMBA3_APB Protocol. A feature list of AMBA3_APB was made. The RTL of AMBA3_APB was made. A verification environment was made for AMBA_APB in SV. Different test-cases were made to test the RTL. The RTL was verified. Later on a UVM environment was made to verify the AMBA3_APB Design. Dual Port Ram with Decoder Deign a Dual Port RAM (Verilog). Design a Ram Decoder for the Dual Port Ram. Verify the Deign(SV) Understand the Dual Port Ram specification. A feature list of Dual Port Ram was made. The RTL of Dual Port Ram was made. A verification environment was made for Dual Port Ram in SV. Different test-cases were made to test the RTL. The RTL was verified.

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CAREER OBJECTIVE

To secure a challenging career in ASIC Design and Verification of VLSI Domain,

leveraging a strong background in ASIC Verification and work at an organization

where I can put my knowledge to best use as well as help in development of the

Organization.

WORK EXPERIENCE

LANGUAGES(HDL/HVL)

Verilog, System Verilog, UVM.

CAD TOOLS USED

Cadence (Encounter), QuestaSim, Xilinx, Tanner

PROJECTS DONE

Goutam Padhy

Mail: [email protected] Phone: +91-8093611841

ADDRESS

S/o: Santunu Padhy,

ChokadolaCloth Store,

Girls High School Road,

Paralakhemundi,

Gajapati,

Orissa,

Pin – 761200.

PERSONAL INFORMATION

Fathers Name: Santunu Padhy

Sex : Male

Marital status: Single

DOB: 13th June 1992

EDUATIONAL EXPERIENCE

COLLEGE-

(Domain)

BOARD-

(Score)

NIST(B.tech)-

ECE

BPUT- 7.5/10

JITM +2

SCIENCE(12th)

CHSE – 67%

St.Ann,S convent

School(10th )

ICSE-65%

DEPARTMENT DESIGNATION PLACE WORK PERIOD

VLSI DESIGN AND VERIFICATION ENGINEER(Intern)

AsicZen Technology, BBSR(Orisa)

5th April 2015 - Present

ECE(VLSI) Cadence Trainer(Faculty)

NIST College, BAM(Orissa)

16th April 2014 - 30th March 2015

PROJECT DETAILS MY WORK IN THE PROJECT

Arbiter Design and Verification

Deign of Arbiter (Verilog).

Verify the Arbiter (SV.)

Understand the Arbiter specification.

A feature list of Arbiter was made.

The RTL of Arbiter was made.

A verification environment was made for Arbiter in SV.

Different test-case was made to test the RTL.

The RTL of Arbiter was Verified

Later on a UVM environment was made to verify the Arbiter Design

UART VERIFICATION IP To make UART verification IP

(UVM)

Make master and slave UVC (UVM)

Connect them and check whether the UART IP is working fine

Understand the UART Protocol specification.

Architecture of the project was made.

A feature list of UART was made.

To make master and slave UVC.

Verification Plan was made.

Different test cases were made according to the feature List.

AMBA3_APB To make AMBA3_APB

Design(Verilog)

To verify AMBA3_APB(SV)

Check using Test-Cases

Understand the AMBA3_APB Protocol.

A feature list of AMBA3_APB was made.

The RTL of AMBA3_APB was made.

A verification environment was made for AMBA_APB in SV.

Different test-cases were made to test the RTL.

The RTL was verified.

Later on a UVM environment was made to verify the AMBA3_APB Design.

Dual Port Ram with Decoder Deign a Dual Port RAM (Verilog).

Design a Ram Decoder for the Dual Port Ram.

Verify the Deign(SV)

Understand the Dual Port Ram specification.

A feature list of Dual Port Ram was made.

The RTL of Dual Port Ram was made.

A verification environment was made for Dual Port Ram in SV.

Different test-cases were made to test the RTL.

The RTL was verified.

TECHNICAL WORKSHOP AND TECHFESTS ATTENDED

Attended IEEE workshop for implementation NANO ELECTRONICS IN VLSI.

Workshop on Real Time Embedded System Design for Signal Processing Application –FPGA design Approach.

Techfest – Sampark organized by Odisha Oracle Users Group, Kalinga Institute of Industrial Technology(KIIT), Bhubaneswar

Techfest – Daksha organized by Gandhi Institute of Engineering and

Technology, Gunupur.

Haptic and motion controlled Robot for House Application

To make a Physical arm, which function alike the human Arm.

Make a programmable hardware which can take all the expected work to be done by normal human hands.

The Arm was made of fiber (Low Weight).

Servo motor was used for joints and fingers.

The Arm was made of fiber (Low Weight).

Flex Sensors were used to control the Hand to fingers.

Motion Sensors were used to control the direction of the hand and its motion.

XBEE module was used to communicate to the Human arm to the Robotic hand Control Unit.

The other covering was made of tin and other plastic materials

Design Synchronous FIFO: To design a synchronous FIFO.

To verify the design writing test-cases

Understand the synchronous FIFO specification.

The RTL of synchronous FIFO was made.

A feature list of Arbiter was made.

A verification environment was made for Synchronous FIFO in SV.

Different test-case was made to test the RTL.

The RTL was verified.

Courseware development for open-source magic VLSI tool

To make 40 Hours of Video Lecture on design cycle of Layout tool Using Magic Tool.

It was sponsored by MHRD, IIT Delhi.

Under the Guidance of Dr. Ajit Kumar Panda, Dean at NIST.

This project was to make a 40 Hours tutorial on Magic Tool.

The tool work in the Linux Platform.

So the video, how to Install Ubuntu and use it was made by me.

The editing of all the 40 Videos was made by me in Apple Final Cut Pro.

The videos were so made that the student can watch the video and understand the layout flow of VLSI.

Then all the videos were uploaded to the Website.

Reference: http://www.nist.edu/Projects/NMEICT

Serializer Design and

Verification To make RTL(Verilog)

Verify the Design ( SV)

Understand the Serializer Protocol specification.

Architecture of the project was made.

A feature list of Serializer was made.

To design a RTL for Serializer.

Verification Plan was made.Different test cases were made according to the feature List.

ACHIEVEMENTS

1ST Prize in PSPICE design at GIIT , BERHAMPUR

BEST MENTOR in India Award for the National Level Competition by ROBOTZ INDIA (Publish Twice on News).

1st Position in On-Spot Circuit Designing Contest in IMPULSE 2011 held at APEX, Bhubaneswar.

2nd Position in Automated Robotics in ABHIGYAN 2013 held at GIIT, Berhampur.

2nd Position in Automated Robotics in AAKASH 2012 held at VITAM, Berhampur.

Organizer for IEEE EDA workshop.

3rd Position in State Level Drawing and Painting Competition.

INTERESTS AND HOBBIES

Circuit designing

PCB designing

Dancing

Singing

Painting

Video Editing

Photography

REFERENCE

Mr. Suresh Sadangi Sr. Design Engineer

Broadcom, Bangalore. Ph. No: +91- 9901444399.

Mr. Sujit Kumar Panda,

Vice President,

AsicZen Technology,Orissa

Ph. No: +91 – 9437116441.