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GlueX electronics
Collaboration Meeting
May, 2004
Paul Smith
• 12,500 ADC channels• 8,200 TDC channels
Level 1 Trigger:200 KHz X5 KB/event= 1GB/sec
Digital PipelineDeadtimeless
~$3.5M
Cockcroft-Walton PMT base
Robotic Selective Assembly
QuickTime™ and aH.263 decompressor
are needed to see this picture.
Electronics Review
Andy Lankford (UC Irvine) and Glenn Young (ORNL)at the GlueX Electronics Review - July 23 2003
Single channel FADC prototype
Test bed for::
SPT converter chipXilinx chip and softwareMentor PCB & FPGA softwareIntellectual Property (PCI core)Robotic assembly
JLab TDC Module
“Electronics” View of Trigger/DAQ
Digital PipelineFront End“Digitizer”
FE/DAQInterface
Trigger
AnalogData To ROC
Event BlockBuffers
Every 64-256 events
Every event
Photon Rates
Level 1
Level 3
PhysicsSignal
Software-basedLevel 3 System
Start @ 107 /sOpen and unbiased triggerDesign for 108 /s 15 KHz events to tape
Level 1 trigger systemWith pipeline electronics
Selected Review Conclusions:
• It is important to insure that the requirements on the electronics derive from the physics.
• The requirements and specifications of the analog front-end electronics are not yet adequately defined. This is coupled to the tentative status of some detector designs. The lack of full definition of detector designs may soon limit progress on electronics design,
• The manpower resources shown during the review will be inadequate for developing an electronics system of the scope required by GlueX.
• The decision to standardize all detector readout on a single TDC module design and a single Flash ADC module design is good, and will help simplify the overall electronics system design in a constructive way and conserve valuable engineering resources.
• The Committee feels that it is desirable to locate these modules in a radiation-free area if possible, in order to improve access.
CD-0• 5 years to beam!
BaBar required 100s of engineer-yearsGlueX currently has 2 electronics
engineersKey detector parameters still undefinedFunding profile unknownManagement plan unimplemented
Welcome new collaborators from Alberta and Oak Ridge!
Divide and Conquer
F,B Cal FADCs ~3000 channels8 Bits, 250 MSPSEnergy Sum for Level 1
dE/dX FADCs~3400 channels125/250 MSPS?8 Bit log vs 10/12 Bit linear
FDC cath FADCs~6000 channels62.5 MSPS?Positive input polarity
BCal FEPhotodetector, discriminator
TOF FEHV, discriminator
Tracking FE
Level 1 Trigger Clock/Sync/CalibTDCs
~8200 channels
Vertex Tracking TaggerHV, discriminator
Active Collimator
At least one engineer per sub-system:
FADC price/performance space
250 MSPS 125 MSPS 62.5 MSPS
8 bits SPT7721 $20 AD9289 $11 / 4 channel chip
10 bits MAX1124 $50MAX1122 $37
AD9411 $42
ADS5122 $43 / 8 channel chip
ADS5277 $40 / 8 channel chip
12 bits
AD9226 $20
LTC1741 $13
ADS5221 $14
ADS5273 $65 / 8 channel chip
14 bits AD5500 $95LTC1742 $25
ADS5422 $31
Next (final?) version of FCAL FADC6U
FADC
Clock/Sync
XilinxV2PRO
PIC
MG
2.1
6
SmallXilinx
Energy sum
Ethernet
Buy FADCs?
Gage
LeCroy
Acqiris Struck