GLAST LAT ProjectPDU/GASU MRR, February 3, 2005 4.1.7 DAQ & FSWV1 1 GLAST Large Area Telescope: B. Estey, G. Haller SLAC xxxx LAT Quality Engineer [email protected]

GLAST LAT Project PDU/GASU MRR, February 3, 2005

4.1.7 DAQ & FSW V1 1

GLAST Large Area Telescope:GLAST Large Area Telescope:

B. Estey, G. HallerSLACxxxxLAT Quality Engineer

[email protected](650) [email protected](650) 926-8531

Gamma-ray Large Gamma-ray Large Area Space Area Space TelescopeTelescope

PDU & GASU Manufacturing PDU & GASU Manufacturing Readiness Review (MRR)Readiness Review (MRR)


4.1.7 DAQ & FSW V1 2

ContentsContents

• Presentation I (G. Haller)

– DPU & GASU Module Description

– Changes since CDR

– Design and Test Documentation

– Engineering Module Validation

• Presentation II (B. Estey)

– Parts, Materials & Processes

– Procurement Status

– Manufacturing Facilities

– Manufacturing Flow Plan

– Quality Assurance Plan

– Configuration Management

– Manufacturing Issues/Concerns

• Presentation III (xxxxx)

– Quality Assurance Plan


4.1.7 DAQ & FSW V1 3

GLAST Large Area Telescope:GLAST Large Area Telescope:

G. HallerSLAC

[email protected](650) 926-4257

Gamma-ray Large Gamma-ray Large Area Space Area Space TelescopeTelescope

PDU & GASU MRR Part I PDU & GASU MRR Part I


4.1.7 DAQ & FSW V1 4

LAT ElectronicsLAT Electronics

3 Event-Processor Units (EPU) (2 + 1 spare)

– Event processing CPU– LAT Communication Board– SIB

ACD

empty

EPU-3

EPU-2EPU-1

empty empty

Power Dist. Unit*

GASU*

empty

empty

SIU*SIU*

Spacecraft Interface Units (SIU)*

– Storage Interface Board (SIB): Spacecraft interface, control & telemetry

– LAT control CPU– LAT Communication

Board (LCB): LAT command and data interface

16 Tower Electronics Modules & Tower Power Supplies

* Primary & Secondary Units shown in one chassis

Power-Distribution Unit (PDU)*

– Spacecraft interface, power

– LAT power distribution

– LAT health monitoring

Global-Trigger/ACD-EM/Signal-Distribution Unit*

TKR

CAL

TKR Front-End Electronics (MCM)ACD Front-End Electronics (FREE)

CAL Front-End Electronics (AFEE)


4.1.7 DAQ & FSW V1 5

PDU & GASU Mounted on LAT PDU & GASU Mounted on LAT

Show picture of PDU and GASU on test-bed

TEM

TPS

CAL


4.1.7 DAQ & FSW V1 6

EM PDU enclosure with primary/redundant PDU circuit cards, no coating/staking

• Primary and Redundant Circuits in one Enclosure– Receives Primary and Redundant 28-V from spacecraft– Each, primary and redundant DPU can select between

primary and redundant spacecraft power– Filters 28V– Turns on/off 28V to 16 towers and 3 EPU’s under

program control– Protects PDU and down-stream circuits from over-

current and under-voltage situatations• Over-current via poly-switches• Under-voltage via custom circuit in each power-

on branch – Receives command/clock from GASU– Digitizes voltaes/temperatures from > 150 sources

• Includes temperatures from radiators, GRID used for thermal control

– Reads back data to SIU via GASU– Provides PDU DAQ voltage and temperature analog

data to spacecraft for monitoring

Power Distribution Module (PDU)Power Distribution Module (PDU)


4.1.7 DAQ & FSW V1 7

EM PDU enclosure with primary/redundant PDU circuit cards, no coating/staking

• Primary and Redundant Circuits in one Enclosure– Contains two types of circuit card assemblies

• GASU Power Supply CCA• GASU DAQ Board CCA

– GASU Power Supply• Receives 28-V supply voltages for

– Primary and redundant DAQ board, generates 3.3V and 2.5v

• ACD power-switch circuit for ACD FREE cards– Filtering

– GASU DAQ Board• Contains 9 FPGA’s• Includes Command Response Unit, Fan-out and

fan-in of commanding to 16 TEMs, PDU, EPU’s, ACD

• Includes Global Trigger Logic• Includes LAT Event-Builder Logic• Includes command/control/read-back for ACD

sub-system• Includes power-control for ACD FREE Boards

GASUGASU


4.1.7 DAQ & FSW V1 8

Changes since CDRChanges since CDR

• PDU– Creation/Modification of PDU FPGA code – Power-on circuit was modified to include under-voltage

shut-off to protect MOS power-on switches– In-rush current limits modified to loads

• GASU– Code in 9 FPGA’s were modifed/finalized and bugs fixed– ACD power-on low-frequency system clock selection added– ACD power circuits replaced with circuit to protect for over-

current and updated ICD interface voltage/current requirements


4.1.7 DAQ & FSW V1 9

Peer Review RFA StatusPeer Review RFA Status

• Are there any?


4.1.7 DAQ & FSW V1 10

PDU (replace spread-sheet below)PDU (replace spread-sheet below)

Tower Electronics ModuleLAT-DS-01481-04 Assembly, Tower Electronics Module Signed OffLAT-PS-02615-02 Statement of Work, TEM Assy Signed OffLAT-SS-00288-01 Specification, TEM Assembly Signed OffLAT-TD-03415-01 Test Procedure, TEM LPT Signed OffLAT-TD-03875-01 Electrical Interface Continuity and Isolation Test, TEM Pending Sign-OffLAT-TD-04097-01 TEM Interface Verification Test Pending Sign-OffLAT-TD-03831-01 TEM Safe to Mate Procedure Pending Sign-OffLAT-DS-00554-06 TEM Box Base Signed OffLAT-DS-00555-06 TEM Box Lid Signed OffLAT-DS-01026-02 TEM Connector Plate Signed OffLAT-DS-01031-02 TEM Connector Pin Signed OffLAT-DS-01646-04 Circuit Card Assembly, TEM DAQ Signed OffLAT-DS-01649-05 Printed Wire Board, TEM Signed OffLAT-DS-02583-03 PWB Fab, Loading and Assembly Signed OffLAT-DS-02588-02 Connector and Cable Assembly, TEM CCA Signed OffLAT-DS-01650-02 Schematic Diagram, TEM CCA Signed OffLAT-TD-02230-02 Bill of Materials, TEM CCA Signed OffLAT-TD-01782-02 Parts Stress Analysis, TEM CCA In ReviewLAT-TD-01785-02 Worst Case Design Analysis, TEM CCA In ReviewLAT-DS-03895-50 Programmed FPGA, GTIC Signed OffLAT-DS-04376-01 Program, GTIC FPGA Signed OffLAT-DS-04452-01 Design Database for GTIC FPGA Signed OffLAT-DS-03894-50 Programmed FPGA, GTIU Signed OffLAT-DS-04377-01 Program, GTIU FPGA Signed OffLAT-DS-04453-01 Design Database for GTIU FPGA Signed OffLAT-TD-01880-01 VHDL, LAT TEM GTIC FPGA Signed OffLAT-TD-01881-01 VHDL, LAT TEM GTIU FPGA Signed OffLAT-DS-03582-01 Spacer, TEM Connector Signed OffLAT-DS-04354-01 Washer, TEM CAL Baseplate Signed Off


4.1.7 DAQ & FSW V1 11

GASUGASU


4.1.7 DAQ & FSW V1 12

ASICsASICs

GTCC ASIC _ Part of TEM CCA LAT-DS-01646LAT-TD-01812-01 Layout, GTCC ASIC Signed OffLAT-DS-01811-01 Schematic Diagram, GTCC ASIC In sign-offLAT-TD-01550-02 Specification, GTCC ASIC Signed OffLAT-TD-01810-01 Test Procedure, GTCC/GCCC ASIC Signed OffLAT-TD-02656-02 Screening and Test Plan, GTCC/GCCC ASIC Draft-In WorkLAT-TD-01882-01 VHDL, GTCC ASIC Signed OffLAT-TD-02487-01 GTCC1 ASIC T36T Wire-bonding and Packaging Require Signed Off

GCCC ASIC - Part of TEM CCA LAT-DS-01646LAT-TD-01814-01 Layout, GCCC ASIC Signed OffLAT-DS-01815-01 Schematic Diagram, GCCC ASIC in sign-offLAT-TD-01549-02 Specification, GCCC ASIC Signed OffLAT-TD-02656-02 Screening and Test Plan, GTCC/GCCC ASIC in sign-offLAT-TD-01883-01 VHDL, GCCC ASIC Signed OffLAT-TD-02486-01 GCCC1 ASIC T36T Wire-bonding and Packaging Require Signed Off

• GLTC radiation and qualification– SEL and SEU ok– TID is scheduled for next week in Italy– Qualification at GSFC will start after the radiated ASICs are tested on the

test-setup, so it can be shipped to GSFC.– ASICs for flight boards are being burned in and tested, full quantity required

ready within one week.


4.1.7 DAQ & FSW V1 13

Engineering Model Design ValidationEngineering Model Design Validation

• PDU & GASU– Tested on bench and on test-bed

• Functionality and performance validated on test-bed• 16 TEM/TPS connected to EM PDU and GASU and to

SIU, EPU’s and ACD FREE’s– Validated over frequency and voltage margins– GASU used in ACD G3 test-stands at GSFC

– Limitations• No temperature tests performed on PDU or GASU• Flight boards checked for flight component foot-prints• PDU: flight board loaded with some flight components

and tested• GASU: no flight board tested yet


4.1.7 DAQ & FSW V1 14

IssueIssue

• GLTC ASIC (GASU)– ESD sensitivity about 200V

• Assembly controls to < 50V• Trigger FPGA code (GASU)

– Only recently finalized and tested on test-bed• Flight FPGA’s slower

– Could not burn 9 flight FPGA’s for use on non-flight board– Finite risk

• Omnirel fixed-voltage regulator (PDU)– Was recalled and we are waiting for replacements,

promised end of February• Transient Suppressor diode did not pass DPA (PDU)

– Ordered S-class replacements which were in stock• PCB’s did not pass coupon testing (PDU)

– Fabricated new batch, is at GSFC for coupon testing

Documents

GLAST LAT ProjectPDU/GASU MRR, February 3, 2005 4.1.7 DAQ & FSWV1 1 GLAST Large Area Telescope: B. Estey, G. Haller SLAC xxxx LAT Quality Engineer [email protected]