GIBIN P GEORGEE-mail : gibin.knr@gmail.com Mob : 09539079990

Title: RTL Verification engineer

Nearly 1 year of experience in RTL Verification using System Verilog and UVM 3 years and 6 months of experience (2 years of project experience) as RTL Design

Engineer and worked in FPGA design, Simulation, Debugging and board level verification of the design.

Objective To be an integral part of a respected and professional organization, where I can exploit myself and to contribute to the growth of organization.

Educational Qualification Bachelor of Technology (B.Tech) in Electronics & Communications Engineering with

first class from LBS College of Engineering, Kasaragod, Kerala during 2004-08.

Passed 12th & 10th std (CBSE) from J Navodaya Vidyalaya, Kannur with good academic track record.

Brief on Skill Set-

RTL verification using Sytem verilog, UVM and Verilog. Good understanding of constrained random verification concepts. Knowledge in coverage driven verification.

RTL hardware design using VHDL and Verilog. Simulation of the design modules using ModelSim. Synthesizing the RTL modules using Xilinx/Altera tools. Chip level analysis and debugging the design. Board level verification of the design. Project related detailed documentations.

HVL System verilogVerification Methodology UVMVerification Tool QuestaSimHDL VHDL, VerilogDevelopment Tools Xilinx ISE, Altera Quartus IISimulation Tool ModelSimTest and Debugging Tools Chipscope Pro Analyzer, OscilloscopeInterfacings AMBA AXI, AHB, APB, MIL-STD 1553, I2C busOperating Systems Windows, LinuxOther tools Microsoft Office Suite

Nature of job done

Analyzing the requirement from client companies and prepare design document. Write the RTL for the modules assigned and integrate the modules. Simulate the design at various levels. Verify the design on the board. Prepare detailed document for the project.

Experience Summary

Trainee Experience Institute : Maven Silicon Course Title : ASIC Verification Period : Oct. 2014 – June 2014

Completed a training program in ASIC verification using system verilog and UVM methodology. Designed RTL for AHB to APB bridge and verified it using UVM. Verified AXI protocol.

2) Previous employer : Mindteck (India) Ltd. Designation : Hardware Design engineer Department : EDS Hardware Services Period : May 2012 – Oct 2013 Location : Bangalore, IndiaDesigned, implemented and tested I2C master, slave.

3) Previous employer : Digeratti Systems Designation : Design engineer(FPGA) Period : March 2010 – May 2012 Location : Bangalore

Designed, implemented and verified MIL-STD_1553B bus interface on Spartan-3 FPGA, that provides a complete integrated interface between a host processor and MIL-STD-1553 bus.

Verification Project Details

1) AHB to APB bridgeAHB to APB bridge RTL is designed and verified for single master multiple slaves. The bridge is an AHB slave providing interface between AHB and APB. Read and write transfers on the AHB are converted to equivalent transfers on APB. Wait states are added during transfers to and from APB when AHB is required to wait.

Role Played: Designed, developed the RTL and verified it using UVM.2) AXI

AXI protocol is verified for single master single slave. The AXI master and slave modules were created in testbench to observe communication between them, and ensure that it works as per specification. For master write, Narrow, Aligned, Unaligned transactions were verified for various burst size and burst length. For master read, burst and overlapping burst transfers were verified.

Role Played: Designed, developed the RTL and verified it using UVM.

FPGA Design Project Details

1) MIL-STD-1553 Bus InterfaceClient organization : A public sector customer from defense applications domain

Mil-Std-1553B protocol data bus interface being implemented on SPARTAN-3 FPGA that provides a complete integrated interface between a host processor and MIL-STD-1553 bus. The system uses command/response method. It interfaces a host processor to the external RAM. The MIL-STD-1553B interface incorporates processor interface, memory management and MIL-STD-1553B protocol elements such as Bus Controller, Remote Terminal, and Bus Monitor.

Role Played: RTL development, Simulation and on board testing of the modules.

2) I2C Slave ModuleClient organization : USA customer from embedded computing domain

The I2C slave module is implemented on Max II CPLD from Altera. It can work at 100 KHz and 400 KHz clock frequency. It supports features like burst read and write operation. Debounce logic is incorporated. Role Played: RTL development, Simulation and on board testing of the I2C slave module.

3) I2C Master coreClient organization : USA customer from embedded computing domain

The I2C master core incorporates all features required by the v.2.1 of I2C specification including arbitration, multi-master systems and High-speed transmission mode. It can operate from a wide range of the clock frequencies.The I2C core can be configured as a master transmitter or master receiver. It uses 16 bit address and data interface to the host. This core is having an internal register set of configuration registers and data registers.

Role Played: File I/O based test bench development and verification of the complete I2C Master core.

Personal DetailsDate of Birth : 18/05/1986Gender : MaleMarital Status : SingleLanguages Known : English, Hindi and Malayalam.Nationality : IndianCurrent Location : Bangalore

Place : Bangalore Date : GIBIN P GEORGE