Embed Size (px)
DESCRIPTION
Binary Counters Integer Representations towards Efficient Counting in the Bit Probe Model (paper presented at TAMC 2011). Gerth Stølting Brodal (Aarhus Universitet ) Mark Greve (Aarhus Universitet ) Vineet Pandey (BITS Pilani , Indien ) S . Srinivasa Rao (Seoul, Syd Korea) - PowerPoint PPT Presentation
Citation preview
Binary CountersInteger Representations towards
Efficient Counting in the Bit Probe Model(paper presented at TAMC 2011)
Gerth Stølting Brodal (Aarhus Universitet) Mark Greve (Aarhus Universitet)
Vineet Pandey (BITS Pilani, Indien)S. Srinivasa Rao (Seoul, Syd Korea)
MADALGO Seminar, June 1, 2011
0
1
10
11
100
101
110
111
1000
1001
1010
1011
1100
1101
1110
1111
0000- we are counting modulo 100002 = 1610
10111 2∙ 3+ 0 2∙ 2+ 1 2∙ 1+ 1 2∙ 0 = 8+2+1 =
1110
Decimal Binary0 00001 00012 00103 00114 01005 01016 01107 01118 10009 1001
10 101011 101112 110013 110114 111015 11110 0000
b3b2b1b0
b00 1
b1
b2
b3
0 1
0 1
0 1
---1
--10
0000
-100
1000
Reads 4 bitsWrites 4 bits
Decimal Binary0 00001 00012 00103 00114 01005 01016 01107 01118 10009 1001
10 101011 101112 110013 110114 111015 11110 0000
Decimal Binary0 00001 00012 00103 00114 01005 01016 01107 01118 10009 1001
10 101011 101112 110013 110114 111015 11110 0000
Algorithm
Decimal Binary Reflected Gray code0 0000 00001 0001 00012 0010 00113 0011 00104 0100 01105 0101 01116 0110 01017 0111 01008 1000 11009 1001 1101
10 1010 111111 1011 111012 1100 101013 1101 101114 1110 100115 1111 10000 0000 0000
"To get the next code, for a code
with even parity, flip the rightmost
bit. For a code with odd parity, find
the rightmost ‘1’ and flip the bit to
its left. The only special case is
when the last bit bn is the only ‘1’ in
the code. This is also the last code
in the sequence."
Decimal Binary Reflected Gray code0 0000 00001 0001 00012 0010 00113 0011 00104 0100 01105 0101 01116 0110 01017 0111 01008 1000 11009 1001 1101
10 1010 111111 1011 111012 1100 101013 1101 101114 1110 100115 1111 10000 0000 0000
Always reads 4 bitsAlways writes 1 bit
---0
b0
b1
b2
--1- ---0 ---0 --0- --0- --1- -0--
b2 b2 b2
b1
0 1 0 1 0 1 0 1
0 1 0 1
0 1
0------1 -1-- 1--- ---1 ---1 ---1 ----0
b30 1
b30 1
b30 1
b30 1
b30 1
b30 1
b30 1
b30 1
b3b2b1b0
QuestionDoes there exist a counter where one
never needs to read all bits to increment the counter ?
Decimal0 00001 00012 01003 01014 11015 10016 11007 11108 01109 0111
10 111111 101112 100013 101014 001015 00110 0000
Decimal0 00001 00012 01003 01014 11015 10016 11007 11108 01109 0111
10 111111 101112 100013 101014 001015 00110 0000
Decimal0 00001 00012 01003 01014 11015 10016 11007 11108 01109 0111
10 111111 101112 100013 101014 001015 00110 0000
b3b2b1b0
-1-0
b0
b1
b1
---1 --1- ---1 0--- --00 1--- -0--
b3 b3 b3
b2
0 1 0 1 0 1 0 1
0 1 0 1
0 1
Always reads 3 bitsAlways writes ≤ 2 bits
[B., Greve , Pandey, Rao 2011]
bn-1 bn-2 ∙∙∙ b6 b5 b4 b3 b2 b1 b0
Generalization to n bit counters
Y4 bits
3 reads2 writes
Xn-4 bit Gray code
n-4 reads1 writes
metode Increment(XY) inc(X) if (X == 0) inc(Y) Always reads n-1 bits
Always writes ≤ 3 bits
[B., Greve , Pandey, Rao 2011]
Theorem 4-bit counter 3 reads and 2 writes
n-bit counter n-1 reads and 3 writesOpen problems n-1 reads and 2 writes ? « n reads and writes ? [number of reads at least log2 n]
-1-0
b0
b1
b1
---1 --1- ---1 0--- --00 1--- -0--
b3 b3 b3
b2
0 1 0 1 0 1 0 1
0 1 0 1
0 1 n=5??
bits read
bits
writt
en
Redundant Counters
Represent L different valuesusing d>log L bits
Efficiency E = L / 2d
bn bn-1 ∙∙∙ blog n blog n ∙∙∙ b0
Redundant counter with E = 1/2
XL
log n bit Gray codelog n reads
1 write
XH
n-log n bits 1 read1 write
standard binary counterwith delayed increment
Idea: Each increment of XL performs one step of the delayed increment of XH
n+1 bits 2n values log n + 2 reads 3 writes
[B., Greve , Pandey, Rao 2011]
carry1 bit
1 read1 write
carry XH XL
1 0 1 0 1 1 0 0 0
1 0 1 0 1 0 0 0 1
1 0 1 0 0 0 0 1 1
0 0 1 1 0 0 0 1 0
0 0 1 1 0 0 1 1 0
0 0 1 1 0 0 1 1 1
0 0 1 1 0 0 1 0 1
0 0 1 1 0 0 1 0 0
1 0 1 1 0 0 0 0 0
0 0 1 1 0 1 0 0 1
Redundant counter with E = 1/2
increment
…
Value = Val(XL) + 2|XL|·(Val(XH)+ carry·2Val(XL) )
n+1 bits 2n values log n + 2 reads 3 writes
carry XH XL
1 0 1 0 1 1 0 0 0
1 0 1 0 1 0 0 0 1
1 0 1 0 0 0 0 1 1
1 0 1 1 0 0 0 1 0
0 0 1 1 0 0 1 1 0
0 0 1 1 0 0 1 1 1
0 0 1 1 0 0 1 0 1
0 0 1 1 0 0 1 0 0
1 0 1 1 0 0 0 0 0
1 0 1 1 0 1 0 0 1
Redundant counter with E = 1/2
increment
…n+1 bits 2n values log n + 3 reads 2 writes
delayed reset
delayed reset
bn+t-1∙∙∙ bn bn-1 ∙∙∙ blog n blog n ∙∙∙ b0
Redundant counter with E = 1-O(1/2t)
XL
log n bit Gray codelog n reads
1 write
XH
n-log n bits 1 read1 write
delayed standard binary counter
”Carry” : part of counter = 0.. 2t-3, set = 2t-2, clear 2t-1
n+t bits (2t-2)·2n values log n+t+2 reads 4 writes
[B., Greve , Pandey, Rao 2011]
”carry”t bits
t read1 write
Redundant Counters
Efficiency Space Reads Writes
1/2 n + 1log n + 2 3log n + 3 2
1-O(1/2t) n + tlog n + t + 3 4log n + t + 4 3
Open problem 1 write and « n reads ?
Addition of Counters
Numbers in the range 0..2n-1 and 0..2m-1 (m ≤ n)
Space Reads Writesn + O(log n) Θ(m + log n)
Θ(m)n + O(loglog n) Θ(m + log n·loglog n)n + O(1) Θ(m + log2 n)
Ideas: log n blocks of 20,20,21,22,…,2i,2i+1,… bitsIncremental carry propagation
THANK YOU
