Gerousis Toward Nano-Networks and Architectures C. Gerousis and D. Ball Department of Physics, Computer Science and Engineering Christopher Newport University

Gerousis

Toward Nano-Networks and Architectures

C. Gerousis and D. BallDepartment of Physics, Computer Science and Engineering

Christopher Newport UniversityNewport News, VA 23606

2 1015/MAPLD 2005Gerousis

Nanoelectronic

Architectures• Limits of Conventional CMOS technology - Device physics scaling, power dissipation - Interconnects

• Nanoelectronic Integrated Circuits

• Present Work-Simulation of nano networks synthesized from single-electron tunneling transistors (SETs)-Demonstration of SET-CNN and SET neural applications

- Hybrid circuits of ultrascale CMOS coupled to locally connected cellular nonlinear networks (CNNs) of nanodevices for special purpose processing


Nanoelectronic Integrated Circuit

CMOS drivers for fan-out

Single-electron transistors as processing elements

Photo-detector

CMOS and SETs are rather complementary: SET is the winner of low-power consumption and of new functionality while the advantages of CMOS such as high-speed, driving, voltage gain and input impedance can makeup for exactly for the SET's intrinsic shortcomings.


R ,Cd d R ,Cs s

island

V a _+

V g _+

C g

__

n 1 n 2

sourcedrain

gate

Single-Electron Transistor

A single-electron tunneling (SET) transistor composed of a conducting island (or quantum dot) between two tunnel junctions characterized by junction capacitances, Cs and Cd,

and tunneling resistances, Rs and Rd.


Electron tunneling is suppressed due to the Coulomb charging energy, e2/2C. A separate gate voltage changes the charge state of the dot (island), and periodically lifts the Coulomb blockade allowing tunneling.

EFl

EFr

e

0 1 2 30

1

G/Gmax

Vg (e/Cg)

Single-Electron Transistor

Si SOI Single Electron Transistor:D. H. Kim et al., IEEE Trans. ED 49, 2002


Monte Carlo simulation of SET circuits

The Master Equation for a set of N dots (islands) in terms of the multi-island distribution function is given by

tnnfnnnntnnfnn

tnnfnndt

tnnndf

iiiii

iNi

iN

,,..,...,...,1,..1,...

,1,..1,...,,...,,

11111

1,1

121

kTE

n

tjne

eE

eRn

/1

/1

where the tunneling rate depends on change of total free energy of systems after tunneling


)]()([)()]()([)( )( 1122 nnnfnnnfeVInn

Average quantities such as current in a two junction system are given as averages

Single electron tunnel events modeled as instantaneous events which are generated stochastically using the calculated tunneling rates for all possible events across all junctions, and using the computer random number generator

j

jr

rt .....

)(ln-

where r is random number 0,1 and tr is the random time between tunneling events. After tunneling, the new tunnel rates are computed, and the next tunneling event generated. The time evolution according to the master equation is modeled as random walk.

Monte Carlo simulation of SET circuits


‘SIMON’ (SIMulation Of Nano structures)

C. Wassshuber and H. Kosina, "SIMON: A Single-Electron Device and Circuit Simulator", Superlattices and Microstructures 21, 37 (1997).


SET Cellular Nonlinear Networks

Feedforward synapses Feedback synapses

xij

a ykl klb ukl kl

xij

A non-linear architecture suitable for SET devices is a locally interconnected CNN type array structure for use in array processing such as image processing applications. The center cell, Cij, receives a weighted

feedforward signal bklukl and a weighted feedback signal aklykl from each

neighboring cell Ckl.


ijij

ijijijij

ijijij zubyax

dt

dx Cell state equation:

x

y

1

-1

1 1,-

1

1 ,1

112

1)(

ij

ijij

ij

ijijijij

x

xx

x

xxxfyCell output equation:

Transfer function:

Cellular Nonlinear Networks


V in 1

C 11

V in 2

C 1 2

V b o u n d a ry -L

V b o u n d a ry -R

V in 3V o u t2

C 2 3

V o u t3

V o u t1

C 2 1

C 2 2

C 3 2

C 3 3

C12=C23=0.55aF

C11=C22= C22=0.1aF

Template:

Single-Electron Cellular Network - Shadowing


Threshold Gate in SET Networks

Model of a TLG with SET technology (Lageweg et al.)

A threshold gate can be described by the following equations:

where ω are the weights, x represents the inputs, and ψ is the threshold

n

1i

iixXG

0xGif1

0xGif0XGxF

)(

)(

)()}(sgn{)(


Threshold Gate - SET inverter

Model of a TLG with SET technology (Lageweg et al.)


Network for Recognition of Bit Pattern

V1

V2

V3

V4

Vout

1111 1001


Network for Recognition of Bit Pattern

V1

V2

V3

V4

Vout

1000 0001


Number Recognition Sub-Networks


Number Recognition Test Circuit

The network contains several levels/layers of hidden operations between input and output. These layers include row detection, number recognition, and encoding.


M S1 S0

0 0 0

1 0 1

2 1 0

≥3 1 1

M2

M1 M2

M3 M4

Number Recognition Test Circuit

Input Matrices for V0-V19:


0.00E+00

4.00E-03

8.00E-03

1.20E-02

1.60E-02

2.00E-02

0.00E+00

4.00E-03

8.00E-03

1.20E-02

1.60E-02

0.00E+00

4.00E-03

8.00E-03

1.20E-02

1.60E-02

2.00E-02

0.00E+00

4.00E-03

8.00E-03

1.20E-02

1.60E-02

2.00E-02

00 01

10 11

Number Recognition Network – Results


• A neural nanoelectronics architecture with a low interconnection density, such as cellular neural networks (CNNs) are implemented in analog circuit techniques so that low power applications, such as intelligent sensor pre-processing are preferred applications.

• Limitations: - Small capacitance values required for room- temperature operation. - SET weights are hard wired by the use of capacitive connections, which limits the range of applications. - The charge sensitivity of the devices also imposes strong limitations on the allowable electrostatic interaction between different devices in a ULSI circuit.

Conclusions

Documents

Gerousis Toward Nano-Networks and Architectures C. Gerousis and D. Ball Department of Physics, Computer Science and Engineering Christopher Newport University