George Mason University ECE 449 – Computer Design Lab Introduction to FPGA Devices & Tools

ECE 449 – Computer Design Lab George Mason University

Introduction to FPGA

Devices & Tools


FPGA Devices

ECE 449 – Computer Design Lab 3

World of Integrated Circuits

Integrated Circuits

Full-CustomASICs

Semi-CustomASICs

UserProgrammable

PLD FPGA

PAL PLA PML LUT(Look-Up Table)

MUX Gates


• designs must be sent for expensive and time consuming fabrication in semiconductor foundry

• bought off the shelf and reconfigured by designers themselves

Two competing implementation approaches

ASICApplication Specific

Integrated Circuit

FPGAField Programmable

Gate Array

• designed all the way from behavioral description to physical layout

• no physical layout design; design ends with a bitstream used to configure a device


Block R

AM

s

Block R

AM

s

ConfigurableLogicBlocks

I/OBlocks

What is an FPGA?

BlockRAMs


Which Way to Go?

Off-the-shelf

Low development cost

Short time to market

Reconfigurability

High performance

ASICs FPGAs

Low power

Low cost inhigh volumes


Other FPGA Advantages

• Manufacturing cycle for ASIC is very costly, lengthy and engages lots of manpower• Mistakes not detected at design time have

large impact on development time and cost• FPGAs are perfect for rapid prototyping of

digital circuits

• Easy upgrades like in case of software

• Unique applications• reconfigurable computing


Major FPGA Vendors

SRAM-based FPGAs• Xilinx, Inc.• Altera Corp.• Atmel• Lattice Semiconductor

Flash & antifuse FPGAs• Actel Corp.• Quick Logic Corp.


Xilinx

Primary products: FPGAs and the associated CAD software

Main headquarters in San Jose, CA Fabless* Semiconductor and Software Company

UMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996} Seiko Epson (Japan) TSMC (Taiwan)

Programmable Logic Devices ISE Alliance and Foundation

Series Design Software


Xilinx FPGA Families• Old families

• XC3000, XC4000, XC5200• Old 0.5µm, 0.35µm and 0.25µm technology. Not

recommended for modern designs.

• High-performance families• Virtex (0.22µm)• Virtex-E, Virtex-EM (0.18µm)• Virtex-II, Virtex-II PRO (0.13µm)

• Low Cost Family• Spartan/XL – derived from XC4000• Spartan-II – derived from Virtex• Spartan-IIE – derived from Virtex-E• Spartan-3



Basic Spartan-II FPGA Block Diagram


F5IN

CINCLKCE

COUT

D Q

CK

S

REC

D Q

CK

REC

O

G4G3G2G1

Look-UpTable

Carry&

ControlLogic

O

YBY

F4F3F2F1

XBX

Look-UpTable

BYSR

S

Carry&

ControlLogic

SLICE

COUT

D Q

CK

S

REC

D Q

CK

REC

O

G4G3G2G1

Look-UpTable

Carry&

ControlLogic

O

YBY

F4F3F2F1

XBX

Look-UpTable

F5INBYSR

S

Carry&

ControlLogic

CINCLKCE SLICE

CLB Structure

• Each slice has 2 LUT-FF pairs with associated carry logic• Two 3-state buffers (BUFT) associated with each CLB,

accessible by all CLB outputs


CLB Slice Structure

• Each slice contains two sets of the following:• Four-input LUT

• Any 4-input logic function,• or 16-bit x 1 sync RAM• or 16-bit shift register

• Carry & Control• Fast arithmetic logic• Multiplier logic• Multiplexer logic

• Storage element• Latch or flip-flop• Set and reset• True or inverted inputs• Sync. or async. control


LUT (Look-Up Table) Functionality

• Look-Up tables are primary elements for logic implementation

• Each LUT can implement any function of 4 inputs

x1 x2 x3 x4

y

x1 x2

y

LUT

x1x2x3x4

y

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y0100010101001100

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y1111111111110000

x1 x2 x3 x4

y

x1 x2 x3 x4

y

x1 x2

y

x1 x2

y

LUT

x1x2x3x4

y

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y0100010101001100

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y0100010101001100

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y1111111111110000

0x1

0x2 x3 x4

0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y1111111111110000


RAM16X1S

O

DWE

WCLKA0A1A2A3

RAM32X1S

O

DWEWCLKA0A1A2A3A4

RAM16X2S

O1

D0

WEWCLKA0A1A2A3

D1

O0

=

=LUT

LUT or

LUT

RAM16X1D

SPO

D

WE

WCLK

A0

A1

A2

A3

DPRA0 DPO

DPRA1

DPRA2

DPRA3

or

Distributed RAM

• CLB LUT configurable as Distributed RAM• A LUT equals 16x1 RAM• Implements Single and Dual-

Ports• Cascade LUTs to increase

RAM size

• Synchronous write• Synchronous/Asynchronous

read• Accompanying flip-flops used

for synchronous read


D QCE

D QCE

D QCE

D QCE

LUT

INCE

CLK

DEPTH[3:0]

OUTLUT =

Shift Register

• Each LUT can be configured as shift register• Serial in, serial out

• Dynamically addressable delay up to 16 cycles

• For programmable pipeline

• Cascade for greater cycle delays

• Use CLB flip-flops to add depth


Shift Register

• Register-rich FPGA• Allows for addition of pipeline stages to increase throughput

• Data paths must be balanced to keep desired functionality

64Operation A

4 Cycles 8 Cycles

Operation B

3 Cycles

Operation C64

12 Cycles

3 Cycles9-Cycle imbalance


COUT

D Q

CK

S

REC

D Q

CK

REC

O

G4G3G2G1

Look-UpTable

Carry&

ControlLogic

O

YB

Y

F4F3F2F1

XB

X

Look-UpTable

F5IN

BYSR

S

Carry&

ControlLogic

CINCLKCE SLICE

Carry & Control Logic


Each CLB contains separate logic and routing for the fast generation of sum & carry signals• Increases efficiency and

performance of adders, subtractors, accumulators, comparators, and counters

Carry logic is independent of normal logic and routing resources

Fast Carry Logic

LSB

MSB

Car

ry L

ogic

Rou

ting


Accessing Carry Logic

All major synthesis tools can infer carry logic for arithmetic functions

• Addition (SUM <= A + B)

• Subtraction (DIFF <= A - B)

• Comparators (if A < B then…)

• Counters (count <= count +1)


Block RAM

Spartan-IITrue Dual-Port

Block RAM

Port A

Port B

Block RAM

• Most efficient memory implementation• Dedicated blocks of memory

• Ideal for most memory requirements• 4 to 14 memory blocks

• 4096 bits per blocks

• Use multiple blocks for larger memories

• Builds both single and true dual-port RAMs


Spartan-II Block RAM Amounts


Block RAM Port Aspect Ratios

0

4095

1

1023

40

1047

20

511

80

255

160

4k x 1

2k x 2 1k x 4

512 x 8

256 x 16


Basic I/O Block Structure

DEC

Q

SR

DEC

Q

SR

DEC

Q

SR

Three-StateControl

Output Path

Input Path

Three-State

Output

Clock

Set/Reset

Direct Input

Registered Input

FF Enable

FF Enable

FF Enable


IOB Functionality

• IOB provides interface between the package pins and CLBs

• Each IOB can work as uni- or bi-directional I/O

• Outputs can be forced into High Impedance

• Inputs and outputs can be registered• advised for high-performance I/O

• Inputs can be delayed


Routing Resources

PSM PSM

CLB

PSM PSM

CLB CLB

CLBCLB CLB

CLBCLB CLB

ProgrammableSwitchMatrix


Spartan-II FPGA Family Members



Virtex-II 1.5V Architecture

Configurable

Logic

Block

Block R

AM

s

I/OBlock

Multipliers 18 x 18

Block R

AM

s

Multipliers 18 x 18

Block R

AM

s

Multipliers 18 x 18

Block R

AM

s

Multipliers 18 x 18


Virtex-II 1.5V

Device CLB Array

Slices Maximum I/O

BlockRAM

(18kb)

Multiplier Blocks

Distributed RAM bits

XC2V40 8x8 256 88 4 4 8,192

XC2V80 16x8 512 120 8 8 16,384

XC2V250 24x16 1,536 200 24 24 49,152

XC2V500 32x24 3,072 264 32 32 98,304

XC2V1000 40x32 5,120 432 40 40 163,840

XC2V1500 48x40 7,680 528 48 48 245,760

XC2V2000 56x48 10,752 624 56 56 344,064

XC2V3000 64x56 14,336 720 96 96 458,752

XC2V4000 80x72 23,040 912 120 120 737,280

XC2V6000 96x88 33,792 1,104 144 144 1,081,344

XC2V8000 112x104 46,592 1,108 168 168 1,490,944


Virtex-II Block SelectRAM• Virtex-II BRAM is 18 kbits

• Additional “parity” bits available in selected configurations

WEA

ENA

SSRA

CLKA

ADDRA[# : 0]

DIA[# : 0]

DOA[# : 0]

WEB

ENB

RSTB

CLKB

ADDRB[# : 0]

DIB[# : 0]

DOB[# : 0]

DIPA[# : 0]

DIPA[# : 0]

DOPA[# : 0]

DOPB[# : 0]

WEA

ENA

SSRA

CLKA

ADDRA[# : 0]

DIA[# : 0]

DOA[# : 0]

WEB

ENB

RSTB

CLKB

ADDRB[# : 0]

DIB[# : 0]

DOB[# : 0]

DIPA[# : 0]

DIPA[# : 0]

DOPA[# : 0]

DOPB[# : 0]

Width Depth Address Data Parity

1 16,386 [13:0] [0] N/A

2 8,192 [12:0] [1:0] N/A

4 4,096 [11:0] [3:0] N/A

9 2,048 [10:0] [7:0] [0]

18 1,024 [9:0] [15:0] [1:0]

36 512 [8:0] [31:0] [3:0]


FPGA Nomenclature


FPGA Tools


Design process (1)

Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..

Library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; );end AES_core;

Specification (Lab Experiments)

VHDL description (Your Source Files)

Functional simulation

Post-synthesis simulationSynthesis


Design process (2)

Implementation

Configuration

Timing simulation

On chip testing


Design Process control from Active-HDL


Simulation Tools

Many others…




Synthesis Tools

… and others


architecture MLU_DATAFLOW of MLU is

signal A1:STD_LOGIC;signal B1:STD_LOGIC;signal Y1:STD_LOGIC;signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;

beginA1<=A when (NEG_A='0') else

not A;B1<=B when (NEG_B='0') else

not B;Y<=Y1 when (NEG_Y='0') else

not Y1;

MUX_0<=A1 and B1;MUX_1<=A1 or B1;MUX_2<=A1 xor B1;MUX_3<=A1 xnor B1;

with (L1 & L0) selectY1<=MUX_0 when "00",

MUX_1 when "01",MUX_2 when "10",MUX_3 when others;

end MLU_DATAFLOW;

VHDL description Circuit netlist

Logic Synthesis


Features of synthesis tools

• Interpret RTL code

• Produce synthesized circuit netlist in a standard EDIF format

• Give preliminary performance estimates

• Some can display circuit schematics corresponding to EDIF netlist


Implementation

• After synthesis the entire implementation process is performed by FPGA vendor tools



Translation

Translation

UCF

NGD

EDIF NCF

Native Generic Database file

Constraint Editor

User Constraint File

Native Constraint

File

Electronic Design Interchange Format

Circuit netlist Timing Constraints

Synthesis


Sample UCF File

• #• # Constraints generated by Synplify Pro 7.3.3, Build 039R• #• # Period Constraints• #Begin clock constraints• #End clock constraints• # Output Constraints• # Input Constraints• # Location Constraints• # End of generated constraints• NET "clock" LOC = "P88";• NET "control(0)" LOC = "P50";• NET "control(1)" LOC = "P48";• NET "control(2)" LOC = "P42";• NET "reset" LOC = "P93";• NET "segments(0)" LOC = "P67";• NET "segments(1)" LOC = "P39";• NET "segments(2)" LOC = "P62";• NET "segments(3)" LOC = "P60";• NET "segments(4)" LOC = "P46";• NET "segments(5)" LOC = "P57";• NET "segments(6)" LOC = "P49";


Pin Assignment

LAB2

CLOCKCONTROL(0)

CONTROL(2)CONTROL(1)

RESET

SEGMENTS(0)SEGMENTS(1)SEGMENTS(2)SEGMENTS(3)SEGMENTS(4)SEGMENTS(5)SEGMENTS(6)

P39

P42P46

P48P49P50

P57

P60

P62

P67

P88

P93FPGA


Parallel Port Interface


Constraints Editor


Circuit netlist


Mapping

LUT2

LUT3

LUT4

LUT5

LUT1

FF1

FF2


PlacingCLB SLICES

FPGA


Routing

Programmable Connections

FPGA


Static Timing Analyzer

• Performs static analysis of the circuit performance

• Reports critical paths with all sources of delays

• Determines maximum clock frequency


Static Timing Analysis

• Critical Path – The Longest Path From Outputs of Registers to Inputs of Registers

D Qin

clk

D Qout

tP logic

tCritical = tP FF + tP logic + tS FF


Static Timing Analysis

• Min. Clock Period = Length of The Critical Path

• Max. Clock Frequency = 1 / Min. Clock Period


Configuration

• Once a design is implemented, you must create a file that the FPGA can understand• This file is called a bit stream: a BIT file (.bit extension)

• The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information


Resources & Required ReadingSpartan FPGA devices

Xilinx Spartan-II 2.5V FPGA Family: Complete Data Sheet

• Module 1: Introduction & Ordering Information• Module 2: Functional Description

http://direct.xilinx.com/bvdocs/publications/ds001.pdf


Integrated Interfaces: Active-HDL with Synplify®

http://www.aldec.com/Previews/active_synplify.htm

Integrated Synthesis and Implementationhttp://www.aldec.com/Previews/synthesis_implementation.htm

Resources & Required Reading

FPGA Tools


Hands-on Session

Enough Talking Let’s Get To It!!Brace Yourselves!!


0

1Y [3:0]

neg_Y

0

1

ar_log

0

1

2

3

arith [1:0]

A + B

A - B

A <<< 1

A >>> 1

0

1

2

3

logic [1:0]

A and B

A or B

A xor B

A xnor B

A[3:0]

B[3:0]

ALU Schematic


Questions?

Documents

George Mason University ECE 449 – Computer Design Lab Introduction to FPGA Devices & Tools