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Geometry Sensitivity Analyses of Micro-structures of IC Packages
on Passivation Cracking
Y.T. He1,2,a, F. Li1,a, R. Shi3,b, G.Q. Zhang4,c, L.J. Ernst5,d,
J. Zhang6,e and Z.T. Song3,b 1College of Aeronautics, University of Air Force Engineering, Xi’an, P.R.China
2College of Aeronautics, Northwestern Polytechnical University, Xi’an, P.R.China
3Shanghai Institute of Microsystem and Information Technology, CAS, Shanghai, P.R.China
4Philips Centre for Industrial Technology, P.O.Box 218, 5600 MD Eindhoven, The Netherlands
5Delft University of Technology, 2628 CD Delft, The Netherlands
6Loctite Corporation, San Diego, CA92126, US
[email protected], [email protected], [email protected], [email protected], [email protected]
Keywords: Package, IC, Passivation crack, Interconnect, Principal stress, Response Surface Model
Abstract. Passivation crack is one of the main failures of micro-electronics. And the IC interconnect has a large varying range values comparing with its geometry size. In this paper, the influence of geometry values of micro-structures of IC packages on passivation cracking is studied by maximum principal stress theory using a certain 2D FEM model with different design geometry parameters, pitch of lines, width of line, thickness of epoxy, thickness of dielectric layer and the Aluminum yielding stress (following as “d”, “w”, “t_epo”, “t_Teos” and “sy_al” respectively). For different critical process step, here the final process temperature is acted as a representative parameter to analyze its impact. Furthermore, Response Surface Model (RSM) of principal stress is established using any two design parameters. Results show that width of line, thickness of dielectric layer and the Aluminium yielding stress will have great influence on passivation cracking while other parameters having little impact.
Introduction
Reliability of the Integrated Circuits (ICs) is one of major concerns for semiconductor industry. Thermo-mechanical failures, such as passivation cracks, pattern shift, loose bond balls, wire break, voids, buckling, hillocks, delamination and (or) debonding, are often observed during manufacturing processes, qualification tests and field applications [1-5].
To predict the phenomena of passivation crack, the geometry sensitivity analyses of micro-structures of IC packages are carried out here. Namely, the principal stress method is used here, which calculates the stress distribution and applies the maximum principal stresses as the failure criteria.
According to the observations, passivation cracks often occur close to the metal layout close to IC edges: the power line, the seal ring and the bond pads. The position of these devices is expected to have large influence on the local stresses in the passivation layer too. As an example, a model is employed to represent a cross-section of the IC to find this influence by varying the dimensional parameters and to quantify the stress occurrence during each step of the whole building process. From the stress distribution we can analyze the geometry sensitivity of micro-structures of IC packages on passivation cracking and find the dangerous designed structure schedules out so that to draw out some useful design rules for next generational products.
Key Engineering Materials Vols. 297-300 (2005) pp 819-824Online available since 2005/Nov/15 at www.scientific.net© (2005) Trans Tech Publications, Switzerlanddoi:10.4028/www.scientific.net/KEM.297-300.819
All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of TTP,www.ttp.net. (ID: 128.42.202.150, Rice University, Fondren Library, Houston, USA-15/11/14,23:45:32)
Experimental Observations
In order to investigate the “passivation crack” failure behaviour of the package, the defected ones are opened and observed with microscopes [6], as shown in Fig. 1.
Fig. 1 Passivation cracks observation
Methodology
In this paper, to analyze the geometry sensitivity of micro-structures of IC packages on passivation cracking, maximum principal stress theory is employed. The stresses are obtained by means of Finite Element Method using commercial FEM code MSC/MARC.
A two-dimensional model is employed to represent a cross-section of the IC to find this influence by varying the dimensional parameters and to quantify the stress occurrence during each step of the whole building process.
Fig. 2 Typical evaluated FEM geometry of IC package Fig. 3 Typical FE meshes of dielectric layer
Finite Element Models
Typical FE Meshes. We use two-dimensional plane strain FE models to perform the simulations. The evaluated geometry is visualized in Fig. 2 which shows a local part of the interconnect structure on the die. In this model, there are 5 layers on the silicon substrate consisting of metal and dielectric materials in the interconnect structure and a compound layer on top. Due to the large range in dimensions the mesh density (50nmx50nm) is much larger in the interconnect layers than in the silicon and compound layers. The typical FE meshes of dielectric layer and metal line are shown in Fig. 3. Here TiN is used to be instead of Ti material in calculations.
Geometry. In these calculations, model parameters are categorized into constant and varying parameters, shown in Table 1.
820 Advances in Fracture and Strength
Table 1 Geometrical parameters of the 2D models
material symbol value or varying range [mm]
Fixed parameters lower boundary Upper boundary
Silicon thickness Si t_Si 0.38
Al layer thickness Al T_Al 0.88e-3
TiN layer thickness TiN t_TiN 30e-6
Analysed package length L 15
Metal line width Al w 3.20e-4 2.0e-2
Compound thickness epoxy t_epo 0.2 1.5
Dielectric thickness dielectric t_Teos 2.0e-4 8.0e-4
Metal line pitch d 1 10
Fig. 4 Thermal loading schematics
Table 2 Materials properties and models [7-9]
Material E [MPa] ν [-] CTE [e-6/˚C] FEM material model
Isotropic Silicon 169000 0.23 3
Linear elastic
Isotropic Dielectric 70000 0.23 0.4
Linear elastic
Isotropic
Ideal elastic-plastic Al 60000 0.35 20 Temperature dependent
yielding stress
(50 to 300MPa)
TiN 260000 0.25 10.5 Isotropic
Linear elastic
Isotropic Epoxy
Temperature dependent
0.25 Temperature dependent Linear elastic
Boundary Conditions. In the FE simulations, on the left side of the geometry a symmetry
boundary condition is used while the left bottom node is also fixed in y, z-displacements and other three rotating directions.
Key Engineering Materials Vols. 297-300 821
Loading History. A simplified thermal loading is used, simulating the manufacturing processes of the die and package. The thermal loading is simplified to 5 temperature steps as shown in Fig. 4 ( room temperature as the final one in Fig. 4): 1) Cooling down from metal line initiation temperature 400°C to room temperature 25°C (the largest of the back-end process), acting on silicon and metal layers; 2) Heating up from room temperature 25°C to dielectric layer deposition temperature 400°C, for silicon and metal layers; 3) Cooling down from deposition temperature 400°C to room temperature 25°C, acting on silicon, metal and dielectric layers; 4) Heating up from room temperature 25°C to epoxy package temperature 180°C, for silicon, metal and dielectric layers; 5) Cooling down from 180°C to final temperature 25°C. For all materials. Here for all simulations, the intrinsic stresses in the dielectric layers are considered to be zero.
Material Properties. The material properties and models are given in Table 2. In order to acquire reliable material properties of thin films of Teos, PSG, SiON, and metal, material characterisation measurements are carried out.
Fig. 5 The calculation positions for stresses in dielectric layer
Results
Analysed Positions and Fitting Method. For the stresses analysis in dielectrics, here maximum principal stresses along the out left side of dielectric layer (i.e. S1_dielleft_O at P_out point of Fig. 5) and that along internal left side of dielectric layer (i.e. S1_dielleft_I at P_in point of Fig. 5) were displayed out.
For this model, here the design parameters “d”, “w”, “t_epo”, “t_Teos” and the Aluminium yielding stress “sy_al” were employed as the same as the following section.
In order to analyze the impact of design parameters on the stress distribution in dielectric layers, the Response Surface Model [10-13] is used here. A space-filling Latin-Hypercube-Design consisting of 40 variations is first constructed. Using the parametric non-linear FEM models, FEM simulations are carried out for all the 40 designs. The design optimisation problem is to choose the parameters of the package such to minimise the stress values as to maximise the fatigue lifetime, within the specified ranges of design variations. For S1_dielleft_I stress response parameters polynomial models are used for RSM generation while for S1_dielleft_O response parameters kriging models are used. The regression statistics indicated that the reliability and accuracy requirements are accepted, the CV-RSME value is 11.99% for S1_dielleft_O and 8.04% for S1_dielleft_I.
Maximum Principal Stresses. For the models above, the 3D-RSM results of maximum normalized principal stresses along left outside of dielectric layer (i.e. P_out point) are mainly presented following while some special values along left inside of dielectric layer (i.e. P_in point) are with together.
822 Advances in Fracture and Strength
Fig. 6 Max. principal stress along left outside of dielectric layer with “w” and “d”
Fig. 7 Max. principal stress along left outside of dielectric layer with “t_epo” and “t_Teos”
Fig. 8 Max. principal stress along left outside of
dielectric layer with “w” and “sy_al” Fig. 9 Max. principal stress along left outside of
dielectric layer with “w” and “t_epo”
Fig. 10 Max. principal stress along left outside of dielectric layer with “w” and “t_Teos”
Fig. 11 Max. principal stress along left inside of dielectric layer with “t_Teos” and “sy_al”
Summary
From the above analyses, some conclusions can be drawn out. 1) When decreasing “w” value, the maximum principal stress along left outside of dielectric layer will increase promptly, but it will reach the maximum value when “w” equals about 5.0e-3mm. 2) When decreasing “d”, the maximum principal stress along left outside of dielectric layer will increase slowly.
Key Engineering Materials Vols. 297-300 823
3) “t_epo” only has a little effect on the stress level. 4) When “t_Teos” reaches the thinner or thicker thickness, it will increase the maximum principal stress dramatically. 5) When increasing Al yielding stress, it will also increase the maximum principal stress. 6) To the maximum principal stress along the left inside of dielectric layer, decreasing the “t_Teos” will increase the values while “sy_al” has a little influence. 7) Increasing the maximum principal stress value means it’s easy to crack for passivation layers. 8) According to these results, some good design schdules could be drawn out.
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824 Advances in Fracture and Strength
Advances in Fracture and Strength 10.4028/www.scientific.net/KEM.297-300 Geometry Sensitivity Analyses of Microstructures of IC Packages on Passivation Cracking 10.4028/www.scientific.net/KEM.297-300.819
DOI References
[8] D. Nix William and R.F. Mehl Medallist: Mechanical Properties of Thin Film, Metallurgical ransactions
A, Vol. 20A (1989), p. 2217
doi:10.1007/BF02666659 [11] V.V. Toropov, A.A. Filatov and A.A. Polynkine: Multiparameter structural optimization using EM and
multipoint explicit approximations, Structural Optimization Vol. 6 (1993), p. 7
doi:10.1007/BF01743169 [8] D. Nix William and R.F. Mehl Medallist: Mechanical Properties of Thin Film, Metallurgical Transactions
A, Vol. 20A (1989), p. 2217
doi:10.1007/BF02666659 [11] V.V. Toropov, A.A. Filatov and A.A. Polynkine: Multiparameter structural optimization using FEM and
multipoint explicit approximations, Structural Optimization Vol. 6 (1993), p. 7
doi:10.1007/BF01743169
