A short list of embedded systems
1Chapter 3 General-Purpose Processors: SoftwareEmbedded Systems
Design: A Unified Hardware/Software IntroductionEmbedded Systems
Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 2IntroductionGeneral-Purpose ProcessorProcessor
designed for a variety of computation tasksLow unit cost, in part
because manufacturer spreads NRE over large numbers of
unitsMotorola sold half a billion 68HC05 microcontrollers in 1996
aloneCarefully designed since higher NRE is acceptableCan yield
good performance, size and powerLow NRE cost, short
time-to-market/prototype, high flexibilityUser just writes
software; no processor designa.k.a. microprocessor micro used when
they were implemented on one or a few chips rather than entire
roomsEmbedded Systems Design: A Unified Hardware/Software
Introduction, (c) 2000 Vahid/Givargis Processors3
Embedded Systems Design: A Unified Hardware/Software
Introduction, (c) 2000 Vahid/Givargis 4Basic ArchitectureControl
unit and datapathNote similarity to single-purpose processorKey
differencesDatapath is generalControl unit doesnt store the
algorithm the algorithm is programmed into the memory
ProcessorControl
unitDatapathALURegistersIRPCControllerMemoryI/OControl/StatusEmbedded
Systems Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 6Control UnitControl unit: configures the datapath
operationsSequence of desired operations (instructions) stored in
memory program Instruction cycle broken into several
sub-operations, each one clock cycle, e.g.:Fetch: Get next
instruction into IRDecode: Determine what the instruction
meansFetch operands: Move data from memory to datapath
registerExecute: Move data through the ALUStore results: Write data
from register to memoryProcessorControl
unitDatapathALURegistersIRPCController
MemoryI/OControl/Status10......load R0, M[500]500501100inc R1,
R0101store M[501], R1102R0R1Embedded Systems Design: A Unified
Hardware/Software Introduction, (c) 2000 Vahid/Givargis 7Control
Unit Sub-OperationsFetchGet next instruction into IRPC: program
counter, always points to next instructionIR: holds the fetched
instructionProcessorControl unitDatapathALURegistersIRPCController
MemoryI/OControl/Status10......load R0, M[500]500501100inc R1,
R0101store M[501], R1102R0R1100load R0, M[500]Embedded Systems
Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 8Control Unit Sub-OperationsDecodeDetermine what the
instruction meansProcessorControl
unitDatapathALURegistersIRPCController
MemoryI/OControl/Status10......load R0, M[500]500501100inc R1,
R0101store M[501], R1102R0R1100load R0, M[500]Embedded Systems
Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 9Control Unit Sub-OperationsFetch operandsMove data
from memory to datapath registerProcessorControl
unitDatapathALURegistersIRPCController
MemoryI/OControl/Status10......load R0, M[500]500501100inc R1,
R0101store M[501], R1102R0R1100load R0, M[500]10Embedded Systems
Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 10Control Unit Sub-OperationsExecuteMove data
through the ALUThis particular instruction does nothing during this
sub-operationProcessorControl
unitDatapathALURegistersIRPCController
MemoryI/OControl/Status10......load R0, M[500]500501100inc R1,
R0101store M[501], R1102R0R1100load R0, M[500]10Embedded Systems
Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 11Control Unit Sub-OperationsStore resultsWrite data
from register to memoryThis particular instruction does nothing
during this sub-operationProcessorControl
unitDatapathALURegistersIRPCController
MemoryI/OControl/Status10......load R0, M[500]500501100inc R1,
R0101store M[501], R1102R0R1100load R0, M[500]10Embedded Systems
Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 12Instruction CyclesProcessorControl
unitDatapathALURegistersIRPCController
MemoryI/OControl/Status10......load R0, M[500]500501100inc R1,
R0101store M[501], R1102R0R1PC=10010Fetch opsExec.Store
resultsclkFetchload R0, M[500]Decode100Embedded Systems Design: A
Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis
13Instruction CyclesProcessorControl
unitDatapathALURegistersIRPCController
MemoryI/OControl/Status10......load R0, M[500]500501100inc R1,
R0101store M[501], R1102R0R110PC=100FetchDecodeFetch opsExec.Store
resultsclkPC=101inc R1, R0FetchFetch ops+111Exec.Store
resultsclk101DecodeEmbedded Systems Design: A Unified
Hardware/Software Introduction, (c) 2000 Vahid/Givargis
14Instruction CyclesProcessorControl
unitDatapathALURegistersIRPCController
MemoryI/OControl/Status10......load R0, M[500]500501100inc R1,
R0101store M[501], R1102R0R11110PC=100FetchDecodeFetch
opsExec.Store resultsclkPC=101FetchDecodeFetch opsExec.Store
resultsclkPC=102store M[501], R1FetchFetch opsExec.11Store
resultsclkDecode102Embedded Systems Design: A Unified
Hardware/Software Introduction, (c) 2000 Vahid/Givargis
15Architectural ConsiderationsN-bit processorN-bit ALU, registers,
buses, memory data interfaceEmbedded: 8-bit, 16-bit, 32-bit
commonDesktop/servers: 32-bit, even 64PC size determines address
spaceProcessorControl
unitDatapathALURegistersIRPCControllerMemoryI/OControl/StatusEmbedded
Systems Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 16Architectural ConsiderationsClock frequencyInverse
of clock periodMust be longer than longest register to register
delay in entire processorMemory access is often the
longestProcessorControl
unitDatapathALURegistersIRPCControllerMemoryI/OControl/StatusEmbedded
Systems Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 17Pipelining: Increasing Instruction
Throughput12345678123456781234567812345678Fetch-instr.DecodeFetch
ops.ExecuteStore
res.1234567812345678123456781234567812345678WashDryTimeNon-pipelinedPipelinedTimeTimePipelinedpipelined
instruction executionnon-pipelined dish cleaningpipelined dish
cleaningInstruction 1Embedded Systems Design: A Unified
Hardware/Software Introduction, (c) 2000 Vahid/Givargis
18Superscalar and VLIW ArchitecturesPerformance can be improved
by:Faster clock (but theres a limit)Pipelining: slice up
instruction into stages, overlap stagesMultiple ALUs to support
more than one instruction streamSuperscalarScalar: non-vector
operationsFetches instructions in batches, executes as many as
possible May require extensive hardware to detect independent
instructionsVLIW: each word in memory has multiple independent
instructionsRelies on the compiler to detect and schedule
instructionsCurrently growing in popularity
Embedded Systems Design: A Unified Hardware/Software
Introduction, (c) 2000 Vahid/Givargis 19Two Memory
ArchitecturesProcessorProgram memoryData
memoryProcessorMemory(program and
data)HarvardPrincetonPrincetonFewer memory wiresHarvardSimultaneous
program and data memory access
Embedded Systems Design: A Unified Hardware/Software
Introduction, (c) 2000 Vahid/Givargis 20Cache MemoryMemory access
may be slowCache is small but fast memory close to processorHolds
copy of part of memoryHits and
missesProcessorMemoryCacheFast/expensive technology, usually on the
same chipSlower/cheaper technology, usually on a different
chipEmbedded Systems Design: A Unified Hardware/Software
Introduction, (c) 2000 Vahid/Givargis 21Programmers ViewProgrammer
doesnt need detailed understanding of architectureInstead, needs to
know what instructions can be executedTwo levels of
instructions:Assembly levelStructured languages (C, C++, Java,
etc.)Most development today done using structured languagesBut,
some assembly level programming may still be necessaryDrivers:
portion of program that communicates with and/or controls (drives)
another deviceOften have detailed timing considerations, extensive
bit manipulationAssembly level may be best for theseEmbedded
Systems Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 22Assembly-Level
Instructionsopcodeoperand1operand2opcodeoperand1operand2opcodeoperand1operand2opcodeoperand1operand2...Instruction
1Instruction 2Instruction 3Instruction 4Instruction SetDefines the
legal set of instructions for that processorData transfer:
memory/register, register/register, I/O, etc.Arithmetic/logical:
move register through ALU and backBranches: determine next PC value
when not just PC+1Embedded Systems Design: A Unified
Hardware/Software Introduction, (c) 2000 Vahid/Givargis 23A Simple
(Trivial) Instruction Set opcode operandsMOV Rn, directMOV @Rn,
RmADD Rn, Rm0000Rndirect0010Rn0100RmRnRn = M(direct)Rn = Rn + RmSUB
Rn, Rm0101RmRn = Rn - RmMOV Rn, #immed.0011RnimmediateRn =
immediateAssembly instruct.First byteSecond byteOperationJZ Rn,
relative0110RnrelativePC = PC+ relative (only if Rn is 0)RnMOV
direct, Rn0001RndirectM(direct) = RnRmM(Rn) = RmEmbedded Systems
Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 24Addressing
ModesDataImmediateRegister-directRegisterindirectDirectIndirectDataOperand
fieldRegister addressRegister addressMemory addressMemory
addressMemory addressDataDataMemory
addressDataAddressingmodeRegister-filecontentsMemorycontentsEmbedded
Systems Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 25Sample Programsint total = 0;for (int i=10; i!=0;
i--) total += i;// next instructions...C programMOV R0, #0; //
total = 0MOV R1, #10; // i = 10JZ R1, Next; // Done if i=0ADD R0,
R1; // total += iMOV R2, #1; // constant 1JZ R3, Loop; // Jump
alwaysLoop:Next:// next instructions...SUB R1, R2; // i--Equivalent
assembly programMOV R3, #0; // constant 00123567Try some
othersHandshake: Wait until the value of M[254] is not 0, set
M[255] to 1, wait until M[254] is 0, set M[255] to 0 (assume those
locations are ports).(Harder) Count the occurrences of zero in an
array stored in memory locations 100 through 199. Embedded Systems
Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 26Programmer ConsiderationsProgram and data memory
spaceEmbedded processors often very limitede.g., 64 Kbytes program,
256 bytes of RAM (expandable)Registers: How many are there?Only a
direct concern for assembly-level programmersI/OHow communicate
with external signals?Interrupts
Embedded Systems Design: A Unified Hardware/Software
Introduction, (c) 2000 Vahid/Givargis 27Microprocessor Architecture
OverviewIf you are using a particular microprocessor, now is a good
time to review its architectureEmbedded Systems Design: A Unified
Hardware/Software Introduction, (c) 2000 Vahid/Givargis 28Example:
parallel port driverUsing assembly language programming we can
configure a PC parallel port to perform digital I/Owrite and read
to three special registers to accomplish this table provides list
of parallel port connector pins and corresponding register
locationExample : parallel port monitors the input switch and turns
the LED on/off accordingly
LPT Connection PinI/O DirectionRegister Address1Output0th bit of
register #2
2-9Output0th bit of register #214,16,17Output1,2,3th bit of
register #210,11,12,13,15Input6,7,5,4,3th bit of register
#1Embedded Systems Design: A Unified Hardware/Software
Introduction, (c) 2000 Vahid/Givargis 29Parallel Port Example; This
program consists of a sub-routine that reads; the state of the
input pin, determining the on/off state; of our switch and asserts
the output pin, turning the LED; on/off accordingly.386
CheckPortprocpushax; save the contentpushdx; save the
contentmovdx, 3BCh + 1; base + 1 for register #1inal, dx; read
register #1and al, 10h; mask out all but bit # 4cmpal, 0; is it
0?jneSwitchOn; if not, we need to turn the LED on
SwitchOff:movdx, 3BCh + 0; base + 0 for register #0inal, dx;
read the current state of the portandal, f7h; clear first bit
(masking)outdx, al; write it out to the portjmpDone ; we are
done
SwitchOn:movdx, 3BCh + 0; base + 0 for register #0inal, dx; read
the current state of the portoral, 01h; set first bit
(masking)outdx, al; write it out to the portDone: popdx; restore
the contentpopax; restore the contentCheckPortendpextern C
CheckPort(void);// defined in // assembly void main(void) {while( 1
) {CheckPort();}}LPT Connection PinI/O DirectionRegister
Address1Output0th bit of register #2
2-9Output0th bit of register #214,16,17Output1,2,3th bit of
register #210,11,12,13,15Input6,7,5,4,3th bit of register #1
Embedded Systems Design: A Unified Hardware/Software
Introduction, (c) 2000 Vahid/Givargis 30Operating SystemOptional
software layer providing low-level services to a program
(application).File management, disk accessKeyboard/display
interfacingScheduling multiple programs for executionOr even just
multiple threads from one programProgram makes system calls to the
OS
DB file_name out.txt -- store file name
MOV R0, 1324 -- system call open idMOV R1, file_name -- address
of file-nameINT 34 -- cause a system callJZ R0, L1 -- if zero ->
error
. . . read the fileJMP L2 -- bypass error cond.L1: . . . handle
the error
L2:Embedded Systems Design: A Unified Hardware/Software
Introduction, (c) 2000 Vahid/Givargis 31Development
EnvironmentDevelopment processorThe processor on which we write and
debug our programsUsually a PCTarget processorThe processor that
the program will run on in our embedded system Often different from
the development processor
Development processor
Target processorEmbedded Systems Design: A Unified
Hardware/Software Introduction, (c) 2000 Vahid/Givargis 32Software
Development ProcessCompilerLinkerC FileC FileAsm. FileBinary
FileBinary FileBinary FileExec. FileAssemblerLibraryImplementation
PhaseDebuggerProfilerVerification PhaseCompilersCross compilerRuns
on one processor, but generates code for
anotherAssemblersLinkersDebuggersProfilersEmbedded Systems Design:
A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis
33Running a ProgramIf development processor is different than
target, how can we run our compiled code? Two options:Download to
target processorSimulateSimulationOne method: Hardware description
languageBut slow, not always availableAnother method: Instruction
set simulator (ISS)Runs on development processor, but executes
instructions of target processorEmbedded Systems Design: A Unified
Hardware/Software Introduction, (c) 2000 Vahid/Givargis
34Instruction Set Simulator For A Simple Processor#include typedef
struct { unsigned char first_byte, second_byte;} instruction;
instruction program[1024]; //instruction memoryunsigned char
memory[256]; //data memory
void run_program(int num_bytes) {
int pc = -1; unsigned char reg[16], fb, sb; while( ++pc <
(num_bytes / 2) ) { fb = program[pc].first_byte; sb =
program[pc].second_byte; switch( fb >> 4 ) { case 0: reg[fb
& 0x0f] = memory[sb]; break; case 1: memory[sb] = reg[fb &
0x0f]; break; case 2: memory[reg[fb & 0x0f]] = reg[sb >>
4]; break; case 3: reg[fb & 0x0f] = sb; break; case 4: reg[fb
& 0x0f] += reg[sb >> 4]; break; case 5: reg[fb &
0x0f] -= reg[sb >> 4]; break; case 6: pc += sb; break;
default: return 1;
} } return 0;}
int main(int argc, char *argv[]) {
FILE* ifs;
If( argc != 2 || (ifs = fopen(argv[1], rb) == NULL ) { return 1;
} if (run_program(fread(program, sizeof(program) == 0)
{print_memory_contents();return(0); } else return(-1);}
Embedded Systems Design: A Unified Hardware/Software
Introduction, (c) 2000 Vahid/Givargis 35Testing and Debugging
Implementation Phase
Implementation Phase
Verification Phase
Verification Phase
EmulatorDebugger/ ISSProgrammerDevelopment
processor(a)(b)External toolsISS Gives us control over time set
breakpoints, look at register values, set values, step-by-step
execution, ...But, doesnt interact with real environmentDownload to
boardUse device programmerRuns in real environment, but not
controllableCompromise: emulatorRuns in real environment, at speed
or nearSupports some controllability from the PCEmbedded Systems
Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 36Application-Specific Instruction-Set Processors
(ASIPs)General-purpose processorsSometimes too general to be
effective in demanding applicatione.g., video processing requires
huge video buffers and operations on large arrays of data,
inefficient on a GPPBut single-purpose processor has high NRE, not
programmableASIPs targeted to a particular domainContain
architectural features specific to that domaine.g., embedded
control, digital signal processing, video processing, network
processing, telecommunications, etc.Still programmableEmbedded
Systems Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 37A Common ASIP: MicrocontrollerFor embedded control
applicationsReading sensors, setting actuatorsMostly dealing with
events (bits): data is present, but not in huge amountse.g., VCR,
disk drive, digital camera (assuming SPP for image compression),
washing machine, microwave ovenMicrocontroller featuresOn-chip
peripheralsTimers, analog-digital converters, serial communication,
etc.Tightly integrated for programmer, typically part of register
spaceOn-chip program and data memoryDirect programmer access to
many of the chips pinsSpecialized instructions for bit-manipulation
and other low-level operationsEmbedded Systems Design: A Unified
Hardware/Software Introduction, (c) 2000 Vahid/Givargis 38Another
Common ASIP: Digital Signal Processors (DSP)For signal processing
applicationsLarge amounts of digitized data, often streamingData
transformations must be applied faste.g., cell-phone voice filter,
digital TV, music synthesizerDSP featuresSeveral instruction
execution unitsMultiple-accumulate single-cycle instruction, other
instrs.Efficient vector operations e.g., add two arraysVector ALUs,
loop buffers, etc.
Embedded Systems Design: A Unified Hardware/Software
Introduction, (c) 2000 Vahid/Givargis 39Trend: Even More Customized
ASIPsIn the past, microprocessors were acquired as chipsToday, we
increasingly acquire a processor as Intellectual Property (IP)e.g.,
synthesizable VHDL modelOpportunity to add a custom datapath
hardware and a few custom instructions, or delete a few
instructionsCan have significant performance, power and size
impactsProblem: need compiler/debugger for customized ASIPRemember,
most development uses structured languagesOne solution: automatic
compiler/debugger generatione.g., www.tensillica.comAnother
solution: retargettable compilerse.g., www.improvsys.com
(customized VLIW architectures)Embedded Systems Design: A Unified
Hardware/Software Introduction, (c) 2000 Vahid/Givargis 40Selecting
a MicroprocessorIssuesTechnical: speed, power, size, costOther:
development environment, prior expertise, licensing, etc.Speed: how
evaluate a processors speed?Clock speed but instructions per cycle
may differInstructions per second but work per instr. may
differDhrystone: Synthetic benchmark, developed in 1984.
Dhrystones/sec.MIPS: 1 MIPS = 1757 Dhrystones per second (based on
Digitals VAX 11/780). A.k.a. Dhrystone MIPS. Commonly used
today.So, 750 MIPS = 750*1757 = 1,317,750 Dhrystones per
secondSPEC: set of more realistic benchmarks, but oriented to
desktopsEEMBC EDN Embedded Benchmark Consortium,
www.eembc.orgSuites of benchmarks: automotive, consumer
electronics, networking, office automation,
telecommunicationsEmbedded Systems Design: A Unified
Hardware/Software Introduction, (c) 2000 Vahid/Givargis 41General
Purpose Processors
Sources: Intel, Motorola, MIPS, ARM, TI, and IBM
Website/Datasheet; Embedded Systems Programming, Nov. 1998Embedded
Systems Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 42Designing a General Purpose ProcessorNot something
an embedded system designer normally would doBut instructive to see
how simply we can build one top downRemember that real processors
arent usually built this wayMuch more optimized, much more
bottom-up design
Declarations: bit PC[16], IR[16]; bit M[64k][16],
RF[16][16];Aliases: op IR[15..12] rn IR[11..8] rm IR[7..4] dir
IR[7..0] imm IR[7..0] rel
IR[7..0]ResetFetchDecodeIR=M[PC];PC=PC+1Mov1RF[rn] =
M[dir]Mov2Mov3Mov4AddSubJz011001010100001100100001op = 0000M[dir] =
RF[rn]M[rn] = RF[rm]RF[rn]= immRF[rn] =RF[rn]+RF[rm]RF[rn] =
RF[rn]-RF[rm]PC=(RF[rn]=0) ?rel :PCto Fetchto Fetchto Fetchto
Fetchto Fetchto Fetchto FetchPC=0;from states belowFSMDEmbedded
Systems Design: A Unified Hardware/Software Introduction, (c) 2000
Vahid/Givargis 43Architecture of a Simple MicroprocessorStorage
devices for each declared variableregister file holds each of the
variablesFunctional units to carry out the FSMD operationsOne ALU
carries out every required operationConnections added among the
components ports corresponding to the operations required by the
FSM Unique identifiers created for every control
signalDatapathIRPCController(Next-state and controllogic; state
register)MemoryRF
(16)RFwaRFweRFr1aRFr1eRFr2aRFr2eRFr1RFr2RFwALUALUs2x1
muxALUzRFsPCldPCincPCclr3x1 muxMsMweMreTo all input control
signalsFrom all output control signalsControl
unit16Irld210AD10Embedded Systems Design: A Unified
Hardware/Software Introduction, (c) 2000 Vahid/Givargis 44A Simple
MicroprocessorFSM operations that replace the FSMD operations after
a datapath is createdRFwa=rn; RFwe=1; RFs=01;Ms=01; Mre=1;RFr1a=rn;
RFr1e=1; Ms=01; Mwe=1;RFr1a=rn; RFr1e=1; Ms=10; Mwe=1;RFwa=rn;
RFwe=1; RFs=10;RFwa=rn; RFwe=1; RFs=00;RFr1a=rn; RFr1e=1;RFr2a=rm;
RFr2e=1; ALUs=00RFwa=rn; RFwe=1; RFs=00;RFr1a=rn; RFr1e=1;RFr2a=rm;
RFr2e=1; ALUs=01PCld=
ALUz;RFrla=rn;RFrle=1;MS=10;Irld=1;Mre=1;PCinc=1;PCclr=1;ResetFetchDecodeIR=M[PC];PC=PC+1Mov1RF[rn]
= M[dir]Mov2Mov3Mov4AddSubJz011001010100001100100001op = 0000M[dir]
= RF[rn]M[rn] = RF[rm]RF[rn]= immRF[rn] =RF[rn]+RF[rm]RF[rn] =
RF[rn]-RF[rm]PC=(RF[rn]=0) ?rel :PCto Fetchto Fetchto Fetchto
Fetchto Fetchto Fetchto FetchPC=0;from states
belowFSMDDatapathIRPCController(Next-state and controllogic; state
register)MemoryRF
(16)RFwaRFweRFr1aRFr1eRFr2aRFr2eRFr1RFr2RFwALUALUs2x1
muxALUzRFsPCldPCincPCclr3x1 muxMsMweMreTo all input control
signalsFrom all output control signalsControl unit16Irld210AD10You
just built a simple microprocessor!Embedded Systems Design: A
Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis
45Chapter SummaryGeneral-purpose processorsGood performance, low
NRE, flexibleController, datapath, and memoryStructured languages
prevailBut some assembly level programming still necessaryMany
tools availableIncluding instruction-set simulators, and in-circuit
emulatorsASIPsMicrocontrollers, DSPs, network processors, more
customized ASIPsChoosing among processors is an important
stepDesigning a general-purpose processor is conceptually the same
as designing a single-purpose processorEmbedded Systems Design: A
Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis
PC
Parallel port
Pin 13
Pin 2
Switch
LED
PC
Parallel port
Pin 13
Pin 2
Switch
LED
ProcessorClock speedPeriph.Bus WidthMIPSPowerTrans.Price
General Purpose Processors
Intel PIII1GHz2x16 K
L1, 256K
L2, MMX32~90097W~7M$900
IBM
PowerPC
750X550 MHz2x32 K
L1, 256K
L232/64~13005W~7M$900
MIPS
R5000250 MHz2x32 K
2 way set assoc.32/64NANA3.6MNA
StrongARM
SA-110233 MHzNone322681W2.1MNA
Microcontroller
Intel
805112 MHz4K ROM, 128 RAM, 32 I/O, Timer, UART8~1~0.2W~10K$7
Motorola
68HC8113 MHz4K ROM, 192 RAM, 32 I/O, Timer, WDT,
SPI8~.5~0.1W~10K$5
Digital Signal Processors
TI C5416160 MHz128K, SRAM, 3 T1 Ports, DMA, 13 ADC, 9
DAC16/32~600NANA$34
Lucent
DSP32C80 MHz16K Inst., 2K Data, Serial Ports, DMA3240NANA$75
