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Rare data-sheet of the great microprocessor CP1600 from General Instruments which powered the spectacular video game console Intellivision.
Citation preview
7/21/2019 General Instruments CP1600 Datasheet
http://slidepdf.com/reader/full/general-instruments-cp1600-datasheet 1/44
. .
Chapter16
THE
GENERAL
NSTRUMENT
Pl600
The CP1600
and
he TMS
9900 were the
f irst
two
NMOS
16-bit microprocassors
ommericial ly vai lable.
Even
a
superf ic ia lnspect ion
f the
CP1600 hows t
to be
more
powerfu l
han he
Nat ional
emiconductorace
or
8900),
yet
the
CP1600
s not
widely
used.
This
s
because eneral
nstrument
oesnot support
he CP1600
o the extent
that
National
emiconductorupports.Pace,
r
mostmanufacturers
upport heir
8-bi t
microprocessors.
General
nstrument's
marketing
phi losophy
as been
to seek out
very high-volume
ustomers;
General
nstru-
ment
supports
ow-volume
ustomers nly
o
the extent hat
his
support
would not require
ubstantialnvestment
n
the
part
of
General
nstrument.
From
he
viewpoint
f
the
low-volume
microprocessor
ser.
General
nstrument's
arket ing
hi losophy
s unfortunate.
The
CP1600
s an deal
microprocessor
or
he
more
ophist icated
ideo
games
hatareappear ing, nd
ts r ich
nstruc-
t ion set and
capable rchi tecture
ake
t
an ideal
hoice or
data.processingerminals nd home
computer
ystems.
However,ue o i ts imi ted upport , otent ia low-volume P1600 ustomersre ikely o choose nother qual ly apa-
ble
oroduct .
Three
CPl600
parts
are avaitable, i f ferentiated
nly by
the
ctock speeds
orwhich
they irave
been
designed.
The
CP1600
equires
3.3 MHz.
wo-phase
lockand
generates
600
nanosecond achine
ycle ime.
The
CP1600 equi res
4 MHz.
wo-phase lock
and
generates
500
nanosecond achine
ycle
ime.
The
CP'l
' l0
requires 2
MHz.
wo-phase lockand
generates
1
microsecond
ycle i rr,e.
ln
addition
to the
CPl600 microprocess ors hemselves,
the
CPl68O
Input/Output Buffer
(lOB)
is described n
this
chapter. Additional
support devices
for
the CPl600 may be found in Volume
3.
The
sole
source
or
the CP1600
s:
GENERALNSTRUMENT
M
croelectronics
vision
600
West
John
Street
Hicksv i l le , ew York 11802
There
s
no secondsource
or
the CPl600. Generalnstrument
asa
pol icy
of
discouragingecond ources
or i ts
product
ine.
The
CP1600
s abr icated s ing
NMOS
on
mplant
LSI
echnology:he device
s
packaged
s a
40-pin
DlP.
Three
power
suppl ies re required' .
12V,
*5V
and
-3V.
THE
CP1600
MICROCOMPUTER
YSTEM
OVERVIEW
Logic
of our
general
microcomputer system which
has been
implemented
by
the cP1600 cPU is illustrats d in
Figure16-1.
obs.ervethat thecP16oorequi resexternal |ogic tocreatei tsvar ioust imingandc|ocksigna|s.
Some bus nterface
ogic
s
shown as
absent
becausaa number
of
devices
must
surround
he
CPl600; these
nt l
'c
uoe:
a
1) An
address
uf fer . ince
dataand addresses
remul t ip lexed
n
a s ingle
16-bi t
bus.
2l
Buffer
ampl i f iers
o
provide
he
power
equired
y
the type
of
memory
nd
/O
devices
nat
wi l l normal ly e con-
nected
o
a CP1600CPU.
3) A
one-of-e ight
ecoder h ip to create
ight
ndiv idual
ontro l
ignals
ut
of three ontro ls utput
by
the
CP1600.
4J A
one-of-s ix teen ul t ip lexchip to
funnel
s ix teen
external
tatuss ignals
nto
the
CP1600
f us ing external
b
anches.
ro-
|
7/21/2019 General Instruments CP1600 Datasheet
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were
you
o
compare
igure
6-1
w'r th
n
equivalent
igure
or
a low-end
microprocessor
uch
as
he
SC/Mp
escr ibed
n
cnapter
3) ,
t recP'1600
might
appear
o
of fer ewer
ogic
unct jons;
ut wi th in
he funct ions
t
ide.
the
CF1600 prov iCes
considerably
more
logic
and
prcgram
execut ion
capabi l i t ies
Where
microprocessors
hoose
o co^dense
nto
a
single
hip l
s impie
mplementat ions
f d i f ferent
ogic
unct ions.
roducts
uch
as
the
cP16c0
choose
o
provide
more
devices
wi th
greater
apabi l i t ies
n
each
device
twhich
is
does pro-
low-end
hig
h-end
[]
fl
Clock
Logic
cP1600
PU
cP1680
/O
Arithmetic
and
lna i r I l ^ i+
svvre
v"rr
Interrupt
Prior i ty
Arbit rat ion
Serial to Paral le l
Interface Logic
ROM
Addressing
and
:
Interface
Logic
l,/O
Ports
Interface Logic
RAM
Addressing
and
Interface
Logic
l r
o
Frgure
6-1
Logic
of
the
Cp
1
600
CpU
and
CP1680
lo
Buf fer
to-z
7/21/2019 General Instruments CP1600 Datasheet
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CPl
600 PROGRAMMABLE
EGISTERS
The
CPl600
has
eight
16-bit
programmable
egisters,
which may be illustrated
as follows:
RO
R' )
RZ
)
Dcta Countcrs
R3 ,
Rl
I
Oau Countc6 whh
R5
t
suto-incramcnt
RO
Stack Pointcr
R7
Program
Countcr
Cacral h.rrpora irgistcrs
The
way in'which
he
registers
l lustrated
bove
are
used
s
unusual
when
compared
o other
microcomputers
e-
scribed n
this
book.
Al l
eight
16-bi t
registers
an be addressed s
though they
were
general
purpose
egisters;
however,
nly
Register 0
hasno
other
assignedunction.We
may
hereforeookupon
Register 0
as
he
Primary c-
cumulator
or
this CPU.
Registers 1,R2,
and
R3
serve
as
general
urpose
egisters,
ut
may
alsobe used
as
DataCounters.
In
addit ion
o servingas
general
purpose
egisters, 4
and
Rb
may
be used as auto-incrementing ata Counters.
Memory
eference
nstruct ions
hat
identi fyRegister
4
or
R5
as holding
he
impl iedmemoryaddress i l l
cause he
contents
f
Register
4
or
R5
o be
ncremented
after
he memory eferencenstruct ions
avecompleted xecution.
Registers
6
and
R7,
n
addit ion o
beingaccessible
s
general urpose
egisters,
lsoserve
s a Stack
Pointer
nd a
Program
Counter, espectively.
Having
he Stack
Pointer
ccessible s a
general urpose
egistermakes t
quite
simple
o
maintainmore
han one
Stack n
externalmemory; lso,
ou
can easi ly ddress
he
Stackas
data
memory
using he
Stack
Pointer
s a Data
Cou ter.
Having
he
Program
Counter ccessibles
a
general urpose
egister
an be
useful
when
executing
arious
ypes
of
condi t ional ranch
ogic.
Whi le
having
he
Stack
Pointer
nd
the
Program
ounter ccessible
s
though
hey
were
general urpose
egisters
may
appear
trange.
his
is
a
feature
f
the
PDP-I1
minicomputer
and is
a very
powerful
programming
ool.
CP1600MEMORYADDRESSING ODE
The
CPl60O addressesm€mory and l /O devices
within a
single
address
space.
Whan
referencing
xternal memory,
you
can use
direct addressing,mpl ied
addressing,
r
impl ied addressing
with
auto-incremsnt.
Direct
addressing nstructions are all two or more
words long, where
the second
or
last
word
of
the instruction
object code
provides
a
16-bit
direct
address.
CP1600
di rect
addressingnstruct ions
re
compl icated
y the
fact
that
CP1600
program
memory
s requently
nly
10
bits
wide.That
s
o say,
even hough
he
CP1600
s
a
16-bit
microprocessor,
ts
nstruc-
t ion
object odes
re
only
10
bi ts
wide. f
program
memory
s
only
10
bi ts
wide.
hendi rectaddresses
i l l
onlybe
10
bi ts
wide.
A
10-bi t
d i rect
address
i l l
access
he
i rs t '1024words
of
memory
nly.
CP1600 DIRECT
ADDRESSING
t
16-3
7/21/2019 General Instruments CP1600 Datasheet
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Were
-u, :u
o
implement
16-bi twide
program
memory,
hen
you
coulddi rect ly ddress p
to
65,536words
of
memo-
ry:
hcv'rever,
ix bi ts
of
the
f irst
oblect
program
word or
every
nstruct ion
n
program
memory
would
be wasted.
his
mav
be
i l lust rated
s
ol lows:
Program
Memory
O
{--
Bit Number
Three memory
reference
instructions
that specify
direct addressi
Six unused
birs
n
each
of these
memory locations
Instructions
that reference memory
using implied
addressing
identify
general
purpose
Register
Rl, R2.
or
R3 as containing
he impl ied
address.
A
memory
eferencenstruct ion
hich identi f ies
Register
R4
or
R5
as
providing
he external
memory
ddress i l l
always ause
Register 4
or
R5
contents o
be
incremented
ol lowing
he
memory
ccess;
hus
you
have mpl ied
memory
addressing
ith
auto-increment.
Memory
reference
nstruct ions
hat specify mpl ied
memoryaddressing ia Register
1,2,3,4,
or 5 can
access
8-bi t memory.An
SDBD
nstruct ion xecuted ir ect ly
efore
val idmemory eferencenstruct ion
orces
he
memory
referencenstruct ion
o
access
memory
one
byte
at a
t ime.
f
impl ied
memoryaddressing
ia
Register
,
2.
or
3 is
specif ied.
hen the
samebyte of
memory
wi l l
be
accessed
wice.
For
an
instruct ionhat loads he contents f data
memory
nto
Register
O.
his
may
be
i l lustrated
s
fol lows:
SDBD
MVI RI,RO
Programmemory
PP
oo
Data
memory
cP1600
IMPLIED
ADDRESSING
Memory
=
I
I
Two
single
word
instructions
16-4
7/21/2019 General Instruments CP1600 Datasheet
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l f
Register
4
or
R5
provides
he
impl ied
memory
ddress
or
the
instruct ion
hich ol lows
n
SDBD nstruct ion.
hen
the
mplied
memory
ddress
s
ncremented
wice,and
wo sequentialow-order
ytesof
dataareaccessed.
or
an in-
struct ion
which
loads
data
nto
Register 0,
his
may
be i l lustrated
s
fol lows:
SDBD
MVI R5,RO
Program memory
PP oo
Data
memory
The
SDBD nstruct ionmay
low-order
byte
of the
next
also
precede
n
immediate
nstruct ion. ow
the
two
sequential
rogram
memory ocatio ns. his
immediate data
wi l l
mav
be
i l lustratedas
be
fetched
rom
the
fol lows:
XX
Without
he
preceding
DBD
nstruct ion.n immediate
nstruct ion
i l l
access
he
nextsingle
program
memory
word
to
f ind
the
requi red
mmediate
ata.
Ten
or
more
bits
of
immediate
ata
wi l l
be accessed.epending
n
the
width
of
program
memoryworos
The
GPl6O0
has no Stack
raference
nstructions
such as
a Push
or
Pull;
rather,
a
variety of
momory
reference
instructions
can
identify
Register
R6 as
providing
the
implied address.
When
RegisterRO
provides
he
impl ied
address.t is treatedas an upward migrat ingStack
Poir i ter.
When
a
memorywri te
operat ion
pecif ies egrster 6
as
providing
he
impl ied
memory
address.
RegisterR6
contents
wi l l
be
incremented
ol lowing
he memory
wri te.
A
memory ead
specif ies
egister 6
as
providing
he
impl ied
memory
address
wil l
cause he contents f
Register
mented
before
he
read
ooerat ion
ccurs.
An
unusual
eature of the
CPl600
is
the fact
that
a
variety
of secondarymemory
reference
nstructions
can
also
reference
memory via the
Stack
Pointer.When
these
nstruct ions
re executed.
egister 6
contents
re
decre-
mented
before
he
memoryaccess ccurs as
hough
a
Pul l
operat ion
rom
he
Stack
were
beingexecuted.
Logical ly,
egister
6.
he
Stack
Pointer,
s
being
handled s though
t were
a
DataCounter
with
post- increment
nd
pre-decrement.
RO
cP1600
STACK
ADDRESSING
instruct ion
hat
R6
to
be decre-
t
Memory
Memory
I o-5
7/21/2019 General Instruments CP1600 Datasheet
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0
0
0
n
0
0
X
X
A
A
A A
B
B
FI
B
B
B
tt
Jur:r
inStrr
( , ' t tOnS
SedireCt
memOry
addreSSing.
ump
inStruCttOnS
€ornDuteci
rom
the second
and
third memory
words
as
fol lows'
are
al l
three
words
ong.
The
di rect
address
s
JR
or JSR
Word
2
Word
3
AAAAAABEEBBBBBBB
ump
address
binary)
yy
are
enable/disable
its for
interrupts
xx
ioentify
the
register
where
the return
address wilr
be
stored
for
JSR
xx
and
yy
are
described
n
detdil n
Table
16-4.
You
can
enable
r d isable
nterrupts
henever ou
execute
Jump
or
Jump-to-subrout ine
nstruct ion.
The
only
di f ference
etween
Jump
nstruct ion
nd
a
Jump-to-Subrout ine
nstruct ion
s
hat
he Jump-to-Subrout ine
instruct ion
aves
he
Program
ounter
contents
n
Register
,5.
or
6.
The
wo high-oider
i ts
xx)
or he
second
ump-
to-Subroutine
bject
code
word
specif ies
hich
of
tne
three egisters
i l l
be used
o
hold
he
return
address.
Jump-to-Subrout ine
nstruct ions.
ike
he Jump
nstruct ion,
l low
di rect
memory
addressing
nly.
CP1
600
STATUS
AND
CONTROL
FLAGS
The cPl600 cPU has four of the standard tatus ftags; n addit ion, t has some unusual
ontrol
signals.
These
are
the
four
standard
status
flags:
s ign
fs)
This
status
s
set
equal
o
the high-order
i t
of any
ar i thmet ic
zero
z l
rhis
status
s
set
o
' l
when
any nstruct ion's
xecution
reates
resu
t
The
Carry
C)
and
Overf low
O)
statuses
re
standard
arry
and
overf low,
s described
n
Volume
1.
Four
control
signals
EBcAo
- EVcA3l
are
output
during
a Eranch-on-Externa t
BExn
instruct ion.
hese
our
sig-
nals
re
output
o
ref
ect
he
ow-order
our
bi ts
of
the
BEXT
nstruct ion's
bject
ode.External
ogic
eceives
hese
our
s ignals
nd
(depending
on
thei rs tate) .
may
or may
not
return
high
nput
v ia
EBCI.f
EBcl
s re iurned
igh.
hen
he
BEXT
nstruct ion
i l l
per form
branch;
f EBCI
s eturned
ow,
hen
he BEXT
nstruct ion
i l l
cause
he
next
sequent ia l
inst ruct ion
o
beexecuted.
he
our
contro l
ignals
BcAo EBCA3herefore rov ide hecp1600wi tha means f test-ing 16 external
ondi t ions.
CP1600
CPU
PINS
AND
SIGNALS
CP1600
CPU
pins
and
signals
are
i l tust rated
n
Figure
16-2.
D0
-
D15
is a
mul t ip lexed
Address
and Data
Bus.
Given
tota lof
40
pins
n
a
package,
p1600
designers
ave
been
forced
o share
6
pins
between
ddresses
nd
data.
Three
controt
signals,
BDIR,
BC1,
and
BC2,
denti fy
he
traff ic
on
the Address/Data
Bus.
External
logic
(one
MSI
chipl
must decode
these
three
signals
o
create
eight
controt
signals,
as
summarized
n
Table
16-1.
Remaining
signals
may
be
divided
into
four groups:
timing,
status/control,
interrupt,
and
DMA.
Two
timing
clock
signals
are
required:
@1and
@2.These
re
complementary
lock
signals
hich
may
be l lustrated
as
ol lows:
Q2
a=.-
operat ion esult .
zero esu
t.The
status
s
set
o
0 for
a
nonzero
o1
r
6-6
7/21/2019 General Instruments CP1600 Datasheet
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EECl
MSYNC
8C1
rcz
80lR
nr (
o1 4
ol 3
D1 2
ur I
D9
o8
oo
D7
06
o5
D4
D3
rclT
GNO
ol
o2
vDD
vBB
vcc
BDRDY
ffi
BUSRO
HALT
BUSAK
INTR
]ffi
TCI
EECAO
E8CA1
EBCA2
EBCA3
D2
Pin ?{ame
DO Dr5
BO|R,cr, BC2
ol.
(D2
MSYNC
EBCAO EBCA3
E_ g
rcrT
BDRDY
STPST
HALT
ivfi.ffi
tu
ffio
BUSAK
vB&
vCC.
VDO, GND
O€scriotion
Data and Addrass
Bus
Bus control signsls
Oock signals
M st6r
Synchronrzltbn
Exrernrl brsnch cdndnbn
sddrass
lirE3
E.rr6msl bronch
co.rditbn
input
Program
Countr inhitit/softwao
imemrol
spnal
WA]T
CRJ stop or
stan on
high-to-bw rrrnsition
HEh
ststs signll
lntorrupt roqucst linas
Tcrminate
currcnt intcrrufri
&:s roguest
Enemal
bus cofltrol rcknourt€dgo
Power
rnd Ground
Tvpc
TnstEt., Elidirecrionrl
Output
lnput
Inp{Jl
Output
lnput
lnput
Input
Inpur
OutPut
lnput
Output
Input
Output
r40
239
338
13 7
536
635
734
833
932
r0
cPt6m
31
11 CPU 30
12
29
13
zg
14
27
15
26
16
zs
17
24
18
23
ts
22
?o
21
Figure
16-2.
CP1600
CPUSignals nd
Pin Assignments
MSYNC
s a somewhatunusual ignal,
as compared
o
other
microcomputer
lock
signals n this
book.
Fol lowing
powerup,
Mff i must
be held
ow or at
least
10
mil l iseconds.
n he subsequent
ising
dge
ofWTie.
logic
nter-
nal
o
the
CP1600CPU
wi l l
synchronizehe
O1
and O2
clock
signals
o
star ta new machine
ycle.
Most
of
the CPU
deviceswe
havedescribed
n
this
book
use
a
reset
ignal.
r
have nternal
owerup
ogicwhich
perfofms
his clock
synchron
zation.
Now
consider he status
and control
signals.
First
f
al l .
here are
he four
control
outputswhichwe
havealready escribed:
BCAO EBCA3.There s
one
con-
ditional
Branch nstruction
(BEXT)
which will
only
branch f a
high signal
is input via EBCI.When
the
BEXT
n-
struct ion s executed.he low-orderour BEXT nstruct ion bjectcodebits are outputvia EBCA0 EBCA3. xternal ' '
logi i
is
supposed
o
decode hese
our
signals y
whatever
means ie appropriate
and
thencedetermine
hether
EBCI
hould
be
nputhigh
or
ow.
A
high
nput ,aswe
have
ust
stated,
i l l resul t n a
branch;
low nput
wi l l
cause he
next
sequent ia lnstruct ion
o be executed.
In real i ty ,
here
s
no
connect ion
i th in CP1600
CPU ogicbetween
he
EBCI
nput
and
he
our EBCA0 EBCA3 ut-
puts.
So ar
as
external
ogic
s
concerned,he execution
f
a
BEXT nstruct ions
denti f ied
y
signal
evels
utput
and
mainta ined
n the
EBCAO
EBCA3
utputs,
whi le
he EBCI
nput
determines
hether
branch
wi l l
or
wi l l not
occur.
How
externalogrc
hooseso
determine
hether
EBCI i l l
be
sethigh
or
low s
entirely p
to
external
ogic.
he
only
vi tal unct ion
served
v
EBCAO EBCA3
s
to
identi fy
he
instantat
which
a BEXT
nstruct ions executed.
Another
unusual
ontro l
s ignalprov ided
y the
CPl600 isEiT; th is
s
a bid i rect ionals ignal .
hen nput
ow,
his
signal
prevents
he
Program
ounter
rom
being ncremented
ol lowing
n instruct ion
etch.Thissignal
s
alsooutput
as
a low
pulse
ol lowing
xecut ion
f
a sof twarenterruptnstruct ion
nstructron
imingseparates
he act ive
nput
and
1
6-7
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aci ive
output
of
th is
s ignal ,
rov id ing
xterna
oEic
dheres
o
trming
equrrements.
conf l rc t etween nput
and
cut-
pui
logic
wi l l
never
ar ise.
BDREY
s
equivalent o the
WA]T signal
we have
described
or
a number
of othe r microcomputers.
GF,s
in-
put
low
by
any
external
ogic
v, 'n ichequi res
cre
ime
n
order
o
respcnd
o an
l , 'O
access
Recal l
hat the
Cp1600,
uses
a s ingleaddress
oace
c
reference
emcry
r
IZQ
srraes
The
E'5Ftr
s icnal
auses
he
CPU
o entera
\ \ /ar t
s tate
or
as ongasETHff is
:erng
nput
o 'r" :
cwever
durrng he
Wart
stateCPU ogrc s
not
re ' reshed
Tnus
a
' , \ /ar t
s ta ie
cannot
ast or
mcre
han
40
microseconds.
r
the conients
{
internal
CPU
ocat ions
rl l
be
lcst
STPS-f l
Hal t /Reset
nput ,
s
anedge-t r iggered
ignalWhen
external
ogic nputs
high-to- lcw
ransi t ion
iaf f i
the
CPU
wi l l
complete
xecutron
f
any
nterrupt
nstruct ion
hen
wil l
ente 'a
Hal t
s tate
and
output
HALT
hrgh
l f
a
nnn-rntarnrnt2hlc natruCt iOn
Sbeing exeCuted.hen the Halt Statewi l l nOtberng unlr lCOmplet ionOf next interruptable
rnstruct ion's
execut ion.
The Halt
state
wi l l last
untr l
external
logrc inputs
another
high-to- lowff i
t ranst t ion.
at
which
t ime
the
Halt
output
wi l l
be
returned
low
and normal
programmrng
execut ion
wr l l
cont inue. Execut ion
of
the
HLT
rnstruct ion
aiso
causes he
CP1600
to enter a Halt
state.
as
descr ibed
above
Let
us now
look
at
interrupt
signals.
The
CP1600
has
two interrupt request inputs
-
INTR
ana lffiT.
lf f i
has
higher
prioriry
than
lffiRT lTfiR-
can-
not
be disabled Typical ly,TNTH"wi l l
be used
to t r igger an
interrupt
upon
power
fai lure
or other catastrophes.
The
interrupt
acknowledge
signal
is created
by external
togic
which
must decode
the BC1 BCz,
and
BDIR
sig-
nals,
as
shown in Table
16- ' i
Observe hai there
are,
in
fact .
two
interrupt
acknowledge
signals:
the
f i rst
i INTAK)
acknowledges
he
interrupt tsel f .
whi le
the second
DAB)
s
used
as a strobe
or
external ogrc
o
return
an
Interrupt
ad-
dress vector .
The
interrupt
sequence
s
descr ibed ater in
thrs
chapter
The CP1600 has two addit ional nterrupt-related ignalswhrch are unusual when compared to other microcomputers
descr ibed
n
this boox
TCI
is
output high
when
an End-of- lnterrupt nstruct ion
s
executed.
This
srgnal
makes
t
easy
for
external
logic
to
.rpnorzto;nrorr , ,nr r ;61i1igg
hich
extend across
he execut ion
of an
interrupt
service
out ine.
We
have
discussed
his
vPr
Y'l
subject in
some
detai l
whi le
descr ib ing
he
8259
Pr ior i ty
nterrupt
Control
Unit
in
Chapter
4.
Table
16-1
CP1600
BusContro l
S ionals
DL I
BC2 BDIR
SIGNAL
FUNCTION
0
n
n
1
1
'I
1
n
'l
'i
0
0
1
,]
1
0
1
0
1
n
,l
NACT
BAR
IAB
DWS
ADAR
DW
ut6
INTAK
The
CPU is inact ive
and
the Dara/AddressBus
is in
a hrgh
impe-
oance state.
A
memory
address
must
be
input
to the
CPU via
the
Data/Address
Bus.
Acknowledged
external
interrupt
request ing
ogic
must
place
the
star t ing
address
or
the
rnterrupt
service
out ine
on the
Address
Bus.
Data wr i te
strobe
for
external memory.
This
signal dent i f ies
a t ime interval
dur ing whrch
the
Data/Address
Bus is f loated.whi le
data input
on the
Data Bus
s
being
interpreled
as
the
effect ive
memory
addressdur ing
a direct memory
addressing
oPerat ion.
The
CPU
is wr i t ing
data
into
external memory
DW wi l l
preceoe
DWS by one machine cycle.
This
is
a
read
strobe
which
external
memory
or
l /O
logic
can
use
in
order
to
place
data
on
the DatazAddress
Bus
This
is
an
interrupt
acknowledge
signal
l t
is fo l lowed
by
IAD
which
is
a
strcbe
el l ing
the external
ogic
which is
being acknowledged
to
ident i fy
tsel f
by
placing
an address ector
on the
Data/AddressBus.
1
6-8
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MC
ll
rr i r2 i . r3
t l
Undefined
state
preceding
data
output
I
T1tT2
I
I
T3lT4
I
Fioure16-3.
CP1600
Machine
Cvcles
nd BusTimino
)
BAR
MC1
ll l
11i 12: '
13114
NACT
MC 2
DTB
MC3
rr l
12i 13l to
r l l
r l l t t l13
I r
Instruction
address out
Instruction
obiect code
in
Frgure
6-4.
CP1600
nstruct ion
etchTimrng
16-9
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I
TEMoRY
EAD
I
aan
I
NAcr
I
DTB
I
MC1
|
MC2
|
MC3
l l i t l l i r l r r i
I
' i
zi .
i ' r i
r rz l
s l el l
rz l
s
'o
I
I
I
I
'l
DTB
MC3
INSTRUCTION
ETCH
NACT
MC 2
NACT
tt l
tr l
- . t-^ l -4.- ,
il
rz l
lJ l l . i
lt l
I
-^
t -
l J l
I
I
,,i*1,'i,,
2
BAR
r
Mc1
I
, ,1,"1, ,1. ,1
I t l l
Data
n
ata
address out
Fi^, , .a 1A-E r .p1Ann
Timing for Memory
Read
nstruct ion with
lmpl ied Memory Addressing
CP1600 INSTRUCTION IMING AND EXECUTION
CP1600
nstruct ions re executed
as a sequence
f machine
ycles.Eachmachine ycle has our clock
periods,
as i l lust rated
n Figure16-3. Machine yc les re
dent i f ied
y
thei r
cyc le
number
and by the
evels
f
the
BC1.BCz,
and
BDIR
ignals. ach
f the
eight
evel ombinat ionss
given
a
name.
aken
romTable '16-1.h isname
becomeshe
name
cf the machine
ycle
Thus n
Figure 6-4.
nd
n
subsequent
nstruct ion
iming
l lustrat ions.ach
machine y-
cle
is identi f ied
by a signal
name from Table 16-1.
Figure 6-3
shows
eneral
ase
iming
or
data
outputor
nput
on
the
Data/Address us. n
between
ata
nput
or out-
put
occral ionshe bus
s
f loated.
CP1600
MEMORY ACCESS
TIMING
Figure
16-4 l lustrates nstruct ion
etch t iming or a
CP160O
nstruct ion's
xecution.
Threemachine
ycles
re
e-
att ' roA l-)" . ina thc f rg l
maChine
CyCle
an addreSS
S
Output.
NOthing happens
during the SeCOnd
maChine CyCle;
i t
is
a
v"ev
"r rmr qn:ninn"
m:nhiqg
cycle that
rout inelyseparates
wo
CP
1
600 Bus
access
machine
cycles.
The
object
code
for
the
accessed
nstruct ton
s returned dur ing
the third
machine
cycle
Figure
16-5
i l lustrates t iming
for the simplest
memory read
instruct ion's execut ion.
In
this
case he
data
memory
address s
taken
rcm
one of
the
CPU registers.
here
s
no di f ference
between t imrng
for
the
three
machine
cycles of
an
instructrcn
[etch
c:
a data
memory read.
As
i l lustrated
n
Figure
16-5.
a simple
memory read
instruct ion's
execut icn
ccnsisls
of two three-machine
cycle
memory read
operat ions.
eparatedby
a
spacing
no
operat ion
machine
cycle
to- tu
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MEMORYWRITE
NSTRUCTION
ETCH
BAR
NACT DW DWS
McrlMczlMc3lMc4
l r l r t t l . r l l t r l
rr
rzi,m
r+l r
I
z
rslrcl
rlrzl s
rrlrr
,rz
s
rc
l la l t r r l l l l l l l l
NACT
t: l
lr l
T1
i:T2
T3
1
a
lt l
BAR
NACT
DTB
Mc1
frv/ lczlMca
I
l t
l t
|
l l t
|
|
rr
rz
i ' .
. l l i
rz
i*
i*lrr
z
ra
rc
Data
address out
Data
out
Figure 6-6.
CP1600
iming
or Memory
Wri te Instruct ion i th
lmpl ied
Memory
Addressing
Figure 16-6
illustrates timing for a simple CPl60O
memory write instruction
execution.
Data
s
output
for
two
machine
ycles,
iv ing
external
ogic
ample
ime o
respond
o the
data
output.
External
ogic
uses
he
DWS machine
cycleas a wri te strobe.
i
Any
memory
eferencenstruct ion
hat
specif ies irect
memory ddressing
i l l require
ne hree-clock-period
achine
cycle
o
fetch
eachword
of the
nstruct ion
bject ode;an
NACT
clock
period
wil l
seperale ach
machine
ycle.
After
the
irst
nstruct ion
etch machine ycle.
n
AD,AR-NACT
lock
period
ombination
i l l
be
nsertedn
the
second
and
thi rd. f
presend
nstruct ion
etch machine
ycle.
Dur ing
an
ADAR
clock
per iod.
C1 s
high.
whi le
BC2and
BDIR
re
low. No
other control signals
are active.
Thus,
for
a two-word memory read or memory
write instruction
that
specifies
direct
addressing, he
following clock
periods
and machine cycles will be required or instruction ex-
ecution:
Direct Addressing
Memory Read
Machine
Cycles
Direct
Addressing
Memory Write
MachineCycle
Fetch
irst instruction
obiect code word
OTB
DTB
NACT
-Spacing
machine
ycle--=-*NACT
BAR
r z
BAR
NAcr
| |
r'racr
ADAR
{-Fetch
second
nstrucriong<
ADAR
NACT
I
object
code word
|
ruaCr
DTB
,/
\
DTB
NACT*-Spacing machine
cycle----*
NACT
BAR
)
Memory
ead Memory
write
(:,11,
NACT
>
<-machine
cycte
machine
rcre--)i
;**
DTB
, DWs
16-11
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t l l
Tl lTz l tg l ra
t
I
t '
l r
Figure 6-7.
CP1600Wai t
StateTiming
THE
CPl600 WAIT STATE
The
CPl600 has
a
Wait state
equivalento those
escribed
or
other
microcomputers
n
thisbook.External
ogic
hat
requi res
more
ime o
respond
o
an access
must
nputEDRDY
ow before
he end
of the
BAR
machine
ycle,dur inq
which
an
addresss
output
and
the
device
s
selected.
iming
s
i l lust rated
n
Figure
16-7.
l f
you
examine
igures
6-4.
16-5
and
16-6.
ou
wil l
see hat
an address
s
output
dur ing
a
BARmachine
ycle o
ini t i -
ate
anyexternal
evice
ccess.
heBARmachine
ycle salways
ol lowed
y
an NACTmachine
.ycle;
n
he
middle
of
T1
dur ing
his
NACT
machine
ycle,
heCPl600samplesf f iRDT {B-5 'FDY
s ow.
hen
a
sequence
f
NACT
machine
cyclescccurs nthemiddleof T4foreveryNACTmachinecycle, theCP1600samplesEDff iTagain.Upondetect
Ef f iDY
high.
he CP1600
esumesnstruct ion
xecut ion
i th
a DTB
machine yc le.
A Wait
state
must last
for less
than
4O
microseconds,
ince he CPl600 is a
dynamicdevice.
THE
CP1
600 HALT
STATE
The
GPl600
hasa Ha lt state which may
ol low
executionof the Halt instruct ion,
r may
be
nit iatedby external
logic.
When
he
Hal t nstruct ions
executed,hen.
ol lowing
he
nstruct ionetch
machine
ycle, he
H,ALT
ignal
s
output
high
and
a sequence
f
NACTmachine
ycles
s
executed.
External
ogic n i t ia tes
Hal t
s tateby making
heSTPSTnput
undergo
high-to- low
ransi t ion
ol lowing
xecut ion f
the
next interruptablenstruct ion, Hal t
s tate
begins
The HALT
signal
s
output
high and
a sequence f
NACT
machine
ycles
s
executed.
,
A
Hal t
s tate.
whether t is n i t ia ted
y
executron f
a
Hal t
nstruct ion
r
by a h igh-to- low
ransi t ion f STPST.
ust
be
terminated y a h igh-to- low
ransi t ion f
STPST.
his
wi l l
cause he
Hal t
s tate
o
end
at the
conclus ion f
the
next
NACT
machrne
ycle.
imrng or
a
Hal t
s tate
which s
ni t ia ted nd
erminated y STPSTmay
be l lust rated s
ol lows:
STPST
HALT
HALT
STATE
16-
12
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tneff is ignat
as an input
nhibi ts
CPl600
ProgramCounter ncrement
ogic.
Thus,
external
.
logic
an
input
PCIT
ow
-
in
which case
he
same nstruct ion
i l l be continuously
e-executed
)
unl i rFCTT
oes
high
aga'n
However.
TTI should
only change
evels
whi le
the
CPU
has
been
'
halted.
hus.PCITand STPST
should
be
used
ogetheras
fol lows:
rcTT
REOUEST
CPl 600 INITIALIZATION
EOUENCE
The CPl600 is initialized
by inputting the
ili$ilC-
signal ow f or a minimum of
1O
millisecondsafter
power
is
first
applied
to
the GPU.
ff imust
make
a
low-to-highransit ion.
arking
he
end
of the
nit ial izat ion,
n
a
rising
edge
of
the
O'l c lock
sig-
nal .
On
the
next r is ingedgeof
@1. nstruct ion xecut ion
i l l begin.
hismay
be
i l lust rated s
ol lows:
MSYNC
When instruct ion
xecution
egins.
nterrupts re
disabled.
he ol lowing
equence f
machine
ycles
s
executed:
NACT
IAB
{-
Read
Data/Address Bus and
load into P rogram Counter
NACT
NACT
NACT
BAR{-Output
Program
Counter contents
to
fetch
first
instruction
NACT
DT B
etc
During
he
IAB
machine
ycle,
x ternal
ogicmust
supply
16-bi t
address t
D0
-
D15.
Your
external
ogic
must
pro-
v ide
his
address.
h ich n
the
simplest
asemay
be
0000
by
grounding
hebus.
or
FFFFl6
y ying
t
to
+5V
fol lowing
a startup.
The
address
hich s input
at
IAB s
output
at BAR. n i t ia t ing
rogram
xecut ion.
CPl600 DMA
LOGIC
CPl609
DMA logic is
quite
standard.
When
extarnal
logic
wishes
to transfer data under
DMA control,
i t inputs
BUSRO
low. At
the conclusion
of
the next interruptable
instruction's
execution, the
CPU
floats the
'Data/Address
Bus
and enters
a Wait state, during
which a
saquenco of
NACT
machine cycles
is executed.
EmT
is
output
low
at
the
beginning
of the
first
NACT mach ine cycle.
The
NACT
machinecycles
hat occur
duringa DMA operat ion
efresh he
CPU.NACT
machine ycles hat
occur
dur inga
Wai t
s tatedo
not
refresh
he
CPU.
his
means
hat any
number
f
NACTmachine
ycles an occur
dur ing
a
DMA
break,whi le a
Wait
state
must be
shorter
han
40
microseconds.
The
DMA
break nds
'g1engternal
ogic nputsE'[SF-O-high
gain.EIISFO-is
ampled uring
1t
of
eveE
PMA
NACT
machine
ycle.
WhenEUSROis
ampled
igh,
wo
addi t ionalNACT
achine yc les
re
executed.hen
BUSAK
s
out-
put
high
and normal
program
xecut ion
esumes.
DMA
timing
is i l lustrated n
Figure16-8.
16- 3
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Last machine ycle
of
an inlerruptable
instruction's
executron
NACT NACT
ll l
Tt;
12l T3
tT4
It l
tr l
Tl lT2tT3rT4
l t l
ll l
T1
I
T2
I T3
lT4
l l l
*,n/ \
Figure
6-8.
CP1600DMA Timing
Start execut ing
interrupt
service out ine
l',
'i[,i'.1,,i
i',
'.1',
i
i'.1,,i'{
i"1
Extemal
logic
inputs
staning
address
for
Interrupt
service
routine
Current
Program
Counter contents
wnnen
to
memory
stack
NACT
tr t
r l l
T l l T2 r
T3
T4
tl l
INTAK
I
_^t _
rJ l I
I
I
-t l
.l
I
I
I tl
I
BDIR
D0-
D15
Figure
6-9
CP
600
nterrupt
erv ice
Rout ine
ni t ia l izat ion
16- '14
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THECP1600 NTERRUPTOGIL
The
CPl600 uses a
vsctored
interrupt
processing
systom.
External
ogic equests n
interrupt
y
inputt ing
low signalatei thertheJNff i 'or i f f i 'plns.
Fol lowing
he execut ion f
the
next
interruptable
nstruct ion.he
CP1600acknowledgeshe
interruptby
pushing
Register
7
contents
the
Program
Counter) nto he
Stack:
hen he
CP1600
utputs
111, o l lowed y
010 at
BC1,
BC2.
and
BDIR.
xternalogic
must respond y
placing
16
bitsof dataon the
Data/Address us.
These
16
bits
of
data
wi l l
be
oaded
ntoRegister 7.
he
Program
ounter,
hus
causing
rogram
xecutiono
branch o
an
nterrupt ervice
routine
edicated
o
the
interrupt.
iming s i l lustrated n
Figure
16-9.
TheElTsrgnal
is
output
ow
fol lowi irg
xecution f
a softwarenterrupt
nstruct ion
SlN).
h is s
the only
microcom-
puter
describedn
this book
which
al lows
xternal
ogic
o
respondo a
softwarenterrupt
n
this
ashion.
l lowing
ex-
ternal ogic o respondo a sof twarenterrupt nlymakes ensewhen you ant ic ipate ourproductbeingused n a
minicomputer- l ike
nvironment.
ypical ly.
he
software
nterrupt
wi l l interface
o
logic
of
a
front
panel
or console.
When
an
SIN
nstruct ions
executed. one-machine
ycle
ow
PCIT
ulse
s
output
You
may.
f
you
wish.
end
an interrupt erv ice
out ine
y
execut ing
Terminate
urrent
nterrupt
TCl)
nstruct ion.
n
which
case
he
TCI
s ignal
wi l l
be
output
high.
Timing
or
TCI s
given
in
Figure16-10.
Fol lowing
n interrupt
cknowledge,
he
interrupt ervice
outinemust
execute
nstruct ions
n
order
o disable
nter-
rupts
and
save
he
contents
f
registers
n
he
Stack. he
exception
sRegister
7.
he
Program ounter,
hich s auto-
mat ical ly
ushed
nto he
Stack
ol lowing
n
interrupt
cknowledge.
External
ogic
s
entirely
esponsible
or
any ype
of
interrupt
r iori ty
rbi trat ion
hich mayoccur,
nd
or
the
genera-
t ion
of
the
interrupt
ectoraddress
hich must
be
input
ol lowing
n
interrupt
cknowledge.
-l',,i:ij
TCI instruction
object code
in
INSTRUCNON
XECUTE/FETCH
NACT
MC 2
I
rslra
INSTRUCTON ETCH
NACT
DTB
I
r',rcz
I
rtrcs
I t
r
r
l r
I
I
lrr l
z
ra
rol
rl z
rs
l r r t l r l r
lnstruction
address out
BAR
MC1
I
r r rz
I
BAR
Mc1
I
t r t l
rr i reira ralrr
Next
instruction
address
out
DTB
MC 3
rr rz s
re
t t l
Next
instruction
obiect
code
in
I
r3l 14
Fioure16-10.
CP1600
imino or
TCI nstruct ion 's
xecut ion
16-15
7/21/2019 General Instruments CP1600 Datasheet
http://slidepdf.com/reader/full/general-instruments-cp1600-datasheet 16/44
I t
is
oui te
easy o
generate
ignals
quivalent
o
othermicrocomputer
ystem
ussesrom
the CP1600System
Bus.
Thorcfnro /^ ,
^2^
use
parts
descr ibed
n Volume
3
to handle
CP' l
00
interruot
equl rements.
'
Ivv
vvr '
THE
CPl600
INSTRUCTION
ET
The
CP1600
nstruct ion et s re lat ively
t ra ight forward.
ddressing
odes. h ich
we
haveal ready
escr ibed.re
sim-
ple.
anC nstruct ionsre ypical
f
those
we
have
een
nd
descr ibed
or
other
microcomputers
nusual
eatures
etat-
ing
to
addressing
odes
vai lable i th individual
nstruct ions
re summarizedn
Table 16-2,
which
describes
he
CP1600
nstruct ion
et
l f
you
have never
programmed
PDP-11
minicomputer,
hen
you
should
pay
part icular
t tent ion
o
program-
ming
techniques hat result
from the Stack PointErand ProgramCounter being accessed as ganeralpurpose
registers.
A
wide
var iety
f
Register
perate
nstruct ions
l low
you
o
compute ataand oad
he resul t
i rect ly
nto
Register 7.
the
Program
ounter.
n
effect,
hese
become
omputed ump
instruct ions.
The
abi l i ty
o
manipulate
egister
6.
he
StackPointer,
s
though
t were
a
general
urpose
egister
means
hat
t i s
easy
o
maintain
number
of di f ferent tacks n
external eadlwri te
memory.
The
Jump-to-Subrout ine
nstruct ion
as
a minicomputer
lavor
o
i t .
Rather
han saving he return
address
n the
Stack.
Register 7
contents
re moved
o General
urpose
egister 4
or
R5.A
number
f
minicomputers
i l l
savea
subrout ine
eturn
ddress
n
a
general urpose
egister
n
th is
ashion.
he'problem
ith
his
ogic s
hat
you
must
ex-
ecute
an
addi t ionalnstruct ion i th in
he subrout ine
o save
he
return
address
n the
Stack f
you
are
going
o use
nest ing
ubrout ines.
f
you
are
passing
ubrout ine
arameters,
owever,
his
s
an
excel lent r rangement.
or
he
Jump-
to-Subrout ine
nstruct ion
laces
he address
f the
parameter
is t
d i rect lv n
a DataCounterwi th
auto- increment.
e
havedescribedhe conceptof parameter assingn Volume1. Chapter .
Note
hat
he
CPi600 nstruct ion
et
acks
a logical
OR.
ln
Tables
16-2
and
16-4.
nstruct ion
ength s
given
n
terms
of
"words"
rather
han
"bytes".
as
we
have
one
n
pre-
v ious
hapters.
ince
nly he
ower10
bi ts
of
theCP1600
bject
ode
are
present ly
sed, ystem
onf igurat ions
eed
not
have
he
ful l
'16-bi t
word
size
Hence
"word"
may
be
10
to
16
bi ts
wide.
depending
n the
implementat ion.
The
ol lowing
otat ion
s used n
Table16-2:
ADDR
One
word
of
di rectaddress
cond
Condi t ion
n
which
a branch
mav
be taken
Table
6-3
l is ts
al l
14
branch
ondi t ions.
DATA
Oneword
of
immediare
ara.
DISP
Oneword
displacement.eeTable 6-4
for
locat ion
f
s ion
bi t .
E External ranch ondi t ion
EBCA0-3
The
external ranch
ondi t ion ddress
ines:
EBCA0, BCAl.EBCA2.
nd EBCA3.
EBCI
The
external ranch
ondi t ion
nout
ine.
LABEL A 16-bi t
d i rectaddress.
argetof
a
Jump nstruct ion
See
Table16-4
or
the bi t
format.
f f i The
software
nterrupt
utput
ine
RB
General
urpose egis ter
4,
R5,
or
R6.
RD
One
of the
general
urpose
egisters.
sed
as a dest ina t ionor
operat ion
esults.
RM
One
of the
general
urpose
egisters
sed
as a
Data
Counter.
4
or
R5.
f
soecif ied.
s
auto-incremented
after
he
memoryaccessR6 s
incremented
ftera
wri te.
and
decremented
eforea read
RR
General
urpose
egister 0,
Rl . R2,
or
R3.
RS
One
of the
general
urpose
egisters,
sedas
he
source
f
an
operand.
S a uses
s
tne srgn status
C
the Carry tatus
Z
the Zerostatus
O
the Overf low
iatus
The
ol lowrng
ymbols
re
used
n
the STATUSESolumn:
X
tne status
ag
rs
af fected
y
the
opdrat 'on
a blankmeans
he
status ag rs not
af fected
0
tne
operat ion lears
he status
lag
1
the
operatronets
he
f lag
2
the
Overf
ow f
ag s
affected
nly on
2-bi t
shi f ts
or
rorates
'16-
16
7/21/2019 General Instruments CP1600 Datasheet
http://slidepdf.com/reader/full/general-instruments-cp1600-datasheet 17/44
SW
The
Status
Word.
whose
bits
correspond
o
the
condit ion
f
the status lags
n
the
fol lowing
way:
+
B'r
No.
StatusWord
When
the status
word
s
copied
nto
a register,
t
goes
o the upper
half
of each
byte:
r
RRJ
t swr
When
the status
word
is loaded rom
a
register .
t
comes
from
the upper hal f
of the
lower
byte:
tswl
Bits
y
through z.of the Register . Forexample,R7<'15.8) representshe upperbyte of the
program
C
ou
nter
lndicates
hat the
operand
.2"
is
ootional
A
low
pulse
Contents
f
location
nclosed i thin
brackets.f
a register
esignations
enclosed
ithin
the brackets.
then
he designatedegister 's
ontents
re
specifed.
f
a memory
ddress
s
enclosed i thin
he brackets,
then
the
contents
f the
addressed
emory
ocation
re
specif ied.
lmpl ied
memory
ddressing:
he contents
f the
memory
ocation
esignated
y
the
contents
f
a
register.
LogicalAND
Logical
Exclusive-OR
Addit ion
or
subtract ion
f
a displacement.
epending
n
the sign
bit
in
the
ob;ect
ode.
Data
s
transferredn
the direct ion f the arrow.
32r
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Table
16-3.
CP1600
Branch
Condit ions
nd Corresponding
odes
MiIEMONIC
ERANCH
CONDITION
OBJECT
CODE
DESIGNANOT{
c
LGT
NC
LLT
ov
NOV
PL
i,0
E
EO
t{zE
NEO
LT
G€
LE
GT
usc
ESC
C= l
Catry
{bgiccl
gr .tr
rhrr)
C
=0
fb
Cr.ry
lbqi:d
16 thm)
O= l
Or.rfiow
O
=0
l,lo
ovrfiow
S= 0
Phr.
s:1
Mnur
Z=l
Zro
l.Crdl
Z=O
fforucro
{rcr
cquel}
Sr*O=l
' - . . , \
t6r d[,1
SYO=O '-=;r
Graarr drrn
or
cquel
zV{SYOI
=
I
Lecs trm
or aqd
z v(SvOl
=
O
Crartr thln
.
_
CYS=t
.- '-
-'
trqUrip md clry
CYS:O
i
--
-
Equd
dgn
lrid c-ry
d)r
l@1
@1 0
r0r0
mil
10t
0r @
1r@
o101
t ro l
o l
r0
1l 0
ot i l
l t l t
The ol lowingnotat ion s used
n
Table
16-4:
Where en digi tsareshown, hey are he en ow-order i tsof a 10 to 16-bi tword. Wordsizedepends n the system
)
implementat ion.)
here our d ig i ts
areshown, hey
represent
he
hexadecimal
otat ion
or
an ent i re
word
(10
o
'16
' b i ts) .
bb
Two
bits
ndicat ing ne of the
f i rst
hree
general
urpose
egisters
cccc
Four
bi ts
giv ing
he
branch ondi t ion.
s shown n
Table
16-3
ddd
Three
bits ndicat ing
destinat ion
egister.
D
eeee
Four
bits
giving
he
external
ranch
ondit ion,
l l l l
One
word
of
immediate
ata
mmm Threebi ts ndicat ing
Data
Counter
Register
M
m One bi t
indicat ing he
number
f
rotates
r
shi f ts :
0
one
bi t
oosi t ion
1 two bit posit ions
p
One
bi t
of
immediate
ddress
P
One
hexadecimal
igi t
(4
bits)of
immediate ddress
rr Two
bits
ndicat ing
ne of
the
irst
our
general
urpose
egisters
sss Three
bits
ndicat ing source
egister.
S
z
Sign
of the
displacement:
0
add the displacement
o
PC
contents
1
subtract
he
displacement
rom
PC
contents
I
ln
the
"Machine
Cycles"
olumn.
when wo
numbers re
given
with
one
slash
etween hem
e.g.,7/9\.
xecution
ime
depends
n
whether
or
not a branch
s
taken.
When
wo
numbers re
given.
eparated
y
two slashes
such
s
8//11).
execut ion
ime depends
n
which regis ter
ontainshe
impl iedaddress.
16-23
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MACHINE
CYCLES
ADCR
RO
ADO
ADDR,RD
ADD@.
RM,RD
ADDI
DATA,RO
ADDR
RS,RD
AND
ADOR,RO
ANOA
RM,RD
ANDI
DATA,RO
ANDR
RS,RD
B
OISP
Bcond
DISP
BEXT
DISP,E
at Qa
CIRR RD
CMP
ADOR,RS
CMP.'I
RM,RS
CMPI
DATA,RS
CMPR
RS,RO
COMR
RD
OECR
RD
ots
EI S
GSWD
RR
HLT
INCR
RD
J 4OtrL
JO
LABEL
JE
LABEL
JR RS
JSR RB,LAEEt
JSRD
R8,LA8EI
JSRE
R8,LA8EL
MOVE
RS,RO
MVI
ADDR,RD
MVI
RM,RD
00mi01ddd
10',i000ddd
PPPP
101lmmmddd
'1011111ddd
iltl
0O
1
ssddd
11100@ddd
PPPP
1l Ommmddd
11]01
1 dcld
i l i l .
0
I l0sssddd
10OOz@O0O
PPPP
lfficccc
PPPP
10@z1e€ee
PPPP
ffi
01 1 dddddd
1'101o@sss
PPPP
I10lmmmsss
110111lsss
ml
0l01sssddd
om@r
1ddd
000001oddd
rrrl?
ffi2
0OOOI 0Or
0000
0000001ddd
0004
I 1
ppppppOo
PPPP
0@4
l1pppppp10
PPPP
0004
'I
lppppppol
PPPP
@10sssl1l
0004
bbppppppOO
PPPP
0004
bbpppppp
0
PPPP
0004
bbppppppO't
PPPP
0O
osssddd
r0lmooddd
PPPP
l0lOmmmddd
10
8//11
5
o
l0
8/ /11
o
o
7/ 9
7 /A
7/ 9
A
l0
8/ /11
d
o
b
4
6
17
1a
Table
1
6-4
CP
600
Insrrucrron
et
Oblecr
Codes
OBJECT
CODE
MACHINE
CYCLES
MVII
DATA,RD
MVO
RS,AOOR
MVOO
RS,RM
MVOI RS,OATA
NEGR
RD
NOP
(2 )
NOPP
PSHR
RS
ruLR
RD
RLC
RR(,2}
RRC
RRI,2)
RSWD
RS
SAR
RR(,2)
SARC
RR(.2)
SDBD
QTT'
stN
(2 )
SLL
RR(.2)
SLLC
RR(,2}
SLR RR(,2)
SU8
ADDR,RO
SUB@
RM,RD
SUBT
DATA,RD
SUBR
RS,BD
SWAP
RR(.2}
TCI
TSTR
RS
XOR
ADOR,RO
XORt( i ]
RM,BD
XORI
DATA.FD
XORR
RS.RD
10101
lddd
iltl
l@1Ooosss
PPPP
l0Olmmmsss
' l0Ol
l1 ' lsss
lill
0000100ddd
OO@l10lOm
l0OOZOt0oO
PPPP
10O1
lOsss
10101
oddd
0@10lOmn
0OO1110mn
00OO1
sss
0@ll0lmn
0OO11l ' lmrr
0001
0007
0@01'l0l1m
00O10O
mn
0OO101lmn
0@t
lOomn
11o@oodctd
PPPP
l lOommmddd
I r00l
I lddd
lill
0'lOosssddd
00O1O@nn
0005
0olOssssgs
1
1
l000ddd
PPPP
' I
l l
lmmmddd
111111lddd
iltl
0l
l lsssddd
o
b
a
1l
A /e
6/ 8
o
R/ 9
6/ 8
4
6
6/ 8
6/ 8
6/ 8
10
8/ /11
A
6/ 8
6/
/7
8/ /11
8
to-14
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THE BENCHMARK
ROGRAM
1
For
the CPl600
our
benchmark
program
may
be i l lustrated
as follows:
I
'
MVII
IOBUF.R4 LOAD
THE
/O
BUFFER
TARTING
DDRESS
NTOR4
MVII
TABLE,Rl LOAD
THE
TABLE
TARTING
DDRESS
NTO
R1
MVt@
R1.R5 LOAD
ADDRESS
F
F|RST
BEE ABLE
WORD NTOR5
MVII CNT,R2
LOAD
WORD
COUNT
NTOR2
loop
MVr@
R4,Ro
LoAD
NExr
DATA oRDFRoM
oBUF
RO,Rs
STORE
N
NEXT
ABLE ORD
oecn
Rz DEcREMENT
oRD
ouNT
BNzE LooP RETURNFNor END
Tnis
benchmark
rogram
makes
ery ew assumptions.he nput
able
OBUF
nd he data able
TABLE
an haveany
length.
and can
reside
nywhere
n memory.
he
address
f the
first reeword
in TABLE
s
stored
n
the
f rrstword
of the
TABLE.
,
1
6-25
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cP
1
00
System
Bus
Signals
BC't
BC 2
BDIR
INT
IN T
BUSEN
HOLD
BDYIN
WAIT
lfrSVNe
rr.r;
STSTP
HALT
Tr'l
EBCAO
EBCA3
EBCI
8080A
System
Bus
Signals
AO
A15
Dot
D7t
Dot
D7
I
High-order
byte
Loar-order
byte
I
of 8
Decoder
Figure
6-1
1
CP 600
ro
80BOA
Bus
Conversron
1
6-26
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SUPPORT
DEVICES
HAT
MAY
BE
USED
WITH
THE
CPl600
A
CP1600 microcomputer
ystem
with any
signif icantcapabi l i t ieswi l l
use
support devices
of some
other
microprocessor.aral le l/O
capabi l i ty
s avai lable i th
the
CP1680.
descr ibed
ext) , .but
r ior i ty
nterrupt
ogic .DMA
logic,
nd serial
/O
logic.
o
mention
ust
a
few
common
ptions.
may need
addit ional
upport
evices. ortunately.
t
is
quite
easy
o
generate
an
8o80A-compatible ystem bus from the
CPl60O system bus.
Logic
s
i l lustrated
n
Figure16-1
1.
The
CP16004 s
the
fastest ers ion
f
the
CP1600
CPU;
t runs v i th
a 500 nanosecond achine
ycle.
he
CP1600
machine
ycle
s
equivalento
an
80804
clock
eriod.
ince he standard 0804
clock
period
s
also
500 nanoseconos,
no speed onf l ic tswi l l ar ise.
The
bus-to-bus
nter face
ogic
l lust ratedn
Figure 6-1
s
sel f -ev ident ,
i th
the
except ion f
busdemul t ip lex ing
ogic.
The
CP1600Data/Address us s
shown
buffered
y
a demult iplexing uffer
hat s
connectedo two
latched
uffers.
One
of
the atched
uf fers cceptshe
demul t ip lexer
utputs n ly
when a val id
address
s
being
output ,
s dent i f ied
y
BARhigh.The
second
atched
buffer
may
be a bid irect ional
atched
buffer.
or
i t may
be two unidirect ionalatched
buffers. hree
atching trobes re
required: TB. AB,
and DWS.
DTB
and
AB
aredata nputstrobes.
TB
strobes
ata nput
hat
s
o
be
interpreted
s
data,
whi le AB
stroves
ata
n-
put
hat
s
o
be
nterpreted
san
address. o
ar
as
externalogic s
concerned, oth
of hese
ignals
resimple
ata
n-
put
strobes.
We
could herefore
enerate
single
ata nput
strobe s
the
OR
of
DTBand
AB.When
this
data nput
strobe
s
high,
nformation
n the
80804
SystemBus
side
of the
latched
atabuffer
must
be
nput
o
the buffer;
his
datamust
simultaneously
e transmittedo the mult iplexer.
DWS s he dataoutputstrobe.Whenhigh, hissignalmuststrobe ata rom he mult iplexero the atched atabuffer;
this
atched
ata
must mmediately
ppear t
the
80804
systemBus
side
of the
latched
ata buffer.
Since
he CP1600 ses
16-bit
DataBus.
ou
wil l
probably
a 've
o
generate
wo external evice atabusses: high-
orderbyte bus and
a
low-order
yte bus.
Al l
external
evices
hat ransmitor
receive
aral lel
atamust
be
present
n
dupl icate.
or
example.
were 8255
paral lel
nterface
evices
o
be
present.
he
fol lowing
onnections
ould
be re-
qui red:
wF-
RD
DO
D7
D8
D15
AO
A1
A2
A15
wR-
m
6t t3
oD l
AO
A1
:dE
WR
FN
5tc5
PPI
AI
Lt r
16-27
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l f f : : t ; t , ,?
i l :
yrttt t :
svstem
usses
re
insularlv
ncompatibre.
ou
hourd
or
rrempt
ouse
MC6800
upp(
1
2
3
5
6
7
I
9
10
1l
12
t5
to
17
td
IJ
40
JY
38
37
JO
35
34
33
32
cP1680
31
loB
30
29
28
27
26
25
=iei
IMSKO
nl
mm
IMSKI
EL I
BC2
BDIR
M'RbF
GND
VDo
PE
tl t
D3
vq
D6
ffiT
rcLB
PDO
PDl
PD2
ffi
PD
5
PD
4
PD 3
PO12
PD11
PD1O
PD 9
PD 8
PD3
PD4
PD5
PD 6
PD7
Pin
Name
D0-D7
i
POo
PD15
I
BDIR,
C1,
Cz
cK l
'. -
LE
PE
AN
INTR_O
Ter
IMSKI
IMSKO
EFFOF
FdH'
vcc,
vDD,
ND
Description
CPU
Data/Address
Bus
Peripheral
/O
Port
8us
Control
signals
.
Clock
signal
Chip
Enable
l/O
handshake
ontrol
l /O
handshake
ontrol
lnterruptrequest
Terminate
urrent nterrupt
Daisy
chain
priority
Daisy
chain
prior i ty
Error nterrupt
request
Reset
Power.
Ground
Tvpe
Bidirectional,
ristate
Bidirectional
Input
Input
lnput
Output
Input
Output
Input
Input
Output
Input
Input
Figure
16-12
CPtO80 OB
Signats
nd
pin
Assiqnments
I
o- lu
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o-
fi
i
3d
UV
UOUUS
:rud
3d
HV
unuHl
r ud
tM
z
o-sEF-->
63H82?6"i
FEHg
s?E
F
;E
< >d o
.\
t
1
6-29
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THE
CPl680
INPUT/OUTPUT
UFFER
IOB}
The CPl680 IOB
s
a
paral lel
/O device designed
pecif ical lyor
the
CPl600 CPU.This device
provides
a singte
15-bi t
paral lel
/O
port,
which
may optionatly
e configured
s wo 8-bi t l /O
ports.
Primit ive
handshaking
ontrol
signals are
availablewith
the
parallel
/O
logic.
Elementary nterval
timer
and
prioritized
interrupt
logic is
also
provided.
Figure16-1
also l lustrates
hat
part
of our
general
microcomputer ystem ogicwhich
hasbeen mplemented
n
the cPl680
toB.
The
CP1600
OB
s
packaged
s a
40-pin
DlP.
t
requi res
wo
power
uppl ies,
5V
and
+12V. A l l
inputs
re
TTL
com-
pat ib le. hedevice s implemented singN-channel OS echnology.
Figure16-13
l lustrates
CPl600
microcomputer
ystem
with
three CPl680 IOB devices
n the configurat ion.
CP1E8O
OB PINS
AND SIGNALS
The
CPl680 IOB
pins
and signals
are l lustrated
n Figure16-12.We wi l lsummarize
hese
signalsand he
func-
tions
they serve
before examining
device
operations
n
detail.
Let us
beginby
looking t
the
interface
etween
he
CP1680
OB
and the CP1600CPU.
D0
-
D7
provide
an
8-bit
parallel
Data/AddressBus
via which all
communicationsbetvrieen he CPU and
IOB
oc -
cur.This
bus must
connect
o the
low-order
ight
b i ts
of the
16-bi t
CPU.Data/Addressu$.
The
three bus controlsignals,
BCl, BC2,
and
BDIR,
connectthe CPl68O
tothe
CPl60O as
it lustrated
n Figure
16-13.
The
CP1680
OB
decodes hese
hreebus
contro l
ignalsnternal ly .
A clock nput s required y the CP1680. hisclock nput {CK1} s used by internal ogic o determinewhen BCl,
BC2,
and BDIRare val id.CK1
must have
he
fol lowinq
wave orm:
I
13
IT4
I
rl l
T1lT2lT3tT4
Ir l
ll
r r
rz
I
CK1must
be der ived
rom
he
CP1600
lock
signals
y
external
ogic
Let
us now look
at the
interface
etween
externalogic
and he CP1680
OB.
PDO
PDl5
provide
a
16-bit
parallel
/O
port
which
can
optionally
be
configured as
two
8-bit /O
ports.
Whi lePDO PD15
are
n
theory idirect ional.hese
ins
are more
ac-
curately
escribed s
pseudo-bidirect ional.
his s
because
hen
a zerohas
been
wri t ten
to
oneof these
oins.
he
outout
can s ink
1.6
mA
for
an
outout
ol taoe
f
*0.5V.
External
logicwi l l
havea hard
imeovercoming
his
s ink n
order
o
pul l
he
pin
high.
n
contrast ,
hen a
I
is wr i t ten
o one
of
these
ins.
he
output
ources
ust
100pA
at
+5V.
Externalogicwi l l
have
i t t le
problem
inking
1OOpA
n
order
o
pul l
a
pin
ow.Therefore.
ou
should
utput
a
' l
to
any
pin
hat
s
subsequent ly
o
receive
nput
data
External
ogic
wi l l
then
leave
he
pin
high
when
nput t ing
1, whi le
pul l ing
he
pin
low
to
input
0.
The
handshaking
ontro l ignals
which l ink
he
CP1680
OBwrth
external
ogic
are
PE
and
EfA
pg
is a
contro l
ignal
which
s
output
by
the
CP1680.
nd
fi
is a
contro l ignal
which
s i , rput
o the
CP1680.
Now
consider
P '1680nterrupt
ignals .
An
interrupt
request
s transmitted
to th e cPl600 cPU viaTtIiFO. The cPU acknowledges the
interrupt via the
TNTAK
ombination
f
BDIR,
BCl, and
BC2.Tei
must
be
output
ow by the
CPUat
the
end
of
the
intemrpt
ser-
vice
routine.
This
signal s required
y
CP1680 nterrupt
ogic.which
uses he
lowTTpulse in
i ts
priori ty
rbi trat ion,
as
descr ibed
ater
n
his
chaoter .
cPl600 /o
PORTPI N
CHARACTERISTICS
I
O-JU
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)
Interrupts
may be
generated
by
conditions
nternal
o the
CP1680.
r
by a tow
input
atff i ff iF.
TneffiF-O'H'input
s
reserved or
error
conditionsdetected
by
external
ogic.
\
,
IMSKI
and
IMSKO are interrupt
priority
input
and nterrupt
priority
output signals,
espectively.
These
ignalsare
used
o
generate
aisy
chain
nterrupt
r iori t ies
etween
CP1680
OB
devices.
s
l lustrated
n
Figure
16-13.
We
wil l
describe
CP1680
nterrupt
r iori t ies
n
moredetai l ater
n
this chapter.
TiEEF
is the
master eset control
nput or
the
CPl68O.
This
signal
must
be nput
ow or
at least10
mil l iseconds
n
order o
reset
he
CP1680
OB.
CP1680
ADDRESSABLEEGISTERS
The CP1680 has eight addressable ocations,which may be illustrated as follows:
These
ightaddressableocations
real l
8-bi t egisters;
heyareaddressed
sing
he
irst
eight
addressesn a
256-ad-
dress
block,as fol lows:
Register
Control
Data
buffer. ow-order
byte
Data
buffer. igh-order
yte
Timer. ow-order yte
Timer.
igh-order
yte
l /O
interrupl ector
Timer
nterrupt
ector
Error nterrupt
ector
Address
\J
1
2
6
16-3'r
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The
actual 56
addresses
i l l be
dent i f ied
y
the
eighthigh-order
P1600Datai
Address
us ines.
which
wi1
be
u
to createCP1680
evice
elect
ogic This
device
eiect
ogic
reatesGi tne chip
enable
ignal ) ;t
may
be i l lusrrat r
as
fol lours:
00000Y
Y
Y Valid CPl680 addresses
May
be
000,
001, 010, 011. 100,
101.
l10.
t I I
May have any 8-bit
pattern
that
device
select ogic
has beendesigned
o createG
low
in
response
o.
THE
CP1680
CONTROL EGISTER
We
wi l l
summarize
he
indiv idual i ts
of
the CP1680
ontro l
egis ter
efore escr ib inghe operat ions
hey contro l
Here
are CPl680 Gontrol
egisterbi t
assignments:
#-Bir
No.
CPl680 Control
register
DO
I
t
o7
D8
O
a
D15
43210
I o - parailer/o active 1 This.is.calledhe
1 1
-
Parattet/o inactivef
:aoJ
o'l'
l -E:HEAOV
ERROR
nput
signal
evel held here
0
-
PD0-PD15
onfigured
s two 8-bit
ports
'l
-
PD0-PD15
configured
as
one
16-bh
port
0
-
Disable
parallel
/O and Error
nterrupts
'I
-
Enable
parallel
/O
and
Error
ntemrpts
0
-
Disable
imer
interruots
1
-
Enable imer interruots
0
-
Disableclock
logic
1 - Enableclock logic
Parity
of
D8-D15 bvre
I
O
:
even
parity
\
Pariry
of
D0-D7 byte
I
t
:
odd
ParitY
D0---D7atCPl680
1
6-32
7/21/2019 General Instruments CP1600 Datasheet
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Bit 0 is
always
he
complement f
the
PE
control
output.
This
bi t
may
be
interrogated
y
the
CPU. f
paral lel
ata
t ransfer
nterrupts
redisabled.
his
al lows
he CPU
o
pol lon
status
when
moni tor ing
aral le l
ata
ransfers.
E
signal
levels
re
l lust rated
n
Figures 6-14
and
16-15
Bit
I
ref lects
he
level
of
theff iOF-input.
l f
paral lel
ata ransfer
nterrupt
ogic s
disabled.
hen
the Error nterrugt
logic
s
alsodisabled.
hus,
he
CPU
must
also
examine
he
Error
tatusbi t when
pol l ing
he
CP1680.
Bi t2determineswhetherPDO-PD15wi l lactasasingle16-bi t l /Oport .orastwo8-bi ti /Oports
his isonly impof iant
when
outputt ing
ata.
Contro l egis ter
i ts
3 and
4
areused o
enable nd
disable
aral le l
ata ransfer nd Errornterrupt
ogic , nd
imer n-
tor r r rnt lnnin
Contro l egis ter
i t 5
is
used
o
enable nddisable P1680
nterval
imer
ogic . f
th isbi t
s0,
the
nterval
imer
wi l l not
decrement.
B i ts6
and
7
repor l
he
par i ty
f
tne h igh-order
yte
and ow-order
yte
ordata
hat
s nput
oroutput
via
PD0
PD15.
indicates
ven
pari ty
whi le
l
indicates
dd
pari ty.
Al l
Control egister
i tsmay be
wri t ten nto
or
read. ou
should
be
very
careful
when
sett ing
r
resett ing
ndividual
i ts
not
o
simultaneously
odify
other
Control egister
i ts.
This
means
ou
should
usea
three-instruct ion
equence
ith
an
AND
or
OB mask
o set
or
resetany Control eg ister
i t .
For
detai ls
eeVolume
1-Qas1c
olceptg
CP1680
DATA
TRANSFER
PERATIONS
The
CPU
nputs
and outputs data via the CPl680
IOB
by
executing
MVI
and MVO
instruct ions,
espectively.
The
CPU
mustaccesshe CP1680 n bytemode, ince n 8-bi t Data/Address us
D0
D7)connectshe CPUand he
CP1680OB.
Whether
he
/O
port
PD0 PD'15
s
conf
gured
sa s ingle
16-bi t
port
or
as
wo
8-bi t
ports
hasno
bear ing
on
the
fact
that the
CPUmust
access
he
CP'1680n
bvte mode.
The
most
eff ic ient
way
of accessing he
CPl680
is by
using the SOBO nstruct ion
with
impl ied memory
ad-
dressing.
Consider ata
nput .
f
PDO PD'15
s
conf igured
s
wo
8-bi t /O
ports
and
you
wish
to
access,ust
ne of
thesel /Oports .thenyoucanuseimpliedmemoryaddressingviaRl .R2.orR3
emayi l lust rate input f romrhehigh-
orderbvte
cf
l /O
Pc: t
PDB PD15
as
ol lo, ,vs
Register
l
4F
I O-JJ
7/21/2019 General Instruments CP1600 Datasheet
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l f PDO
Pll15
3re
conf
guredas
therr
or :
should
use he
SDBD
iol lows:
tv/o
B-bit
O
oortsor
as
instruct ion
i th rmplred
a s ingle
16-bi t
/O
port .
memory
addressing
ia
and
you
want
to
read
both rO
oorts .
R4
or
R5
This
may
be i i lust rared
s
Corr trol
egi , \ t :e
tr t
2 l
conf igures
PDO
PD15
as a
single
16-bi t
l /O
Civr ;n
hr :
a. , :1
11;3i l r1\ ' r
nd
lVlVOrnstructrons
in
byte
mode)
should
i rr. i , i : l : : : f lS
t)r-a' . t
i'
/
Thc
dr]svver
:
ihat
ihe
PE
ano
ff i -srgnals
control
event sequences.
Consider
paral le l
data input,
as i l lustrated
in Figure
16-14.
port
or as
two
8-bit
/O
ports.
be used
o access
heCp1680.
when
should
hese
IN RO
:) i
iA f
When
the CPU s
ready
o input
data in
resets
the
Control
egister
READY
bit low.
This forces
the PE
output high
Extemal
ogic
uses PEhigh
to
trigger data rransfer
to
the
PD'1680.
xternal ogic
signals
he end
of
data input by inputting
fi- low
Frgure 6-14
PD16B0
Handshaking
rth
Data
npur
L
1
6-34
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When the
CpU
s
ready
o
receive
ata.
t
resets-Control
egister
i t
0
to
0,
this
orces
he
PE
controlsignal
high.
When external
ogic
senses
E high,
t
must
t ransmi t
ata to the
PDO
PDl5 l /O
port .
At
th is
point
t
makesno
dif ference
hether
pins
havebeen
configured
s two
B-bit
ports
or
as a single
16-bi t
port.
External
ogic
wi l l
pul l
to
ground elected
igh
pins.
whi le eaving
ther
high
pins
alone.
When
external
ogic
has
completed
ata
nput . t s ig-
ials the
act
by
nputt ing
f i - tow.
l t
is
he
high-to-low
ransit ion
f
the
AR
control
nput
which ndicates
he
presence
f
new
data
or
the
CpU o
read.
When
AH'makes
ts
high-to-low
ransit ion,
E
also
makes high-to-lowransit ion.
nd
C"",J
r"gir, .r
bi t
O s
set o
1 l f
interrupts
avebeenenabled.
hen
an
nterrupt
s
requested
ia
ff fRa,.Figure
6-14
assumes
hat
nterrupts
avebeenenabled;
hereforeINTR-Ois
hown
making
a
high-to-lowransit ion.
The CpU wi l l acknowledge
he
interrupt
equest .
s descr ibed
ar l ier
n
th is
chapter ,
y
output t ing
NTAK ia
BC1.
BC2.
and
BDIR.
ogic
nternal o
the
CP1680
ses
NTAK
o
reset
NTRO igh again
There re
many
ways
n
which
external
ogic
andetermine
hen
o
set l -R
high
again.
n Figure
6-14we
show
exter-
nal
ogicusing
PE
o
setAFhigh.
Clear ly .
hen
PE
makes
low-to-high
ransi t ion,
he
CPU
must haveacknowledged
m
lo;; thereiore
xternat
ogiccan
now
set
f i 'nign. Now
hat
El:
n ign
again,
xternal
ogic
an
nput
new data.
An
alternativecheme
wouldbe
or
external
ogic
o
constantly
old
AR-low.
sing he
evel
f the
PE
output
o determine
when new datacould
be t ransmi t ted.
hen
PE
s
high,external
ogic
wi l l
t ransmi t
ew data
o
the
CP1680
nce.
As
soonas
t
t ransmi ts
ew data,
external
ogic
wi l ls t robe
he data
wi th a short ,
igh
ARpulse"
hen
wai t
for
PE
o
go
low
and high
againbefore
nput t ing
more
data.
This
may be
i l lust rated
s
ol lows:
AF
t
PU
s
ready
again
for input
Extemal
logic
nputs
data
Data
output
handshaking
s
i l lustrated
n Figure
16-15.
-+
I
Extemal
logic
nputs
data
When CPU outputs
data,
PE s automatically
se t
high
Extemal
ogicuses
PEhigh as a
"val id
data
ready"
signal.
After
reading
his
data
it resets
fi'tow
DO-D7
PE
AH
iNTFO
INTAK
Figure
6-15.
PD1680Handshaking
or
DataOutput
1
6-35
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The
most
important
point
to note is that there
s
no control
bi t
which specif ies
data
nput
mode
or data
output
mode.
Thus,
he signal
seguenceswe described or
data
nput
and
hose
we are
about
to describe
or
data
out-
put
occurautomatical ly; he
input
or output
mode s
purely
a funct ionof CPU
and
external
ogic nterpretat ion.
WhenevertheCPUoutputsdatatothePDl630, thearr ival
f
dataforcesPEoutputhigh
lPD0-PDiShasbeei rcon-
f igured
as
wo 8-bi t
ports ,
hen he
arr ival
f
a
s ingle atabyte o e i ther
port
wi l l
cause
PE
o be
output
hi -oh
f PDO
PD'15
s
conf igured s
a s ingle '16-br t
/O
port ,
hen
PD
wil l
not
be output h igh
untr l
wo byres
of
data have
been
received
rom
he
CPUbv the
PD1680.
Once
PE
s
output
high.
nothing
morehappens
'nt i l
x ternal
ogic
esponds.
xternal
ogic
annot e l l
by
the
simple
n-
spect ion
f
any
contro l
ignals
hether
data nput
operat ion r
a data
outputoperat ion
s n
progress.
t is
up to
you.
whendesigningoursystem.o dedicate P1680 eviceso inputor output ;oryoumustgenerate ourown dent i fca-
t ion
ogic
n
the event
hat
a CP1680
OB
s
bidi rect ional .
n
Figure 6-15
we
simplyassume
hat
external
ogicknows
data s
o be
read,
nd
knows
whether
he
data
s
16
bi ts
or
8
brts
wide.
Furthermore.f
the
data
s
8
bi ts
wide.
external
logic
must
knowwhich
8 bi ts
o
read
n
any
event .
hen
external
ogichas
ompleted
ts
undef ined
perat ions.
t must
input
AR
ow.Thehigh-to- lowransi t ion f
AF' forces
E
ow
again. nd
f nterrupts
re
enabled. n
interrupt i l l
be
re-
quested
ia
I ITFt ' . When
the CPU
acknowledges
he interrupt y output t ing
NTAK
vra
BC1.BC2.and BDIR.
he
PDl680
uses
he
INTAK
pulse
o
reset INTRQ-ign.
The
method
used
by external
ogic o
resetA-F
igh
again
s
undef ined.
n
Figure
6-15.
we
show
PEgoing
highas
he
tr iggerwhich
external
ogicuses o
reset
AR
high.
This
s
c lear ly
v iable
cheme;
E
wil l
not
go
high
again
rnt i l
resh
datahas
been
output ,
t
which
point
t
is
safe o assume
hat
heCPU
knows
r ior
datahas
been
ead
by external
ogic .
I t would
be
equal ly
iable
or
external
ogic
o holdf f i -cont inuously
ow,
ransmi t t ing
short . igh
pulse
whenever
t
reads
ata.
This mav
be
i l lust rated s
ol lows:
CPU
has
output
oata
-
t-
I
External
rE
+
I
Extemal
logic
has
read
data
CPU
has
outplJt
more
data
logic has
read
data
Because
here are no controlsignals
which identi fy
he PD1680
operat ing n
input
mode
or output
mode, here
is
no
straightforward c heme or handl ingbidirect ional
ata transferswith a single PD1680 device.
THE
CP1680 INTERVALTIMER
The
CP1680
has very
elementary
nterval imer ogic.A
16-bitTimer
egister.
ddressed
s wo separate
-bi t
oca-
t ions,
decrements
nce
every
eight
CK' l
pulses,
rov id ing
he
t imer hasbeen
enabled
You
enable
nd disable imer
logic
via
Contro l
egis ter
i t
5.
As a
separate
vent ,
imer
nterruptsmay
be
disabled ia
Contro l
egis ter
i t
4. l f
t imer
interrupts
re
enabled.hen
when
the t imerdecrements
o
0.
an
interrupt equest i l l
occur.
f imer
nterrupt ogic s
descr ibed
i th
other
CP1680 nterrupt
ogic
ater n
th ischapter)
f
t imer
nterrupts
renot
enabled.hen he t imer
t-
sel f s
effect ively
isabled. ince
you
cannot estany
t imer
status
lag
to
see
f
the
t imer
imed out;
nor
can
you
ac-
curate ly
ead
he
contents
f the
Timer
egis ters
n the
ly.
s ince here
s no
protect ion
gainst
eading
imercontents
whi le
t
is in
the
process
f
beingdecremented.
The
only
t imer
programmable
ption
you
have
s
to load
an ini t ial
value before he
timer is enabled.
The t imer
has
no buffer; therefore,
once
it
t imes out
i t
begins
decrementingagain, f st i l l
enabled,beginning
with the
value FFFF15. his may be i l l ustratedas fol lows:
Time
out.
Restarl
Time
out.
Restart
f ime out.
Restan
Timeintervals-
[<-
xxxx.
8.cK
-+F-
FFFF.8..K
---'{*--
rr*
1..*
r
--{
Load
Timer
stanrn9
value
XXXX
ano stan
Timer
16-36
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The
only
accurate
ong
ime
ntervals
ou
can
compute
reexact
mul t ip les
f
FFFF16'8 'CK1.
The
CP16004
uses
a
4MHz
wo-phase
lock,
which
generates
500 nanosecond
ycle ime.
Thus.
CK1
equals
500
nanoseconds,
nd ong
CP'16004
ime
ntervalsmustbe an exact
mult iple
o'f
262. '144 i l l iseconds
the t ime
t wi l l
take
or
the
counter
o
decrement
rom
FFFF16
o
0000.
^
3MHz wo-phase
lock,
which
generates
600
nanosecond
ycle
ime; herefore.ong
ime
nter-
hE Lt,
I
OUU
USES A
J.
vals
must
be exact
mul t ip les
f
314.572
mi l l iseconds.
The
CP1610.
hich runs
on
a
2MHz
wo-phase
lockand
hasa
one
microsecond
ycle ime.
wi l l
compute
ong
ime
n-
tervals hat
areexact
mul t io les
l524.288
mi l l iseconds.
Youcannotat tempt o generate lockper iodshataremul t ip les f shorter ime ntervals y loading ome ni t ia l a lue
into
he
imer
ol lowing
ach imeout ;
an unknown mount
f t ime
wil l
e lapse etween
he
nterval
imer
nterrupt
c-
curr ing
nd beingacknowlOdged.
he ength
of th is
unknown
er iod
f
t ime
wil l
depend n
the
number
of
non- inter-
ruptable
nstruct ions
hich may
be execut ing
n
sequence
hen
the
interrupt
equest
i rs t
occurs.
p lus
any
higher
pr ior i ty
nterrupts h ichmayexis t .
herefore,f
you
oad
an
ni t ia l
a lue nto
he
imer.
t
should
be o compute
n
isol -
ated
ime
nterval
n ly .
Here s
an appropr iate
nstruct ion
equence.
MVI
IOB,RO
;INPUT
ONTROL EGISTEBONTENTS
ANDI
CFH.RO
;ZERO
ITS
AND
5
MVO RO.|OB
;RETURN
O
CONTROL
EGISTER
MVl l 2AH.R0 ;TRANSMIT
OW-ORDER
IMER
MVO
RO,|OB+3
; lNlTlAL
YTE
MVl l 34H.R0 ;TRANSMIT
IGH-ORDER
IMER
MVO
R0,JOB+4
lNlTlAL
YTE
MVI |OB.RO
:LOAD
PRIOR
ONTROL
EGISTER
CNTENTS
ADDI 30H.R0
;SET
BITS
AND
5
MVO
R0.|OB
:START
IMER
The
nstruct ion
equence bove
begins
wi th
three
nstruct ions
hat
load
he
CP1680Contro l
egis ter ontents
nto
Register
0.
Bits
4
and 5 are
zerod,
hen
he
resul t s returned
o
the
Ccntro l
egis ter
hus,
he
t ime.
and
imei ' in ter-
rupts
are
disabled
We
dc
not
botherrar i th
n
SDBD nstruct ion
ince he dalasource
s
eightbi ts
vrrde.
nly
he
low-
orderbyt€
o{
Register 0wi l l
be s igni f
cant .
hrs
berng
he case.
we
can
usean
8-bi t mmediate
ND
masr
o
mt
Ci ty
Register 0
contents
efore
eturning he
low-order
yte o the
Control
egister.
Next .
we
load
he
ni t ia l imer
value.
ne
byte
at
a
t ime.
nto
Register O.
ach yte
swri t ten
out
to the
appropr iate
al t
of the Contro l
egis ter .
nceagain
we
do
not need
o
use
he
SDBD
nstruct ion. ince n 8-bi tdata
path
connectshe
CPU
o
the
1680 OB.
only
he
low-order y te
of
Register 0 wi l l
be s igni f icant ur ing he
data
output .
Final ly . e star t he t imerby loadingContro l egis ter ontentsntoRegister 0.set t ingbi ts4 and 5 to ' l and wri t ing
back
he
resul t .
When
you
wri te
nto he
Timer egis ters.
ou
clearany imer
nterrupt
equests h ich may at
that
t ime
be
pending.
CPl680 INTERRUPT OGIC
A CPl680 IOB
will
generate
an interrupt
request by
outputting
a low signal
atTtiffiE if any one of
these
three
condit ions
occurs:
1) A
low input
atmE6fi- ' .
External
ogiccan request n
rnterrupt ia
the
CP1680 sing
heff i -OF
input.
2\ Thef f i -handshaking
ontro l
nput
makes
high-to- low
ransi t ion
his
s l lust ratedn
Figures 6-14
and
16-15
3) The nterval
imerdecrements
rom
1
to
0.
Recal l
hat
here
are wo separate
nterrupt
nable/d isableontro l i ts
n
theContro l
egis ter . necontro l
i t
appl ieso
the .nterval imer.whi le he othercontrol i t appl ies o both freff i 'handshaking nOEH-RG-interrupts.
Interrupt
priori t ies
among he three
sources
within
a single
CP1680
OB
are
as fol lows:
EF'FOR-'
iohesr
IT"
na-nOsbat<ing
Timer lowest
When
more han
one
CPl680 IOB
s
present
n a
CPl6O0
microcomputer ystem,
hen daisy
chain
priori ty
s im-
plemented
using
he
MSKI nput
s ignal
and
the
MSKO
output
s ignal .S ignalconnect ions
re
i l lust rated
n
Figure
16-13.
The
manner
n which intarrupt
priori t ies
are
handledby
the
CPl680
is a l i t t le unusual.
Two
or
more
CP1680
devices
may
combine
hei r nterrupt
equest
ignals .
h ich
are
wired
ORed
and
inpul to
the
CP1 00
via
Tfr iJEdThe
CP1600 cknowledges
n nterrupt
ia
he
NTAK
ombination
f
BC'l BCz.
and
BDIR.
We
de-
16-37
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scr ibed his
process
ar l ier
n
the
chapter .Al l
CP1680devices
imul taneouslyeceive
he
INTAK
combinat ion:
however. CP1680
which
s
acknowledgedaises
ts
MSKO
ignal
igh,
ausing
t
to become
he
MSKI
nput
o
the
next
CP1680
n
the daisy hain.
Any
device
hat
receives
high
MSKI
nput gnores
he
nterrupt
cknowledge.hus,
only
he
highest
r iori ty.
nterrupt
eQuesting
P1680
evice
n
he
daisy
hain
wi l l
process
he
nterrupt
cknowledge.
However,t
takes
f in i te
amount
f
t ime
or MSKO
igh
signals
o
propagate
s
MSKI
ignals . nd
hus
ipple
hrough
the daisy harn.
Consequent ly .
maximum
f e ightCP1680
evices
may
be
present
n
the
darsy hain
A
ninth
device
wil l receivets
IMSKI
igh s ignal oo
late
and wi l l respond
o
an interrupt
cknowledge.
CP1680IOB
evices
mainta inhei r
nterrupt
r ier i ty
tatus
nt i l hey
eceive
high
TCI
pulse.
t
that ime.
pr ior
nter-
rupt
priori t ies
re
eset t al ldevices. ndnew
priori ty
rbi trat ion
egins
Thus.
when
usingCPl680 IOB
devices,
you
are required
o end all
interrupt service routines
by executing
a TCI
instruction.
Note
hat
f
one
CP'1680IOB
as
more
han
oneactive
nterrupt
equest
for
example, n
ERRORnterrupt
equest nd
a
timer
nterrupt equest).
hen his
nternal
nterrupt
r iori ty
wi l l
take
precedence
ver he
daisy
hain
nterrupt
r iori ty.
That
s
o
say,
he
ERROR
nterrupt equest i l l
be acknowledged
nd
serviced
rst.
After
he
nextTCI
nstruct ions
ex-
ecuted.
he imer
nterrupt
equest
i l l
be serviced
efore
ny
nterrupt equestrom
a
lower
priori ty
CP1680
evice
s
acknowledged.
Every
CPl680 device has three
8-bit
Interrupt
Vector registers,
one dedicated to
each
of the
three
interrupt
sources.
These
hree
lnterrupt
Vector registers
were i l lustrated
arl ier n
the chapter.
Fol lowing
an interrupt
acknowledge,
when the
IAB
c,ombination
ppears
at
BCI
,B,Cz,
and BDIR,
he contents of
the Interrupt Vector
register
or
the
highest
priori ty
act ive
interrupt
wi l l be returned o
the
CPU.
nterrupt
cknowledge
iming
s i l -
lustrated
n
Figure
16-9.
At
the
interrupt
ervice
ocation
Jump-to-Subroutine
nstruct ion i l l
probably
e stored.
Since
he
Jump-to-Subroutine
bject
ode
s
three
words ong.a maximum
f
85
interrupts
an be
origined
n
the
irst
256
words
of
memory.
his s
more
han suff ic ient.
inceonly
eight
CP1680
evices
with 24 interrupts
an
be
sup-
ported n a singledaisychain.
1
6-38
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DATA
SHEETS
\
I
f nir
sect ion
ontains
pecif ic
lectr ical
nd iming
data
or
the
fol lowingdevices:
:ffitrs,-li:,*",
l
16-D1
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cPl
600.
CP1
600A.CP1
61
0
BUs
TIHING
OIAGRAH
l l
6z
s
cf,naa-
00-0t5
<€
OI'TPW
.H
lr
Pttr
rF+
OI'TPUT
C+I TO
FETCH
DISPUCEIIXT
f,OGRAT
UNER
EEXI
IXSTRUCNOI
EBCI
-
00r'r clR€
CIRE
+
LEG€ID:
\\\\\\
m-Dt5
EUs
r\\\\\r
g;161X6
DtREgItOr
TYPICAL XSTRUCTION SEOUENCE
G...,.il.;
+-r
Fi:r
Frr F-ri1r
=.
Frs_,
rst
FTs
Frr--,
I r
94v
I
OE Y
lz
I
l;
U
i
I
I
I
I
I
I
ll
tl
tl
ll
il
lFla,
-
Frrs
-J
gcl ,
c?,
i
80I l I
I
I
r-
rsYrc i /
lr #
*
tBF-
-1
tro
l-
ta,-1
Flsz
EUS
8rJ3
8u5'
c]{lrgtrc
Ftfl
ouTPur
our.Gtic
rhol
Flolr
st rc
Y
LtD ourryr
rcot
ro
k-+l
trpul
rrSrRuol0r
oRDrr
OP€RTXO
urrul r@€
FLOrr
00 t
BRANCH
Oil
EXTERNAL
CONOITIOX TNSTRUCTION
Data
sheets on
pages
16-D2
through
16-D6
reprinted by
permission
of General
Instrument
Corporation.
16-D2
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cP1 00
ELECTRTCAL HARACTERTSTTCS
CPl600)
llerlmum
Ratlngr'
Voo, cc,
GND
andall
other
npuVoutput
oltag€s
with resgect
o Vrr -0.3v
to
+18.0v
Storage
emperature
. -55oC
o
+150'C
Operating emperature
.0"C
to
+70oC
Stendard
Condluonr:
(unless
otherwise
noted)
Voo=+1?V+5%,omA(typ)
11omA(max.)
Var=
3Vi10i6,
o.2mA(typ)
zmA(max.)
Vcc=+SVts%,2mA(typ)
,
2smA(max.)
OperatingTemperature Tr)=0oG
o
+70cC
"Typical
valu6
are at
+25oC
and
nomrnal oltages.
NOTE:
The
Bus
Data
ReaDY(BDRDY)ine s
samplod turing ime
period
TSI aftera BAR
or
ADAR bus
control signal.
BDROY
musl
9o
low
reguesting
a wait 3tate
5()
ns before the
o;d of TS1 and
remaih low
lor 50
ns minimum.
BDRDY
mey
9o.
high
asynchronously.
n response
o BDRDY,
he
CPU ryill
extendbus
cyclesby
aclcting
ctditionel
microcyclos
up
to a
msximum
ol
40
psec
durstion.
'Exceeding
these rat ings could
csu3o
p€rmanent
dameg6 to thege
devicos.
Functional
ogoration
at
thes€ cgnditions is
not impl ied-ope16t ing
condit ions aro
specified
below.
Ch.r.cl.dttlc
Syn
Hln
Tvp"
tr r
Unltr Condltlonr
OC CHARACTERISTICS
Clock Inputr
High
Lo w
Loglc lnputr
Low
High
(Al l
Linesexcept
BDRDY)
High
(Bus
Data
ReadyLine
See
Note)
Loglc
Outputr
High
Lo\ry
Data
Bus LinesDO-D15)
Low
(Bus
Control Lines,
BC1,BC2,BDIR)
Low
(All
Others)
Vrxc
Vrlc
Vrr-
Vr r
Vrxr
VoH
Vor
Vor
Vo l
10.4
0
0
2. 4
3.0
2:
Vcc
Vo o
0. 6
0.65
Vcc
Vcc
0.5
0.45
0.45
v
V
v
V
V
v
v
V
v
lor
=
1@pA
lor
=
1.6mA
lor
=
2.0mA
lor- 1.6mA
AC CHARACTERISTICS
Clock
Pub
lnput
, Ol
or
62
PulseWidth
Skew
(d1,
62delayl
Olo'ci
Period
Rise
&
FallTimes
Merler
SYNC:
Delay rom
6
DO-OI5 Bur
Slgnrlr
Output clelay rom
Ol
(f loat
o
output)
Outputdelay rom 62
(output
o
tloat)
Input
setup ime before
61
Input
hold
time after
C1
Bur
Control
Slgnrlr
BC1,BC2.BDIR
Outputdelay rom
01
BUSAK
Output delay
rom
01
TCI
Output
delay rom
61
TCI Pulse
Width
EBCA
output delay
from
BEXT
ingut
EBCA
wait
time tor
EBCI
nput
r62,
rO2
It2,
tzt
tcy
tr, tt
tms
tao
tg r
tg r
te z
toc
tau
tro
tT w
toe
trr
120
0
0. 3
;
r0
T
150
200
300
2.0
15
30
120
120
15 0
400
ns
ns
lrS
ns
ns
ns
ns
ns
ns
n3
ns
ns
n3
n3
ns
1 TTL Load &
25
pF
I
I
I
I
CAPACITAI{CE
61,
62
Clock nput
capacitance
Input
Crplclt nc.
DO-D15
AllOther
Output
Crp.clt nc.
DO-OI5 in
high
impedance
state
co1, c,
clN
Co
20
o
5
I
30
't2
10
15
pF
pF
9F
pF
TA
=
+25'C;
Voo
=
t12V;
Vcc
=
*5V;
Vrr = -3V: t0'l t CA= 120ns
16-D3
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cP1
600A
ELECTRICAL
HARACTERISTICS
CP1600A)
Marlmum Rstlngt'
Voo,
cc. ND
and
allother
npuvoutput
oltages
rvilh
especto
Vrr
-0.3V o
+18.0V
StorageTemperature
.
-55oCto+150'C
Operating
emperature
.0oC
o
+70'C
Strndrrd
Condlilonr:
(unless
otherwise
oted)
Voo=+12V:5%,
0mA(typ)
140mA(max.)
Vss=
3V11oo,i.
.2mA(typ) 2mA(max.)
Vcc=+5V+5%,
2mA(typ)
25mA(max.)
Operating
emperatureTe)=ooC
o
+70"C
"Typical
values
are at
+25oC
and nomrnal oltages.
NOTE:
The
Bus Data
ReaDY(BDRDY)ine
s
sampled
during
ime
perioct
SI after a BAR or
ADAR bus
control
signal.
BORDY
must
go
low
requesting
s wait state
50
ns
b€fore fre eid ot
TS1 and
remain
low
lor
50
ns minimum.
BDROY
may
90
high
asynchronously.
h response
o BDRDY, he CPU witl€xtendbus
cycles
by adcling
dctitional
microcycl$ up
to a
marimum
of
40
rsec
duration.
'Exceeding
lhese
rat ings could cause
permanenl
damage
to these devices.
Functional operation
at thes€ conditions
is
not
implied-operat ing condit ions
are
soecif ied
below.
Chrrlclcrlttlc
Sym
Ml n Tvp"
Mar Unltr
Condlllonr
DC
CHARACTERISTICS
Clock
Inputr
High
Low
Loglc Inputr
Lo w
High
(Al l
LinesexceptBOROY)
High
(8us
Data
ReadyLine
See
Note)
Loglc Outputr
High
Low
(Oata
Bus
LinesDO-D15)
Low
(Bus
ControlLines,
BC1.BCz.BDrR)
Low (AllOthers)
Vrxc
Vrrc
Vr l
Vr x
Vr*r
Vo*
Vor.
Vor
Vou
10.4
0
0
2. 4
3. 0
2:
Vcc
Vo o
0. 6
0.65
Vcc
Vcc
0.5
0.45
0.45
v
v
v
V
v
V
V
lox
=
1@pA
lor
=
1.6mA
lor
=
2.0mA
lor= 1.6mA
AC CHARACTERISTICS
Clock Pslrc lnputr,
61
or
02
Pulse
Width
Skew
61,
62
delay)
Clobk
Period
Rise
&
FallTimes
llerler SYNC:
Delay
rom
d
DO-DI5 Bur
Slgnrlr
Output delay
rom
61
(tloal
to
output)
Output delay
rom
62
{output
o tloat)
Input
setup
ime
b€tore
d1
Inputhold
imeafter
61
Bur Control Slgnrlr
BCI,BCaBOTR
Outputdelay
rom
61
BUSAKOutput
delay
rom
61
TCI
Output delay
rom
01
TCI
Pulse
Wiclth
EBCA output delay
from
BEXT
lnpul
EBCAwait ime
or
EBCI
nout
62,
r6 2
I r2,
t2t
tcy
tr, tf
lm s
teo
tar
tgr
tsa
loc
tsu
tro
t tw
toe
lrr
oc
0
o.25
10
t:"
150
200
300
<. v
15
30
o<
200
15 0
400
ns
ns
pS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NS
1 TTL
Load &
25
pF
I
l
I
APACITAXCE
61, 62 Clock Input capacitance
lnput
C.p.ctt nc.
DO-D15
All
Other
Oulpul
Crprcltrncc
OO-O15
n
high mpedance
tate
c61,c6/
"l
VD
20
6
t
o
30
12
10
15
pF
pF
pF
pF
TA
=
+25'C:
Voo=
*12V;
Vcc=
+5V;
Var=-3V; tC1t62=120ns
16-D4
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cP1.610
ELECTRTCAL
HARACTERTSTTCS
CP1610)
Marlmum
Rallngr'
Voo,
cc,
GNDandallother
npuvoutputoltages
with
espect
o Vrr
-0.3V
o
+18.0V
Storage
emperature
. -55"C o
+150"C
Operating
emperature
.0"C
o
+70oC
Standerd
Condltlonr:
(unless
otherwise
noted)
VDD=+I
V+5%,
0mA(typ)
11OmA(max.)
Var=
3V11096,
.2mA(typ)
zmA(max.)
Vcc=+5V15%,
2mA(typ)
25mA(max.)
Operating
emperature
T^1=g'g
o
+70'C
"Typical
values re at
+25'C
and nomtnat
oltagos.
NOTE:
The
Bus Oata
ReaDY(BORDY)ino s sampledduring ime
period
TSI sfter
I BAR or
ADAR
bus
control
signal.
BDRDY
must
go
low
requesting
wait state
50
ns
b€toro ne end
of
TSI
and
remain
low
for
5O
ns minamum.
BORDY
may
90
high
asynchronously.
n respons€
o 8ORDY,
he
CPU
willextend
bus
cyclasby
aclding
dclitional
microcycles
up to
a maximum
of
40
ssec cruralion.
'Exceeding
these
rat ings could causg
permsnonl
damage
to theso clevico3.
Functional opsration
at thes€ conditions
i3
not
implied-opefat ing
condit ions
at6
sgecitied
below.
.)
Charactcrlrllc
sym
Ml n
Typ"
Mrr Unltr Condlllonr
OC CHARACTERIST ICS
Clock
Inputr
High
Low
I
nput current
Loglc Inputr
Lorv
High
(Al l
Lines
exceplEDRDY)
High
(Bus
Data
Ready
Line
See
Note)
Loglc Outputt
High
Low
(Data
Bus Lines
DO-O15)
Low
(Bus
ControlLines,
BC1,BC2,BDtR)
Low
(All
Others)
Vrxc
"r'
Vr r
Vr x
Vrxa
Vor
Vo r
Vo l
Vor-
10.0
:
0
2.4
1n
,: Vc c
Vo o
0.6
t5
0.65
I"
Vcc
0.5
0.45
0.45
v
v
mA
v
v
v
v
v
v
v
Vnc
=
Voo
-1
lox
=
100rrA
lor
=
1.6mA
lor
=
2.0mA
lor
=
1.6mA
AC
CHARACTERISTICS
Clock
Pulrc lnputr,
dl
ot
02
Pulse
Width
Skew
61.
d2
delay)
Clobk
Period
Rise
&
FallTimes
Mr3ter SYNC:
Delay
rom
6
DO-O158ur Slgnrlr
Output delay
rom
dl
(t loat o output)
Output
delay
rom
62
(output
o
l loat)
Input
setup
ime
before
61
Inputhold
ime
after
d1
Bur
Control Slgnrlr
8C1.BC2.BDrR
Output
delay
rom
61
BUSAK Output
delsy
trom
61
TCI
Outputdelay
rom
61
TCI Pulse
Width
EBCA
output
delay
from
BEXT
input
EBCAwait
ime
or
EBCI
ngut
r62,
r62
r12
tz l
tc y
tr,
tt
tms
tao
lar
ta r
taa
toc
tgu
lro
tr w
toe
ter
250
0
0. 5
;
10
10
150
M
300
2.0
15
30
200
26
:
15 0
400
ns
ns
/rs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1 TTL Load & 25 pF
I
I
I
I
I
CAPACITANCE
d1, 62
Clock
nput
capacitance
lnpul Crp.cltrnc
DO-D15
Al l
Other
Outpul C.p.cltrnc.
OO-O15
n
high
ampedsnce
tale
co1,c6 :
clN
Co
20
6
(
8
30
12
10
15
pF
9F
pF
pF
TA = +25"C: Voo= +12V;Vcc= +5V;
Vrr
=
-3V:
t61
t
02
=
120ns
16-D5
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roB
680
ELECTRICAL
HARACTERTSTICS
Maximum
Ratlngs'
V99
and
Vsg and all other
nput/outout
oltages
withrespect toGND..
. . . . . . . .
. -0.3vto+18V
StorageTemgerature
. . . . .
-55octo+150"C
Operat ingTemperature
. . . . . . .0oCto-70oC
Standard Condlt ions
(unless
otherwise
noted)
All voltages eferenced
o GND
VDo:
*12V
=50/b
V66:
+$\rr
: or'o
Operat ing
emperature
Te)
=
0'C to
t70'C
'Exceeding
these rat ings
coulC cause
permanent
amage.Functionat
peration
of
th is
devrce
at these
condit ions is not
implied-operating
ranges
are
specit ied
Derow.
Characterlgllc
Symbol Mln
Tvp" Ma r
Unll
Condlllon
OC
CHARACTERISTICS
Clock
Input:
High
Lo w
Logic Inputs: High
Low
Logic
Outputs:
High
Low
AC
CHARACTERISTICS
Clock Inputr
eRi
Ctocx
eriod
Clock
width
Rise
&
Fall
imes
CAPACITANCE
1To
=
25'6,
.
Voo
= +12V,
Vcc
=
*5V)
Input
Capacitance: 0-D7
All
others
Output
Cagacitance:
Vinc
v
it c
Vi ,
vo h
Vo t
lPc
tcr, tct
cor,
0
z. q
0
2.4
0. 4
,:
Vcc
o
8
Voo
Vcc
4. 0
10
12
10
1<
ps
ns
ns
pF
pF
lon
=
100pA
lo,
=
1.6mA
V,n
=
0V
V'"
=
ov
' -Typical
values
are at
*25oC
and
nominal vol tages
TIMING
DIAGRAM
1TSi1
'TS21
lTS3p lTScq tTSlt
'TS21
_l
tlc
--------------tl
1TS31 lTSal tTSlt 1TS21
'rS3p
---.1
cK1'
-r
EO|F
I Y
a. t
q. r
I
A
r /*
4
Noter
CK
1
not
drawn to scale
--'tJ
toc
F-
CIRCUIT DESCRIPTION
This
circur l
rs
desidned
to
provrde
al l the data butter ing
an d
control
tunct,cns
requirecj
when Intertacing the
Seties
l600
Mrcroprocesscr
Syslem
lo a srmple
perapheral
evice.
Oata
s
translerred
o and lrom lhe
peripheral
on
16
bidirecl ional
lnes.
each of
whrcn
can be considered
o
be an
inpul
or oulput.
Th e
transterot
Inlormation with
the
CP1600
s
accomglished
ra
an 8-
bi t
highway,
he 16-brts
betng
transterred
s
two
8-bi t bytes.
he
register
addressesare assrgned CP1600
memory locat ions.
as
lol lows (N
is an
arbrtrary
start ing address):
Regl ler
Addre3r
N
N. 1
N' 2
N* 3
N* 4
N. 5
N. 6
N* 7
Oercrlpllon
Control
Regtster
Data Register
Low Order 8-bi ts
Oata
Register
High
Order 8-bi ts
Timer
Low Order 8-bi ts
Trmer
Hrgh
Order 8-bi ts
Pertpheral
nterrupt
Address
Vector
Timer
Interrupt
Address Vector
Error
Inlerruol
Actdress
Vector