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APPLICATION OF ANONBOARD PROCESSOR

TO THE OAO C SPACECRAFT

P

(NASA-TM-X-65937) APPLICATION OF AN

UNBOARD 2ROCESSOR TO THE 0;10C SPACEC3AFTW.N. Stewart, et al (NASA) 7209B

121 p

N72-27211

UnclasG3/08 34247

W. N. STEWARTR. HARTENSTEINC. TREVATHAN

JUNE 1972

co GOMM SPACE FLIGHT CENTERGREENBELT, MARYLAND

X-715-72-226

APPLICATION OF AN ONBOARD PROCESSOR

TO THE OAO SPACECRAFT

W. N. StewartR. HartensteinC. Trevathan

June 1972

GODDARD SPACE FLIGHT CENTERGreenbelt, Maryland

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ABSTRACT

This document describes the design of a stored program computer for spacecraft useand its application on the fourth Orbiting Astronomical Observatory (OAO Q. The com-puter, referred to as OBP 1, is a medium scale, parallel machine with a memory capacity of16 384 words of 18 bits each. It possesses a comprehensive instruction repertoire and oper-ates on 45 W of power (including the do-to-dc converter). The machine operates at a500-kHz rate and executes an add instruction in 10µs. The primary functions of OBP 1 onOAO C will be auxiliary command storage, spacecraft monitoring and malfunction reporting,data compression and status summary, and possible perfor:-'ance of emergency correctiveaction for certain anomalous situations.

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PRECEDING FA,-' PT,ANK NOT FILMED

CONTENTS

Page

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

List of Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . vii

I. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . 1

II. HISTORICAL DEVELOPMENT . . . . . . . . . . . . . . . . . . . 2

III. INTERFACE DEFINITION . . . . . . . . . . . . . . . . . . . . 3

General . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 3

Command and Timing . . . . . . . . . . . . . . . . . . . . . . . 3

Telemetry . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Stabilization and Control . . . . . . . . . . . . . . . . . . . . . 4

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

IV. OBP DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 6

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . 7

Central Processor Unit . . . . . . . . . . . . . . . . . . . . . . . 7

Input/Output Unit . . . . . . . . . . . . . . . . . . . . . . . . 8

SDHE Serial Data Buffer . . . . . . . . . . . . . . . . . . . . . . 8

Command Data Controller . . . . . . . . . . . . . . . . . . . . . 9

Output Data Shift Register . . . . . . . . . . . . . . . . . . . . . 9

Memory Dump Control . . . . . . . . . . . . . . . . . . . . . . 9

S&C Digital to Analog . . . . . . . . . . . . . . . . . . . . . . . 10

Physical Description . . . . . . . . . . . . . . . . . . . . . . . 10

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . 10

V. SOFTWARE SUMMARY . . . . . . . . . . . . . . . . . . . . . 11

Executive Philosophy . . . . . . . . . . . . . . . . . . . . . . . 11

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

v

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CONTENTS—Concluded

Page

VI. IMPACT ON GROUND OPERATIONS . . . . . . . . . . . . . . . . 12

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ground Support Requirements . . . . . . . . . . . . . . . . . . . 13

Appendix A—Input /Output Unit Description . . . . . . . . . . . . . . . . 19

Appendix B—Formats . . . . . . . . . . . . . . . . . . . . . . . . . 77

Appendix C—Detailed Description of Central Processor Unit . . . . . . . . . . 81

Appendix D—Qualification/Acceptance Test Plan . . . . . . . . . . . . 109

vi

LIST OF ACRONYMS

lk

A AccumulatorACMU Auxiliary command memory unitADR Address registerAIR Allowable interrupt registerAPH A phaseBL Block lengthBPH B phaseC Carry (register)CDC Command data controllerCDH Command data handlerCPU Central processor unitCRE Command receiver equipmentCSC Cycle-steal o ;ltrolD Decision (register)DMA Direct memory addressDTL Diode transistor logicEA Extended accumulatorELF Enable lockout functionETCU Experimenter's test control unitFDS Flight Data Storage (Branch)FWJC Fine wheel and jet controllerGCWD Gimbal command wordGFEI Government furnished equipment interfaceIC Instruction counterID IdentificationI/O Input/outputIOBB Input/output unit output bus bufferIRS Instruction registerISR Interrupt storage registerLSB Least significant bitLSR Lockout status registerLST Lockout status tableMAB Memory address lineMIB Memory input data linesMIBXXL Memory input bus (number) lowerMIBXXU Memory input bus (number) upper

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MOB Memory output data busMOB Memory output data linesMOBL Lower memory output bus.90BU Upper memory output busMOBXXL Memory output bus (number) lowerMOBXXU Memory output bus (number) upperMOR Memory operand registerMSB Most significant bitOA Or/and registerOAO Orbiting Astronomical ObservatoryOBP Onboard ProcessorOPL Expenment command lineOV Overflow registerP ParityPAGE Page registerPC Power converterPCM Pulse code modulatedPLM Friority logic matrixPPDS Primary processor and data storageSCALE Scale registerS&C Stabilization and controlSDHE Spacecraft data handling equipmentSLF Store lockout functionSLR Storage limit (register)SN Serial numberSS Subscript registerSSCU Spacecraft systems controllerSTSP Star Tracker signal processorWAITFF Wait flip-flop

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APPLICATION OF AN ONBOARD PROCESSOR TO THE OAO C SPACECRAFT

I. INTRODUCTION

This document describes the implementation of a computer for application on boardthe OAO C mission. The computer, developed at Goddard Space Flight Center (GSFC), wasintegrated with the spacecraft in February 1971. The primary goal of this new flight instru-mentation and its associated ground equipment has been to improve the performance of theOrbiting Astronomical Observatory (OAO) C. In achieving this goal, most personnel in-volved in the project have gained the experience necessary to take full advantage of thispowerful tool.

The Onboard Processor (OBP 1) interfaces with the rest of the spacecraft as shown inFigure 1 (DWG GE 1308566).* This interface has been kept very simple and is configuredin such a way that the OBP is not in line with any spacecraft subsystem. Hence, the OAOcan operate in all normal modes with or without the computer. Primary functions of thecomputer on OAO C are auxiliary command storage, spacecraft status monitoring and report-ing, limit checking, self-checking and diagnosis, and performance of emergency correctiveaction for certain anomalous situations. Secondary functions fall in the general category ofcircumventing single-point failure modes, whereby the computer serves as a backup in theevent of failures in a number of spacecraft subsystems.

t Experiment data processing will not be performed by the OBP on the OAO C mission,because the benefits to be gained by this function did not outweigh the interface complexity.Experiment data handling equipment already provides a very effective mode of operationwhich allows asynchronous sampling and storing of data under experiment control. How-ever, it is felt that the OBP could benefit the experimenter on future spacecraft in the areasof data handling and data-dependent experiment control.

The intent of this document is fourfold: (1) to serve as an informal specification,(2) to provide interface facts required by GSFC and Grumman Aircraft Engineering Corpora-tion spacecraft engineers, (3) to provide performance information required by operationspersonnel, and (4) to provide details of command and telemetry formats needed by the con-trol center and other ground support equipment computer programmers.

S

*Number in parentheses refers to applicable OBP 1 logic drawing.

1 -

The OBP was developed over a period of years by the Flight Data Storage (FDS) Branch.This development has included contracts with the Westinghouse Corporati-)n for fabricationof an engineering model control processor unit (CPU), and with Electronic Memories Inc.for power-switched core memories. Along with these contracts, the FDS Branch developedthe input/output (I/O) and power converter units, thus completing the OBP engineeringmodel system. The OBP engineering unit was integrated as a system in October 1969 andwas subjected to extensive thermal testing by the FDS Branch during November 1969through January

The OBP flight model was fabricated under a contract with Micro-Technology Inc.,which utilized a through-the-insulation weld technique developed by Micro-Technology.'This method of construction was used on both the CPU and I/O flight units, which werereceived at GSFC on March 1, 1970. The flight units were statically tested and ready forintegration into the OBP flight system on April 5, 1970. The memory units, fabricated andtested by Electronic Memories Inc., had been delivered by February 1, 1970; and the powerconverter, designed and fabricated at GSFC by the FDS Branch, was tested and awaiting in-tegration into the OBP system at this time. On April 5, 1970, all components of the OBPwere integrated into the OBP flight system, and thermal testing began. The OBP system wassubjected to many hours of thermal cycles and speed tests to verify the limits of operation.

During the temperature tests, problems with shorts occurring in the CPL' caused somerework of the micro-point welding. This problem was traced to the method of terminatingthe micro-point wires and to the wire routing technique used on the CPU. The CPU, beingthe first flight unit constructed with micro-point techniques, was not wired with the improvedrouting techniques used in the I/O unit and was, therefore, finally replaced with a secondCPU unit. This second unit, CPU 2, was constructed according to GSFC SpecificationsB-S-715-1 and B-S-715-3, which instructed the manufacturer of micro-point welded units inthe proper techniques to ensure flight quality hardware.

The first flight acceptance test performed in accordance with the OAO C OBP qualifi-cation/acceptance test plan (see Appendix IV) was completed on August 31, 1970. Duringthermal vacuum testing, memory unit serial No. (SN) 3 and CPU 1 were not found to bewholly acceptable. The memory unit was returned to Electronic Memories Inc. andrepaired. The OAO project at this time decided to replace CPU 1 as soon as possible, be-cause of its history of shorts.

The OBP was first integrated with the OAO C spacecraft on December 14, 1970. Pre-liminary integration was successful, and no interface problems occurred. The OBP was con-figured with CPU 1 at this time.

For the final flight acceptance test, which was started on February 22, 1971, the OBPwas configured with the CPU 2 unit and the repaired memory unit SN 3. On March 1, 1971,

*See "A versatile Low Cost Packaging Technique for Spacecraft Electronics", GSFC Document X-713-70 .333, GoddardSpace Flight Center, Greenbelt, Maryland, Much 1970.

the final OBP flight acceptance test was completed with no anomalies, and the OBP wasdelivered to the OAO Project for final integration with the OAO spacecraft.

The OAO flight software programs were used to verify that the hardware interfaceswere functioning properly in a dynamic test begun on May 26, 1971, and completed onJune 1, 1971. This included handling ACMU command transfers, loading, dumping, andchanging specific locations in OBP memory. In addition, the power control and stabilizationand control outputs of the OBP were functionally tested.

III. INTERFACE DEFINITION

General

The interfaces specified in this section were designed to minimize the impa,:t on thenormal spacecraft configuration while still allowing the OBP to demonstrate thoroughlyits performance value both to the OAO C mission and to more advanced astronomicalmissions. To this end, all necessary electrical interfaces in the OAO C exist as originally con-figured. Other than cabling changes, essentially no spacecraft modification was required forcomputer integration. The interface also has been designed to minimize the effect of possi-ble OBP failures on the normal operation of the spacecraft systems.

The interface connectors and circuits, shown in Figure 1, are in three major spacecraftsubsystem areas: (1) command and timing, (2) telemetry, and (3) stabilization and control.

Command and Timing

The most significai.t OBP interface with the spacecraft is the interconnection of sixrelays between the Commol nd Receiver Equipment (CRE) and the Primary Processor andData Storage (PPDS). This relay configuration, the same as employed in the Auxiliary Com-mand Memory Unit (ACMU) on OAO 2, provides a means for the computer to send com-mands to OAO subsystems via the PPDS with no modification to spacecraft hardware. Thiscapability will greatly extend the usefulness of the OBP 1 to the mission. For instance, thetask of using the computer to perform the function of the ACMU will be implemented.(More complex tasks that require this interface are discussed in Appendix A.)

These six relays are connected in such a way that the critical CRE-to-PPDS link isestablished with the relays in the released state. The relays are energized for a maximum ofonly 37 seconds and then are released by computer command. Four additional provisionsfor release of the relays are implemented as safety features; these are—

(1) Excluding the first 1-ppm signal following an energize command, all subsequent1-ppm signals are gated to cause the release of the relays.

(2) Existence of command presence at the CRE overrides all OBP control and releasesthe relays.

(3) Disabling of primary power causes release of the relays.

3

(4) The relays and relay drivers are logically configured such that the CRE-to-PPDSconnection is performed in spite of any single failure.

All ground control of the OBP is achieved via six impulse commands and two experi-memer's command lines. The impulse commands provide absolute control of the computerand actuate critical on/off functions. These are power on/off, enable/disable OBP, and en..able/disable OBP to Fine Wheel and Jet Controller (FWJC). All other functions are achievedby using the two experimenter's command lines. One line is used for loading of OBP pro-grams, internal OBP commands, and the first half of the command pair when the ACMUfunction is performed. The second experimenter command line is used for loading thesecond half of the command pair for storage. The format for storing ACMU-type commandsis essentially the same as that used for OAO 2. Format details are presented in Appendix B.

Other inputs from the PPDS are timing signals required for OBP operation.

Telemetry

The OBP receives all its spacecraft data through the serial data stream of the SDHE. Nodirect interface to any other equipinent is required. This serial data stream and a framesynchronization pulse ar- taken from existing outputs of the Government Furnished Equip-ment Interface (GFEI) unit. The serial data are clocked into the OBP I/O unit by a 1042-bpssignal derived from the PPDS.

The OBP has three types of outputs to the spacecraft telemetry system. One is 30 bits(two 15-bit words) in the SDHE main frame into which the OBP places various spacecraftstatus and performance code words and other low-frequency data. These 30 data bits areplaced in the telemetry slots originally occupied by inner and outer gimbal command wordsfor Star Tracker No. 1. Access to these slots is made by adding a gating circuit in se-ies withthe gimbal command word line which interconnects the PPDS and SDHE. To provide acontinuous flow of gimbal command data to the telemetry even if the computer is disabled,this circuit is powered by the spacecraft's 18-'V bus. This circuitry can be bypassed througha spacecraft signal controller unit (SSCU) relay. The second ­ output is a direct, pulse codemodulated (PCM), serial data stream to each wideband transmitter. This will normally beused to verify OBP memory contents, e.g., program or auxiliary command storage. At a bitrate of 50 kbs, any memory bank may be dumped twice in less than 7 seconds. The lasttype of data is 11 bi-levels for OBP status and voltage monitoring, and a single thermal-analog channel fer temperature measurement.

Stabilization and Control

Only three connections are required to the stabilization and control (S&C) system to allowcomputer control of spacecraft attitude: These are the roll, pitch, and yaw analog errorsignals. All information required to compute these error signals is obtained from the SDHEdata and requires no special interface. To implement this interface, digital signals are con-verted to analog and fed to the FWJC by way of the Star Tracker Signal Processor (STSP).Through use of one set of connections vacated by the omission of two star trackers, inputs

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to this unit are made with no hardware modification.. The analog voltage range is from —5to +5 V from a 500042 source.

Summary

The following lists summarize the OBP electrical interface requirements of the space-craft system:

Commands

(1) Two experiment command assignments

(2) Six impulse spacecraft commands

(a) OBP power on

(b) OBP power off

(c) OBP enable

(d) OBP disable

(e) OBP-FWJC drive enable*

(f) OBP-FWJC drive disable*

Timing Signals From PPDS

(1) 1 ppm

(2) Commani ratable

(3) Bit time 3

(4) Bit time 32

(5) Clock time 1

(6) Clock time 2

(7) Clock time 3

(8) Clock time 4

(9) Star Tracker No. 1 address

(10) Gimbal command shift pulse

(11) Gimbal command word

*These commands exist as Stu Tracker No. 1 inhibit sisal to STSP.

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Telemetry Input From SDHE

(1) SDHE serial data line

(2) Frame sync (bit 26, word 29)

(3) 1042 Hz

Telemetry Outputs

(1) 30 bits in the gimbal command word slot for Star Tracker No. 1 (one line)

(2) Dual input to wideband transmitters (two lines)

(3) 11 bi-levels and one thermal-analog channel to SDHE

Inputs From CRE

(1) Command message

(2) Message rate clock

(3) Carrier presence

Outputs to PPDS

(1) Command messagei'

(2) Message rate clock

(3) Carrier presence

Outputs to STSP (Analog)

(1) Pitch error

(2) Roll error

(3) Yaw error

IV. OBP DESCRIPTION

General

The major design objectives in the development of the OBP system were high reliability;low power requirements, small size, and ease of programming. Reliability was emphasizedin the design of the OBP at both the system and component levels. t°

At the system level, modular organization enables reliability enhancement through theease with which redundant subsystems may be d irectly added, although for the OAO Cinstrumentation, no redundant subsystems are included. Even though there are no spare F-

6

modular units, the memory system is organized in such a way that any one of the four unitscan be switched by command to contain the interrupt control locations, thereby protectingagainst a worst-case memory failure.

At the component level, the following steps were taken to ensure maximum reliabilityof all subsystems:

(1) Maximum use was made of monolithic integrated circuits.

(2) To minimize failures due to electrical stresses, circuit components that operatewell below rated values were chosen.

(3) Only those circuit techniques and components that have been tried and provenreliable were used.

(4) All active elements were "burned in" to minimize drift due to aging and to detectearly failures.

t

(5) The number of electrical connections was minimized, and all internal connectionswere either welded or soldered.

(6) All electronic subassemblies were encapsulated.

(7) All fabrication was performed in a clean room.

This section will provide a summary of the significant features of the memory, the CPU,and the I/O subsystems. A more detailed discussion of each of these units is contained inAppendices A, C, and D. ^.

Memory Subsystem

Briefly, the significant features of the memory subsystem are— ,.

(1) Core memory with clear/write and read/restore operating modes.

(2) MIL Spec. version qualified on OAO 2 (ACMU subsystem).

(3) Operating temperature range of —40°C to +80°C.

(4) Random access of 4096 words per unit with 18 bits per word.

(5) Four units for OAO C (16 384 words total).

(6) 2-µs cycle time.

(7) Operating power of 9-W average for program execution.

(8) Low standby power (less than 150 mW per unit).

Central Processor Unit

Significant features of the CPU are-

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(1) Grammatically structured machine language.

(2) 18-bit instructionLind data word size.

(3) 50 instructions, of which 30 require operand fetch.

(4) Binary 2's complement arithmetic.

(5) Fixed point with automatic scaling for multiply and divide.

(6) Hardware multiply and divide.

(7) Parallel data transfers.

(8) Single address one-word instructions.

(9) Low-power diode transistor logic (DTL) integrated circuit implementation.

1 10 ► 10-µs add time; 68-µs multiply time; 140-µs divide time.

1 1 1 ) 4-W power consumption.

t 12) Stored program protection.

1nl)uv(hitluit Unit

Significant features of the standard I/O unit are--

( I) Two cycle-steal control channels (d irect memory access).

(' 1 Both program and command initiation of cycle-steal channel.

(3) Redundant data bus in and out of memory (18 bits parallel).

(4) Eight interrupts with program-controlled priority levels.

(5) Low-power DTL integrated circuit implementation.

(6) 7.0-W power consumption.

Other significant components of the 1/0 subsystem for OAO C include the data chan-nels necessary for throughputting data between spacecraft components and the OBPmemory. The five peripheral circuits that are unique to the OAO C instrumentation areshown in Figure 2. These units are described in the following paragraphs.

SDHE Serial Data Buffer

The SDHE data arrive serially at a 1042-bps rate. These data, along with housekeepingdata, form one 18-bit memory word. This word is fed to the OBP memory through inputchannel 2 at the 1042-bps rate via a cycle-steal channel (direct memory address). After eachgroup of 26 words is input, a channel A block-length-equal-zero interrupt is generated. Thisinterrupt serves as the real-time clock for the software. A frame rate signal (word 29, bit 26)presently used by the GFEI is used to initiate the SDHE buffer hardware and also interruptsthe CPU for program synchronization.

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Command Data Controller

The command data controller (CDC) performs the dual function of inputting com-mands from the PPDS (for OBP use) and outputting commands to the PPDS for theirexecution. Inputs to the CDC are 30-bit command words from experimenter commandlines 1 and 2. Command bits 3 through 32 on both of these lines are gated into a common30-bit shift register. These bits are transmitted in parallel to the memory input bus or to thecycle-steal control registers. Since the memory bus is an 18-bit interface, the 30 bits aresplit into two words of 18 bits and 12 bits. Th: 18-bit word is composed of bits 5 through22 and enters the memory through input data channel 3. The 12-bit word is composed ofbits 3, 4, and 23 through 32 and enters the memory through input data channel 10 octal.A detailed description of the command formats and the use of the command words is pre-sented in Appendix B.

The output from the CDC is the 128-bit command format which is fed to the PPDSthrough the lines that are normally driven by the CRE. The relays shown in Figure 2 areenergized to allow this transfer of command message. A complete command message isgenerated within the computer and output through data channel 1 as a serial bit stream.This message is shifted via a cycle-steal channel at a 1042-kbs rate.

Output Data Shift Register

The 30-bit output data shift register, composed of two 15-bit halves, serves as a parallel-to-serial converter for placing data into the SDHE bit stream. Data are loaded into each halfof the register under program control through computer output channel 5. Since the 30 bitsare fed into time slots previously occupied by Star Tracker No. I inner and outer gimbalcommand words, shifting is achieved by the gimbal command shift pulses. Shifting controlis provided by the inner and outer gimbal select line, which determines the appropriate 15-bit portion to be output for a given period. As the serial data leave the register, they arecirculated back to the input to form continuous bursts of output data which are or-gatedinto the gimbal command word line to the SDHE. The 30-bit register is reset by the com-puter at the SDHE frame rate.

Memory Dump Control

For memory dumps, blocks of up to 4096 words may be transmitted to ground by com-mand control. The memory dump control (MDC) comprises a 32-bit shift register whichserves as a parallel-to-serial converter to output data at a 50-kHz rate to the wideband trans-mitters. The 32-bit register is loaded with 18 bits of memory data through output datachannel 0, and 12 bits of address from the appropriate cycle-steal control register. Anotherinput to the MDC register is the 32-bit synchronization code, which occurs every 64 datawords. As data are shifted out of the register, parity is determined, and a bit to form oddparity is inserted into the bit-32 time slot. The output of the MDC is a 65-word frame withthe format depicted in Appendix B. Data dumps are achieved by the cycle-steal mode of

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operation and can be initiated by the computer program or, in case of CPU failure or pro-gram error, by ground command to the MDC.

S&C Digital to Analog

The S&C interface supplies holding registers and three 6-bit (including sign bit) digital-to-analog converters for the three error output lines. The holding register is 18 bits long andis loaded by program control through output data channel 4. Each analog converter has anoutput range of — 5 to +5 V and an output resistance of 5000 St.

Physical Description

The OBP is composed of seven separate boxes, packaged as shown in Figure 3. Thetotal weight of the computer, excluding the mounting plate, is 64 pounds; a breakdown ofthe volume and weight of the major components is given below:

Unit Volume Weight(in. 3 ) (lb)

CPU 270 14.75I/O 300 16.25Memories 500 23.5xPC 190 8.0Cables — 1.5

Three Deutsch connectors, specified in Figure 1 and designated AJ1, BJ2, and BJ3, aremated to spacecraft cables.

Power Consumption

The power requirements for the OBP in various operating modes are listed below.(Estimates of program execution time indicate that the computer will be in the halt statefor a significant amount of time between real-time clock interrupts; this means the averageoperating power may be lower than indicated.)

+28 V (unregulated) Operating Mode a

17.7 W standby30.0 W average operating51 W command transfer (for 37-s intervals)

+ 18 V (regulated) Operating Mode

0.2 W continuous

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V. SOFTWARE SUMMARY

Executive Philosophy

The development and efficient checkout of those programs that are to fly on the OAO Cmission are critical phases. Ease of programming was a prime consideration in the selectionof the OBP instruction set and in the implementation of the OBP support software system.*In a real-time environment, however, problems often arise in the areas of time synchroniza-tion and input/output. In order to alleviate interface and timing problems for the OAO Cmission, a real-time executive philosophy which eliminates some of the problems of applica-tions programming was developed. The executive performs all input/output operations, in-cluding data decommutation and formatting; processes all interrupts; and monitors theexecution of all applications programs with a time-shared, multipriority scheduling algorithm.Synchronization between the transfer of data into the OBP and the execution of programsegments is derived from a real-time clock interrupt with a 26-ms period (SDHE data wordrate). A new job cycle is initiated once each 1.59 s (an SDHE main frame) with an SDHEword-29, bit-26 interrupt.

Telemetry data from the SDHE are input along with OBP housekeeping data at a 1042-bps rate. As a result of the block-length-equal-zero pulse, a real-time clock interrupt requestis generated for each 26-bit SDHE word. Following the repacking of data by the executiveprogram, all SDHE data are stored in a 320-word spacecraft data buffer in the OBP memory.The commutation identification bits contained in the SDHE data are used to control thestorage assignments of subcommutated data. Two words in the spacecraft data buffer con-tain system time and program code. Twenty-four buffer words are used for storage of StarTracker gimbal command and error angles. Including all subcommutated levels, there are15 SDHE digital words. One OBP buffer word is used to hold one-half of an SDHE digitalword, and 30 buffer words contain all 15 SDHE digital words. The remaining 264 bufferwords are used to store the 8-bit measurement of the 264 analog signals input to the SDHE.

When each SDHE main frame word is stored in the OBP memory (every real-time clockpulse) the executive program determines which applications program shall next receive con-trol. Determination is based on both time and priority. A 16-word table is associated witheach applications program. Three of the 16 words in each table indicate (1) which wordnumber of a frame the worker wishes to begin computation, (2) the maximum computationtime per frame for the worker, and (3) the priority of the worker. Thus, when each SDHEword is received, and also when an applications program has finished, the executive programdetermines if any new job requests are present and, if so, which is of highest priority. Con-trol is passed to the job request having the highest priority, and the status of any programthat may have been interrupted is saved so that control may be smoothly returned to thepreempted program. A check is also made at each SDHE word time to determine whetherthe job in process has equaled its allotted computation time per frame; if so, the status of

*See "Support Software for the Space Electronics Branch On-Board Processor", GSFC Document X-562.68-388,Goddard Space Flight Center, Greenbelt, Maryland, November 1968.

II

this job is saved so that it may be resumed during the next frame. Other words in the 16-word table associated with each worker are used to hold the status of a worker if it is in-terrupted. Basically, then, workers are serviced on a priority basis after their starting timesare reached; and, to eliminate a queuing problem from frame to frame, the total processingtime for all jobs is kept less than 65 word intervals. The reason for giving a "time to start"option to the worker programs is to allow time-critical tasks to begin processing as soon aspossible after the inputting of spacecraft data to be used by those tasks. The frame-syncinterrupt is used to reset the real-time clock counter and thus maintain synchronization withthe SDHE input data stream.

Interrupts

Eight interrupts are implemented for the OAO C mission. Interrupt 1 is the initiateinterrupt and is unique in that it cannot be locked out; it is initiated either by ground com-mand or by recovery from under voltage on board and is used to initiate certain data loca-tions, clear off all interrupts, and pass control to the executive program. Interrupt 2, whichis requested when either a command 2 or a command I with bit 32 equal zero is received,is used to store OAO commands (ACMU function). Interrupt 3, which results from anexperiment command with octal 40 in bits 23 to 28, is used to send code words to theexecutive program. Interrupt 4 is SDHE frame sync (word 29, bit 26) and is used for syn-chronizing the inputting of SDHE data. Interrupts 6 and 7 correspond to cycle-steal chan-nel A block-length-equal-zero and channel B block-length-equal-zero, respectively. Theseinterrupts are requested after the last transfer to memory of a data block when the blocklength register has been decremented to zero; they signal that the block transfers are com-

lete. Interrupt 6 is implemented as the real-title: clock .,,,imp ainn - it occurs every 26 mspp p r.... e - -- -while SDHE data are being input through cycle-steal channel A. Interrupt 5 is the outlimitinterrupt and serves as a warning that memory storage is being attempted outside of estab-lished storage limits. Interrupt 8 is a time reference from the SDHE at the inner gimbalcommand rate.

VI. IMPACT ON GROUND OPERATIONS

General

The operation of the OBP will undoubtedly require an increase in OAO control centeractivity, especially in the command and data handling areas. It is important to note, how-ever, that overall spacecraft operation can be significantly improved by the appropriate useof the OBP. As previously outlined, the OBP is capable of full-time, in-depth spacecraftmonitoring. The results of this monitoring could provide a report of significant events and/or suspected or real problems to the ground either automatically or upon request.

The provisions for OBP command capability not only provide for the duplication ofthe ACMU function as flown on OAO 2 but also opens up a whole new area of highlysophisticated operational techniques that will have enormous impact on the present OAOoperational scheme. For instance, the OBP could be programmed to make logical decisions

12

on input data and, based on the results, either perform experiments or take predefinedcourses of action. It is therefore possible to make the OAO self-diagnosing and self-adaptingto any combination of measurable circumstances. This area requires much further study ifit is to be fully utilized. Fortunately, the OBP software repertoire can be changed at anytime, even after it is in orbit, in response either to unpredictable occurrences or to new re-quirements generated by the operations manager.

Ground Support Requirements

In addition to the impact on operational concepts and procedures, the OBP requires asignificant computer capability within the control center. The most important of theserequirements is the need of a computer to decipher and appropriately display the inforina-tion contained in the two OBP words in the SDHE format. Interpretation of these wordsmust be performed in real time if full advantage is to be taken of the subsystem statusreport feature. A second requirement is that of inputting a wideband dump of OBP memoryinto a ground-based computer and performing a bit-by-bit check on the array. This is neces-sary for validating new program loads and analyzing the results of certain diagnostic execu-tion procedures.

Many other requirements on the control center computer will become apparent as OBPsoftware progresses and operational philosophies develop. It is anticipated that many of theactual flight worker programs will be partially specified and designed by the operatingpersonnel. This should circumvent incompatibilities between the onboard programs and theground users.

The software schedule included in this report covers only those efforts necessary towrite and test OBP flight programs. The SDS-920 system at GSFC has been used to test allauxiliary command functions with a background of SDHE activity by using existing com-puter interface hardware and a PCM simulator. The proper operation of all applicationsprograms are being verified by using the SDHE simulation program developed for theSDS-920 and SDS-9300 systems. A complete dynamic test of the OBP on the OAO C space-

= craft is now underway and has met all major milestones necessary for spacecraft operations.So that proper OBP operation can be verified at a maximum of I/O activity and programexecution complexity, auxiliary command functions are performed while subsystem equip-

{ ment faults are tested and memory dumps are requested. Doing all of these things simul-taneously requires a ground command and wideband telemetry capability to send commandsto the OBP and verify memory dumps from the OBP. Provisions are being made to simulateequipment fault conditions in SDHE telemetry and process the SDHE data-in the test facil-ity to verify that the OBP has correctly reported these faults. An important segment ofground support software is being used to convert a set of 18-bit words into the experimentcommands required to send these words into OBP memory so that the in-orbit reprogram-ming feature can be tested. It is worth noting that this ground support software develop-ment has two incidental benefits: It represents the bulk of the support software requiredfor orbital operations, and it is being effectively used to aid in OAO subsystem integrationin that the OBP is monitoring and reporting the status of subsystems in a manner that wouldplease the most demanding diagnostician.

13

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15

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17

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APPENDIX A

INPUT/OUTPUT UNIT DESCRIPTION

INTRODUCTION

A major objective in the design of the I/O unit for the OBP was to provide for multi-mission applicability. This requirement was met by defining an I/O interface unit that couldbe tailored to the specific mission requirement with minimum impact on the CPU ormemory design. To enhance further the versatility of the I/O unit, a sign ; ficant portion ofit was designed so that for a variety of mission applications it would remain unchanged orrequire only minor modifications. This portion of the 1/0 unit includes—

(1) Two cycle-steal control (CSC) channels.

(2) Eight interrupt channels with lockout control.

(3) The I/O unit output bus buffer (IOBB).

(4) Ten data channels (five input and five output).

(5) The I/O unit control logic.

Also included with this group of the hardware, but functionally separate from the I/Ounit, are the system clock and the memory access controller, referred to as the bus control-ler. The special section of the I/O unit that was designed for the OAO C applicationinc!udes-

(1) The CDC.

(2) The MDC.

(3) The gimbal command word shift register.

(4) Six digital-to-analog converters.

A block diagram of the 1/0 subsystem is shown in Figure Al.

CYCLE-STEAL CONTROL

Cycle-steal operation is a method of transferring a block of data to or from memoryindependently of program execution. The CSC "channels", hereafter referred to as theCSC's, provide both memory addressing and read/write control to the memory. They also

19

handle the requesting of memory cycles through the bus controller (see "Bus Controller",below), which actually effects the interleaving of memory activity sometimes referred to as

aft "cycle stealing".

Implementation

The OBP has two CSC channels: CSCA and CSCB. The two identical CSC's are com-pletely interchangeable and thereby provide a degree of redundancy in the I/O unit. Inaddition, since they can operate simultaneously on different tasks, they provide addedflexibility to the programmer.

Operation

Each CSC can be linked to any of the first four data devices. Using the request-acknowledge technique throughout the operation, the CSC maintains data communicationat the device-dependent rate by interfacing the device and memory. Activity of the CSC isinitiated, terminated, or reassigned by executing a CONNECT TO instruction or by aground command via the Command Data Handler (CDH). Termination of the CSC activityalso occurs when the block length (BL) has been decremented to zero. As each request fromthe external device is acknowledged, the CSC increments the starting address by one countand decrements the block length register by one count until BLA or BLB equals zero. Atthis point all further requests on that particular channel from its external device are ignored.This points out that a maximum block length (7777 8 ) will result in accessing only 409610rather than 4096 10 memory locations. Accessing the remaining memory location isachieved by re-initiating the CSC with the appropriate address and block. As the blocklength register is decremented from one to zero, an interrupt is generated: interrupt 6,called BLA = 0 and associated with CSCA; and interrupt 7, called BLB = 0 and associatedwith CSCB. These interrupts signify to the CPU that the buffer transfer on the respectiveCSC channel has been completed. The CPU may then reassign the CSC to new tasks as theneed arises.

Hardware Description

The two CSC channels in the OBP are identical and separate. Each contains a 16-bitstarting address register and a 14-bit control register (Figures A2 through A5; GE 1308724-27).Functionally, the control register has a 12-bit block length register and a two-bit device (data:hannel) register. The starting address register is a fully parallel, 16-bit up-counter; the blocklength register is a fully parallel down-counter; and the device register is a two-bit reset-set(R-S) latch register.

These registers are loaded by using a common clear and selective set technique. At thetrailing edge of the appropriate CSC acknowledge, the starting address register is incrementedby one, and the block length register is decremented by one until it equals zero.

20

CSC Initiation

CSC operation can be initiated in two ways: program control and command control.

Program control. Under program control, a CSC is loaded from the IOBB upon theexecution of a CONNECT TO (M) instruction. This instruction causes the content ofmemory location M to be loaded into the control register and the content of the CPU aL..;u-mulator to be loaded into the starting address register. During the CONNECT TO instruc-tion, the CPU sends two control signals, called A phase (APH) and B phase (BPH), to theI/O control unit to indicate which of these two data transfers is in progress.

For purposes of the following discussion, refer to timing diagram of Figure A6. Duringthe APH, data are transferred from a memory location to the IOBB. Sequentially in thetime between APH and BPH, both the control register and starting address register of theparticular CSC are cleared; then, the control register is loaded with data from the IOBB.Also during this interval, the CPU stores the content of the accumulator in location 7 of thefixed memory bank. During the BPH, the content of location 7 is read out of memory andplaced in the IOBB; from there it is transferred to the starting address of the appropriateCSC. The CSC is now initiated and ready to honor data requests from the specified device.These requests are honored until the block length register equals zero.

Command control. Under command control, two commands must be sent consecu-tively to the command data handler to initiate a CSC channel. An experiment command(FN CODE 01) to load the control register must be sent first. This command clears boththe starting address and control register of the specified CSC and then loads the control

x register. A second command (FN CODE 02) containing the starting address may be trans-mitted next. (Details of all command formats are discussed in Appendix B.)

CSC Status Monitoring

Once the CSC is in operation, its status can be continuously monitored under programcontrol. The content of the block length register and the device number assigned to eitherCSC can be examined at any time by executing a data input instruction LET INPUT FROMon data device 6 for CSCA and on data device 7 for CSCB. This capability provides theprogrammer with all the information needed for adequate monitoring and control of theI/O unit activities.

Logic Reference

For complete details on logic implementation, refer to Figures A7 through A9(GDI 136184, GD1136182, and GD1136185).

21

INTERRUPT CONTROL

Introduction

As is the case with most general-purpose digital computers, OBP has a priority interruptsystem. The interrupt control portion of the I/O unit stores and gates the individual inter-rupt, and in any given clock cycle allows only one interrupt to pass to the CPU for processing.These control functions are accomplished with an Interrupt Storage Register (ISR), a Lock-out Status Register (LSR), an Allowable Interrupt Register (AIR), and a Priority LogicMatrix (PI.M). A block diagram of this hardware is shown in Figure A10. The hardware pri-ority logic prevents a conflict when several interrupts allowed by the AIR are waiting to beprocessed. The contents of the LSR are stored in the appropriate interrupt priority, fixedmemory locations and thus provide programming control over the order in whit h interruptswill be processed.

OAO C Interrupts

For OAO C, eight interrupts were implemented; they are as follows:

(1) INTRI (INITIATE): Initiates program execution. A ground experiment com-mand 1 with an octal code of 20 in bits 23 through 28 will generate this interrupt.

(2) INTR2 (ACMUFN): Serves as an ACMU function interrupt used to store andtransfer OAO commands. It is generated when a command 2 is received, or when a com-mand 1 with bit 32 equal zero is received.

(3) INTR3 (PROG CMD): Used to send a code word to the executive program. It isgenerated when an experiment command line 1 has an octal code of 40 in bits 23 through 28

(4) INTR4 (FRAME SYNC): Used in a frame reference subroutine. It is generatedwhen FRAME SYNC (word 26, bit 29) is received from the SDHE.

(5) INTRS (OUTLIMIT): Serves as a warning when the CPU tries to store in a re-stricted area of memory. It is generated by the OUTLIMIT signal from the CPU when anillegal write operation is attempted.

(6) INTR6 (BLA = 0): Generated when the block length register of CSCA goes fromone to zero.

(7) INTR 7 (BLB = 0): Generated when the block length register of CSCB goes fromone to zero.

(8) INTR8 (INGEN): Used as a constant time reference should the SDHE fail. It isgenerated at the trailing edge of the inner gimbal enable signal (INGEN).

Operation

An interrupt from a device arrives at the input of the ISR in the form of a 1.5- to 3-µsnegative-going pulse. The stored interrupt is then compared with the corresponding bit

22

position of the LSR. If the LSR bit is a one, the interrupt is locked out; if the correspondingLSR bit is a zero, the interrupt will be clocked into the AIR. Since several allowable inter-rupts may exist in the AIR simultaneously, the priority logic must select the interrupt withthe highest hardware priority. This interrupt level is then converted to a four-bit number andpassed to the CPU. The interrupt number, also referred to as the interrupt address, is sent tothe CPU via four interrupt address lines. When the CPU reaches the end of an instruction, orthe END INST condition, it tests the interrupt address lines for the nonzero state on all fourlines and recognizes this as an interrupt request. As the CPU proceeds to service the inter-rupt, it sends an acknowledge signal (INTACK—) back to the I/O unit so that the serviced in-terrupt may be cleared from the SIR.

Lockout Status Table

Hardware priority on OBP is set with interrupt one having the highest priority and in-terrupt eight having the lowest priority. The sole purpose of the hardware priority is tobreak ties when two or more interrupts happen in the AIR. By selective lockout, however,the real order in which interrupts are serviced can be programmed. All lockout words as agroup are referred to as the Lockout Status Table (LST). If a simple priority order isassigned to the various lockout words, the resulting LST exhibits the shape of a pyramid as aminimum. As an illustration, consider the eight interrupts implemented for OAO C as havinga lockout priority shown in Table Al.

Table A 1—Sample lockout status table.

Interrupt Lockout Status Words

InterruptHardwarePriority

AddressBit

1 2 3 4 5 6 7 8

INITIATE 1 1 1 1 1 1 1 1 1 14ACMU FN 2 1 1 1 1 24PROG CMD 3 1 1 1 34FRAME SYNC 4 1 1 1 1 1 1 1 44OUTLIMIT 5 1 1 54BLA = 0 6 1 1 1 1 1 64BLB = 0 7 1 1 1 1 1 1 74INGEN 8 1 104

The order in which the interrupts will be serviced can be easily determined if one re-arranges the interrupts such that the number of ones in each column increases as the servicepriority decreases. This is shown in Table A2.

23

Table A2—Rearranged lockout status table.

Interrupt Lockout Status Words

InterruptHardwarePriority

ServicePriority

Bit

1 4 7 6 2 3 8 5

INITIATE 1 1 1 1 1 1 1 1 1 1FRAME SYNC 4 2 1 1 1 1 1 1 1BLB = 0 7 3 1 1 1 1 1 1BLA = 0 6 4 1 1 1 1 1ACMU FN 2 5 1 1 1 1PROG CMD 3 6 1 1 1INGEN 8 7 1 1OUTLIMIT 5 8 1

First, from Table A2 it can be noted that the interrupt lockout table exhibits a priorityservice that is at least pyramid. Second, if an interrupt X with low service priority has tolock out an interrupt Y with a higher service priority, the lockout status table has to haveone of the following two properties:

(1) All interrupts with higher service priority than X must be locked out.

(2) All interrupts with greater service priority than X must also lock out interrupt Y.

Table A3 illustrates the two properties when X equals the service priority of 7 and Yequals the service priority of 3.

In assigning the lockout status for an interrupt, it must.be kept in mind that an inter-rupt with a high service priority but with a low hardware priority can experience a delay.This would happen if while servicing an interrupt of low hardware priority (i.e., OUTLIMIT),several interrupts of higher service priority occurred (i.e., ACMU FN, BLA = 0, BLB = 0).The computer would service at least one instruction of the ACMU FN and BLA = 0 interruptsbefore servicing BLB = 0, which has a higher service priority than ACMU FN and BLA = 0interrupts.

There will be slight delays when a low service priority interrupt is set while servicing ahigh priority interrupt. At times, however, this delay can be used to advantage. Assumethat OUTLIMIT is set while servicing BLA = 0 interrupt. From Table A2, it is obvious that0UTLIMIT will be serviced only after honoring the higher priority interrupts ACMU FN andFROG CMD interrupts. The delay, however, can be used to hold off some non-time-criticaltask that is dependent upon BLA = 0 but also wants to be at the first level of interrupt.

24

Table A3—Property of lockout status table for interrupt 8 to lockout interrupt 7.

Interrupt Lockout Status Words*

InterruptsHardwareProperty

ServicePriority

Bit

1 4 7 6 2 3 8 5

INITIATE 1 1 0 1 1 1 1 1 1 1FRAME SYNC 4 2 1 1 1 1 1 1 1BLB = 0 7 3 1 1 1 1 1 1BLA = 0 6 4 W 1 1 1 1 1ACMU FN 2 5 W 1 1 1 1PROG CMD 3 6 W 1 1 1INGEN 8 7 WZ Z Z Z 1 1OUTLIMIT 5 8 1

*Property 1 = Z; property 2 = W.

Hardware Implementation of the I/O Unit

Lockout status register. The LSR is an 8-bit asynchronous R-S flip-flop register thatholds the lockout status word of the interrupt. It is one of the nonaddressable registerswhose content is exchanged whenever the CPU processes an interrupt or executes a RESUMEFROM or EXIT instruction. The register is loaded with the content of fixed locations inmemory (see Table A2) directly from the memory output bus bits 1 through 8. The registeris loaded by a strobe pulse generated by a Read Complete signal from memory and an enablesignal from the CPU (ELF). If address bit 13 is a one, the register is loaded from data in theupper memory output bus (MOBU); if address bit 13 is a zero, the register is loaned from thelower memory output bus (MOBL).

The output of the register is gated with the output of the ISR to determine the allow-able interrupts. In addition, it is also stored in memory. This occurs when a CPU memoryaccess acknowledge (CPUACI) and a store lockout function (SLF) are generated by the CPU.

Interrupt storage register. The ISR is an 8-bit, randomly set R-S flip-flop register thatstores the occurrence of each interrupt until the interrupt is serviced. It is loaded by negative-

- going pulses (1.5- to 3.0-µs) and is cleared with a negative-going Power Clear signal from thepower converter (PC). The individual flip-flop is also cleared whenever the individual inter-rupt is honored by the CPU.

The output of the ISR is and-gated bit by bit with the output of the LSR to determinethe allowable interrupts.

Allowable interrupt register. The AIR is an 8-bit register used to synchronize the allow-able interrupts with PH PROC. PH PROC is and-gated with an INT— signal from the CPU toeffect a clock for the register that is active only when the CPU is not processing an interrupt.

25

This ensures that the interrupt address does not change in the middle of an interrupt process-ing; it also provides an updated set of interrupts at the end of every instruction cycle. Theinput to the register is from both the LSR and ISR; the output is fed to the priority matrixlogic.

Priority logic matrix. Briefly, the PLM gate network establishes a hardware priority tobreak ties in the event that two or more interrupts are allowed at the same time. The com-plement of a high hardware priority interrupt is used to inhibit allowable interrupts of lowerpriority. The output of the PLM is fed to the encoding gates and then sent to the CPU as theinterrupt address.

I/O BUS BUFFER REGISTER

Description

The IOBB, an 18-bit register, is the interface between the Memory Output Data Bus(MOB) and the I/O unit. The function of the register is to store the 1/0 control words andall output data temporarily. As applicable, the outputs are directed to the 1/0 unit controllogic, the CSC channels, and all output data devices.

Operation

Prior to any load, the IOBB is always cleared. An IOBB load enable signal (IOBB LDEN)and a memory initiate ()IfCLK) signal are and-gated to generate an IOBB clear pulse (BBCL—).The load enable signal (IOBB LDEN) is also gated with a Read Complete signal from memory(UBRC— or LBRC—) to generate a 350-ns strobe pulse which enables the transfer o. datafrom either output bus to the IOBB register. In order to give initial transients time to settle,the strobe pulse is delayed about 200 ns after the data are laid on the bus by the memory.The output of the IOBB is broadcast to all output devices; that :..;., any device using the IOBBdata must gate them with the appropriate enable pulse.

Hardware Description

For the purpose of the following discussion, refer to Figure AI I (GD1308695). TheIOBB- register is an asynchronous register with 18 R-S latch flip-flops. The use of the latchflip-flops affords fast as well as asynchronous operation. Each flip-flop is loaded either fromthe upper or the lower output data bus, depending upon whether an even- or odd-numbered4K memory bank was addressed.

Strobe Circuits

The strobing circuits of both the IOBB and the LSR use two interconnected latches toregenerate a clean strobe pulse when a Read Complete (BRC—) signal is received from mem-ory. [The circuit is shown in Figure Al2 (GD1308576).] The BRC— pulse must be presentlong enough for the first latch to be set.

26

OBP BUS SYSTEM

Description

The bus system interconnects the 1/0 unit, the CPU, and the memories address and datalines. All interconnecting buses are redundant. There is a lower bus to interconnect the logicwith the even-numbered memory units and an upper bus to interconnect with the odd-numbered memory units. Each bus has four sections: memory address lines (MAB's), mem-ory output data lines (MOB'S), memory input data lines (MIB's), and control and power lines.

Address Lines

Each address cable has both the address lines and the power and control lines. Anaddress cable has 16 lines for addressing purposes, three lines for control, seven lines for +5 V,seven lines for —5 V, three lines for + 15 V, and six lines for ground. Since there are threesignal sources to the address bus (CSCA, CSCB, and CPU), the address and read/write controllines must be interconnected to perform the "logical or" function. This is done by connect-ing collectors of normally off transistors and holding these lines "high" (logic one state) bythe use of 510042 pull-up resistors connected to +5 V in the I/O unit. With this scheme, theaddress lines are energized to the logic zero state by the turn-on of any source transistor. fheread/write control line is pulled to ground by the appropriate snu;ce for a write operation.The other two control signals are Memory Initiate (MINIT), which is generated by the buscontroller, and Read Complete (BRC—), which is generated by the appropriate memory unit.In the case of MINIT, the only source is the bus controller, and the "or" function is notrequ ired; therefore, this signal is normally at ground and goes positive. This is a significantfactor in that ground on the MINIT line prevents undesired memory operations during OBP

;c turn-on or turn-off.

The line driver for the address and the read/write line is a low-power, collector gatecapable of sinking 6 mA. To speed the address line's return to +5 V (normal state), a 300-nspositive burst pulse is applied to the address bus at the end of each memory cycle. The ReadComplete control signal, like the output data lines discussed below, is terminated by a 1000-SE resistor to +5 V at the I/O end, but this one line also has added to it a 1000dt resistor to+5 V at the CPU end. The memory initiate control line (MINITL, MINITU) is normally lowand is pulsed by a 500-ns pulse which initiates a memory cycle.

Output Bata bus. There are 36 data lines in the output data bus: 18 lines from theeven-numbered memory units, and 18 lines from the odd-numbered memory units. The linesfrom the even-numbered memory units are referred to as the Memory Output Bus Lower(MOBXXL). The lines from the odd-numbered memory units are referred to as the MemoryOutput Bus Upper (MOBXXU). As discussed for the address bus, these lines are held nor-

= mally high and are driven to ground when a zero is put on the line. A 1000-52 resistor to+5 V terminates the lines at the I/O unit.

27

Input data bus. Like the output data bus, the memory input bus is made up of 36 datalines. Because each memory word is 18 bits long, only 18 of the lines go to each memoryunit. Those lines going to the even-numbered memory units are referred to as the MemoryInput Bus Lower (MIBXXL). Those going to the odd-numbered memory units are referredto as the Memory Input Bus Upper (MIBXXU).

Each line is held normally to a logical one (+5 V) by a 5000-St resistor to +5 V at the1/0 unit. A line is pulled to ground whenever a logical zero is placed on that line. A low-power, open collector gate capable of sinking 6 mA is used as the line driver. To speed thedata lines return to their normal state, a 300-ns positive burst pulse is applied to the bus atthe end of each memory cycle.

OBP SYSTEM CLOCK

The OBP clock is a simple two-phase clock system with each phase having a 25-percentduty cycle and a 180-degree relative phase difference. A 1.0-MHz squarewave generated by athree-gate crystal-controlled oscillator [Figure A13 (GD1136183)] is divided into two0.500-MHz timing signals which are gated with the 1.0-MHz wave to generate the two clocksignals PROCCLOCK and SYNCCL. In both the CPU and the I%O unit, these signals aregated through two additional logic levels to provide drive capability and preserve the originaltiming in both units. They become PHPROC and PHSYNC in the I/O unit and PROCCLOCKand SYNCCLOCK in the CPU. The basic frequency of the oscillator is determined by thecrystal. The clock pulse width was based on the clock response time of the 9040 bistablemultivibrator. The clock rate was selected as a function of the CPU carry propagation time.

BUS CONTROLLER

The function of the bus controller logic is to supervise the activity of the memory sys-tem (see Figure A7). It establishes priorities and synchronizes requests made by CSCA,CSCB, or the CPU for memory access. W11— any two devices make simultaneous :equests,the order of priority is CSCA, CSCB, and CPU. However, if simultaneous memory requestsare made by all three, the order of service is CSCA, CPU, and CSCB; therefore, the CPU isguaranteed at least half the memory cycles.

In order to prevent a short or an open circuit on a CSC request line from capturing allmemory cycles, the logic requires that a request be dropped after each memory cycle and beraised again for a minimum of one clock cycle (2.0 µs, in our case) prior to honoring a sec-ond memory cycle. Request on the CSC channels are synchronized on the leading edge ofPHSYNC and are acknowledged at the trailing edge of PHPROC. A block-length-equal-zeroon the particular CSC prevents additional memory requests from being honored. CSCrequests are also inhibited during the execution of an I/O instruction by the CPU so that theCONNECT TO instruction can be properly executed on an active CSC.

The outputs of the bus controller are three memory acknowledge signals (CCAACK—,CCBACK—, CPUACK—), a 300-µs burst signal (BURST—), and three identical 500-ns mem-ory initiate pulses. Two of the memory initiate pulses (MINITL and MINITU) are sent to

28

the memories, and the third (MCLK) is sent to the CPU for gating purposes. The BURSTpulse is used to charge the input and address buses to +5 V at the end of a memory cycle.For complete timing of these signals refer to Figure A14 (GD1 136189).

COMMAND DATA HANDLER

Introduction

The purpose of the Command Data Handler (CDH) is twofold: (1) to input commandsfrom the PPDS, and (2) to output commands to the PPDS for execution.

The inputs to the CDH are 30-bit command words sent over experiment command lineI or experiment command line 2. The data from both lines are gated with the commandenable signal and shifted into a common 30-bit register. These commands are transmitted inparallel to the memory input bus or to the cycle-steal registers as applicable. Because thememory bus is an 18-bit interface, the 30-bit command words are split into two words of 18bits and 12 bits. The 18-bit word comprises bits 5 (MSB) through bit 22 (LSB) and entersmemory through input data device 3. The 12-bit word comprises bits 3, 4, and bit 23through bit 32. This word is transmitted only to memory and is input through device 10.The details of the command formats and use of the command words are presented inAppendix B.

The output of the CDH is an OAO serial command that is transmitted to the PPDSthrough three lines: Command Presence (CMDP), Message (MESS), and 1-Kilobit TransferClock (IKBX). A complete 128-bit command message is generated within the computer andis output by a cycle-steal channel one bit at a time under software control through datadevice 1.

Hardware Description

The CDH comprises the command shift register [Figure A15 (GD1308597)], the com-mand decoding and control logic [Figure A16 (GD1308599)], the relay enable logic[ Figure Al 7 (GD 1308602)] , and the command transfer logic [ Figure A18 (GD 1308589)] .

Command register. The command register is a 30-bit serial-to-parallel shift register thatinputs data from experiment command line 1 (OPL1) or line 2 (OPL2) at a 50-kHz rate.The data are and-gated with the command enable signal (CMDEN) and shifted into the

• register at the trailing edge of clock time 2 (CT02). Bit time 3 (BT03) and bit time 32(BT32) are gated with CMDEN to determine the start and stop of shifting the commandsinto the register. The output of the command register is transmitted in parallel to thememory or to the control channels as determined by the decoded commands.

Command decoding and contro l . The function of the decoding and control logic is todecode the incoming commands and generate the proper control signals. Bit 3 and bit 32 ofan experiment command word are used to determine the type of command. Bit 3 is alwaysa one for commands received on OPL 1. Bit 32 received on OPL 1 is used to distinguish

29

between the first half of an ACMU command and all other OBP commands. A one in bit 3and a zero in bit 32 received on OPL1 indicates that bit 4 through bit 31 of the commandare the 28 bits of the first half of an ACMU FN command (see ACMU command format inAppendix B). As a result of this rendition, the Wait flip-flop (WAITFF) is set to a one state,and interrupt 2 (INTR2) is generated. The second half of an ACMU command must followthe first half because any other experiment command following the first half will reset theWAITFF and be treated as the second half of the ACMU command. When the second halfof the ACMU command is received properiy, WAITFF is reset and another INTR2 is

generated. Any experiment command is detected as being the second half of an ACMU com-mand whenever WAITFF is a one and bit 3 from OPL1 is a zero. If bit 3 and bit 32 fromOPL1 are both ones, bits 23 through 28 of the command are considered to be a 6-bit "hard-ware" function code determining an OBP command.

Relay enable logic. The function of the relay enable logic is to enable and disable thecommand transfer relays. Each relay driver consists of an R-S latch coupled to a relay drivercircuit. A special flip-flop that disables the latch 1 to 2 minutes after it is set serves as a back-up to prevent lockout of ground commands. Prior to any command transfer, the rc!ays areenabled under software control. At the end of a command transfer, the relays are disabledalso under software control. In the event that they are not disabled, the I-ppm signal dis-ables the relays within 1 to 2 minutes after they are set. A master clear command will alsodisable the relays. In the event that a ground command is sent, the relays are reset. [SeeFigure A17 and Figure 1 (in text).]

Command transfer control. For command transfer, only three master/slave flip-flopsare used. Basically, they serve as 1-bit buffers for each of the three signals associated withcommand transfer. The entire command message is assembled within the computer and isoutput under CSC control to device 1 at a 1042-Hz rate. Once the command message isassembled in memory, the 1042 clock generates a data request.

MEMORY DUMP HANDLER

Introduction

The purpose of the MDH logic is to provide a memory dump capability under CSC con-trol that can be initiated either by command or by the computer program. In both cases,dumps occur in blocks of up to 4096 memory words. When a dump is initiated by the pro-gram, the particular block of words is dumped only once, unless it is re-initiated. However,when the initiation is by command, „os only does the dump start with the first word of the4K memory bank selected, but the block of words is dumped twice. t-oiler control is pro-vided by the dump control logic [Figure A19 (GD1308600) and Figure A20 (GD1308598)],and data are output on data device ze; through a 32-bit parallel-to-serial shift register[Figure A21 (GD1308595)1.

30

Hardware Description

Dump shift register. The shift register is loaded in parallel with 18 bits of memorydata, 12 bits of address (bit 3 through bit 14 of the appropriate CSC), one bit for registrationpurposes, and one bit for parity. The odd parity bit is added as bit 32 of each word as thedata are shifted out of the register. The first word of each 65-word frame is a 32-bit synccode. For details of word structure and frame format, see "Dump Format" in Appendix B.The register is shifted at a 50-kHz rate, and its output is converted to split chase prior totransmission to the wideband transmitters.

Dump control logic. The function of the dump control logic is to generate the controlsignals for the proper data dump transmission. The normal dump format for a 4096-wordblock is 32 bits per word, 65 words per frame, 64 frames per dump. When dump is initiatedeither by command or by program, it is synchronized with BT32. The shift register is notcleared but is loaded with ones at the bits corresponding to ones in the frame sync pattern.This unknown data pattern is shifted out first and helps the receiver lock to the signal. Onthe next BT32, the proper frame sync pattern is loaded into the shift register, and the dumpoperation begins. If dump was initiated by program, it is terminated when the block lengthof the particular CSC equals zero; if dump was initiated by command, it is terminated by thecommand dump mode clear signal (CMDDMPCL—), which occurs at the end of the seconddump.

Data request and dump register load are done during BT32. During this time, clock time1 (CT01) and clock time 2 (CT02) are used sequentially to clear (CLRDMPR—) and then loadthe dump register with the appropriate address. Also, CT02 is used to generate data request.The data are loaded into the icgister by data device zero enable pulse (DCOEI). When not inBT32, the register is shifted at the trailing edge of CT03. During BT32, an odd parity bit isadded to the data stream, and the dump register is updated. For timing details refer toFigure A22 (GD 1308660).

Command dump logic. When a dump is initiated by command, only the CSC channelidentification (ID), the CSC block length, and the memory bank ID are sent as a command.As a consequence, when dump is initiated this way, it always starts with the first word ofthe selected memory bank. Another consequence is that the last word in the block cannotbe read out of memory because the block-length-equal-zero condition inhibits the bus con-troller from honoring the 4096 memory requests.

The command dump control logic avoids this impasse by momentarily clocking theblock length out of the zero condition. This allows full dump capability without impactingthe design of the bus controller. Fcr redundancy purposes, the selected block is also dumpedtwice.

When a dump command is received, as part of the dump initiation, the command dumpmode flip-flop (CMDDMPM) is set. A one in this flip-flop causes the block length controlregister of the selected CSC to be decremented to the 7777 8 state from the all-zero condition.This allows the bus controller to honor memory requests. After one additional request is

31

honored, the CSC is cleared and reloaded from the command register. This allows the blockof words to be clumped again. A one-bit counter (DMPI) is used to keep track of the numberof times the block has been dumped; and after the second time, the dump mode is disabled.For a complete timing detail, refer to Figure A23 (GD1308658).

GIMBAL WORD SHIFT REGISTER

The gimbal word shift register was developed to allow the OBP data to be inserted asStar Tracker No. 1 data. Should a failure occur in the OBP, this interface can be bypassedby a ground command to avoid interference with the normal mode of SDHE data_

The 30-bit register comprises two 15-bit halves and serves as a parallel-to-serial con-verter for placing data into the SDHE bit stream. Data are loaded in parallel into each halfof the register under program control through data output device 5. Since the 30 bits arefed into time slots previously occupied by the OAO Star Tracker No. 1 Inner and OuterGimbal Command Word, shifting is achieved by the clock formed by the leading edge of theGimbal Command Shift Pulses (GCSP) and the leading edge of CT01. Shifting control isprovided by the Inner-Outer Gimbal Select line (INGEN), which determines the appropriate15-bit portion to be output for the given period. As the serial data leave the register, theyare circulated back to the input to form continuous bursts of output data. The data arecomplemented and or-gated into the Gimbal Command Word (GCWD) line to the SDHE.Each of the two 15-bit half-registers is independently updated under software control at theSDHE frame rate. Bit 18 of the update word determines whether the inner or outer gimbalhalf of the register is to be refreshed: If bit 18 is a one, the inner gimbal half is loaded; if bit18 is a zero, the outer gimbal half is loaded. When the particular half of the register isupdated, shifting for that half of the register is stopped until the proper time slot for thedata is reached.

32

CONNECT TO DATA FLOW

"ANY" MEMORY LOCATION

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Figure Al-1 /0 subsystem block diagram.

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37

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39

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41

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45

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47

OMV

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49

OUTPUT DATA BUS (ODD AND EVEN, 36 BITS)W

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FU Q W FOW

cm

aU

7 (W.7 WH W d CU Jcc

LL

J O CC CC N UH0 W

Lu

H..Q^

yZ N¢ ¢1-Z

LL Z U2W

F f OL) QV 2 mZ O co

v_f0 OY !3 Lam

wU atn> ¢QIQZ ¢OU

uJ

m^Y

¢ Q

N

p U^ W H F ? p Q ¢> H U U

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zLLp?

aUOW

¢ Q

= J =

co ¢O Q U ¢ F Waazd p ZW ¢ aOd0

k

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4

50

T, FRAMs '

Mvmmgw-mmw•SVJ13B4 +SVJ 14 64 .SvJIDIISEDIME

IOBD18 'OBBIS Ioaw.EVJ16R9

YMM

I I

LBBLDB

e w a 1 e a

35 35 et14 X15 J15 JIS J15

MO U mmm Y llJA M00W 7L 6U MOdIU6 1

2 1 5 -L- 1 S 7— 1 4 2 I

rllVJl+A7 .svi15B2

1

IOBB18

wm IOW9 wwo IOBBa WW7 W07 IOW6 106136 Iows mm M

t?L , JT FRAMr45VJ13B4 45VJ14133 4 SW IS89

to , It o 1 a li

J14 JI6 415 J15 J18 114 JISMOM MOd14V MM4L MDBISU MO9L^ n "L

J i4 L 1 S 4 1 S 4

tt tIs

S 4

D15 F15 15 415 415 I

i J i 3gp ^$ [$ia U 1

11SMOBIL

4i

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LB 1

S'

3

I

TONWR ^^ f am" losel1 I b

E AIS

e 6 f i 8

05815 108D14 I05314 IOBD13 IOB613 IOW12 Iosat IOBDII I06Bq I08D10 lawka

45VJ1582 45W1481 .SVJISBI1 e a It I 10 1 I e

L2 2 1 1 t 1 Jig 1 1

15 415 J15 J14 J14 14 J14 Ji5 I5 IS 4115 aMODfU MOBIL MO MW L MID

1 I I S4 2 2 1 5 4 I t 4 1

I I 1 -F15 N►`f 1415 US 615 5 GI5 FmFIS 415 N15

6 3 3

LBBlD6 LBB^ V^W4 LB^D ^ ^BBID'3 ^^ ^ l^'$L'^Z

I 11 LBO

CAAIE2 CAATE4

IOB5LDEN

Aum 0,

IO8BLM r-

14 t5VAy84

151( A5

WaR1

AS 48,f

IL^

6dOM04—84 EFF

.5E

a2F-f

$?FF

PRECEDL'^G PAGE BLANK NOT FILMED

c A-M

inClT^ FRAM E CC ACL

c

CZ`BLE

CC EICI

1Y 4 4

E8 6 6

CBLXEIMac C8LXE4 MIME CUM

CBLIE3 CBAXE2

CAAxEI b CAAXE3 bI CAAXE2 CAAXE4

^)i

CBAIEI bCBAXE4 C8AIE2

I"CBATE4

NOTE: UNLESS SPECIFIED ALLRESLSTORS ARE 151(n

CCAACK M6ffoxI°m EOLDOUT FRAME

10 9 b J 10 9 b !V

CAA EN

CALIE3

CCAACKIA b CCAACK3A b CCAACKIL

CMIE4 CCMCK2A CCAACK4A C

E3

CMIE2

CBAIEI bCBAIE2

b CCBACKIA b Cl

CBAIE4 CCBACKEA

3A b CCEIACKIL b CCSACK3L

CCBACK4A CCBACK2L

14 ♦SVABB4

ISK A'S

1

A% 48,f

It

G110AS84n BUS2FF

51

i^R

BS

Im

r^SVCSB4

ISK CS

S _Ti Tm

rCIS 7a Pt

0l--oC LLLSP-FF

4910 ^r

6

T As 39r^7

wODAf^BLUFF

.ire Al2(GD1308576)—C Mml logic for CC, LSR, and IOBB registers.

53

V ^- 7socaI 30IK96 It

1 5 1 C7 13 4 5I

I

6 u CG

4.M ^

I

^5

ttOKC

°I 10

ECLOK 0I

I

6Krn ( CLOKCOWSVI

CLOCK IN T I 55-cCLOCK [XT^ I

i

- I

I

I

CLOKC Fe CLOKCON E 8

1- 31.1 MNa XTAL

It

PROCLOK

5C5

PRECEDING PAGE BLANK NOT FILM,!;

FOUCUT, FR" I

^l

FOLDOUT ,i -• OZO

!L-'

_.. _ _ . O PROCCLOC K (TO CM)

5 S 44 5 i P, ._ 6 PHPROC.— _OHALFCLOK DS PROC ^ Df D5 ^

3

^],. r11PROK D .6

CLOKPULSE o 5^— C5 ^ 5 i`'^N : OK F a 5 S Y , F^ . ,^3PHsYNC (TO CPU f T/0)

au -jam 5TNCCL D5 POSM

Figure A13 (GDt I:4j183)—System clock logic diagram.

XTAL

55

ACK NMI

SYHCPU

CCAACK

C^AI^AC^K

CCBACI^

CCeRKK

C 1^J"

A AO( NO, I A ACK HA E

B ACK NQ2S ACM 00.1

PRECEDING PAGE BLANK NOT PILMET

WAVEFORMS03 • I.O,iSEC FOR 1.00 MHt CLOCK

NPROC, - I I I I-1 I_J I L^J U U U U U ^—

ASYNC r^____n I ^^__ ^t n n n rssrN

CCGRA I A REQUEST 1M 1 A REQUEST N0 2 (TINS SHOWS A STF,ADY STATE RQST RESULTS IN ONLY 1 MEMORV CYCLE)

SSMC)

Tw ` S REQUEST NO11 -^ 0 REQUEST NO.P

TUR

CPU REQUEST N0.1 CPU REQUEST N04

CAST

XBST

:CAEN

5YNCB

CCEIEN

IDLE u u I

^ u -U

MCCLK n n n nOPEgAT1pNAL CWpKTERISTICS FOR CHANNEL A/ 8CgiTRdI SAM- OPERATIONAL CHARACTERISTICS FOR CPU CONTROL SIGNAL

THE REQUESTS MUST DROP AND REMAIN LOW UNTIL OCCVRAHCE OF THE WAVEFORM DEPICTS THE LEADING AND TRAILING EDGETHE ACKNOWLEDGE PULSE. FOR ADDITIONAL REQUEST MUST GO TO TIMING OF TYPICAL REQUESTS. A STEADY STATE *SV45VOLTS FOR A MINIMUM OF 1.00rSEC BEFORE DROPPINGi HOWEVER, RESULTS IN CONTINOUG CPU ACKNOWLEDGESOTHERWISE THE REQUEST MAY Nff BE ACKNOWLEDGED. RISEAND FALL TIMES ARC NOT CRITICAL BUT CANNOT BE INCLUDED INT HEI.00MSBC

G THESE REQUEST5 MAY BE ASSYNCHRONOUS

at 7Figure A14 (GD11361

FOLDOUT Fad I

A REQUEST N0,2 (TN5 SNOWS A STEADY STATE RQST RESULTS IN ONLY 1 MEMORY CYCLE)

QI 1 S REQUEST NAt

CPU REGAIEST Nat CPU we was

A ACK 110 2

a A" NG.1 I 15 ACK Nat

II CPU ACK NGL PII AsX NA!

TROL SIf NALS OPERATIONAL CHARACTERISTICS MR CPU CONTROL SIGNALRANCE OF THE WWEFORM DEPICTS THE LEADINb AND TRAIIIMG EDGE

UST GO TO TIMING O► TYPICAL REQUESTS. A STEADY STATE *SVINGI

F

HOWEVER, RESULTS IN CONTINOUG CPU ACKNOWLEDGESD. RISELUDEF IN

Figure A14 (GD1136189)—Clock and bus controller timing diagram.

57

uj^ ERwF- z

9 ^z 9Ale ► All

9AM A1O

9It 9

812 y ' 819^^ 3

CMDRB3

9 ^C9 4

6 4 to I 'I 015

i-ULDUUT FRAME

CED NG PAGE BLANK NOT FII,^ZBjPTtr

2 A 3 OPLIO► 9 It CMDLPM5

Cm—ITNR5 9 6CMDEN

Io 9

^^ ► 9 1A14 OPL20 9

N5CMOL

CMDLNI

9 9

CM^6 ' A6 ► AS3 3

CMDRCLK

croRee9 cMDlzsee claDae219 ►2 9 12 9

A9A4 ► B3 9 I B4y85

3 3

9B6

CMDR816 CMDRBIS

4 9 6 12 9

M RB ' B1O y I Bll0--

CII y H,C O

C15 n

CMDRCLK

FRAME 4Z,

AI3 1 ' I AlZ 14' Hl' AlI I9 I '" I A10 lg —^ A9

CMDRBZ

IS

CMDR62f.9 9 6ne g A7 9

MDRMY ^6

CMDR62a? CMDRB21 CMDR928 CMDR819 CMDR8169 g 9

F99Bq 9 65 y I 66 9 1 97 B8

3 13 CMDR62S 3 M 3 CM1^ 3

MDR812 CMDRSIt CMDRBIQ CMDkB9 CWVRB612 12 9 6 12 q 6 e 9 6 ' 9 6 e 9

[4W—F 514 g 615 g

C159 C14 g C13

3 DR81e 3 X11 3 M BIA ^;f3 CMD 9

CMDR8169 689 9

6

^pCMDRB6

9 6C12 0

Figure A15 (GD 1308597) —Command register logic diagram.

59

ST32EN

ORSCTO

fmivmCNIMENt

FOURXO-X IERO

C MDSYNCHRF.ExXZERo

TWOX

x2ERO

ONEX 1

XZERO =1

ZEROX

X ,SVEN

2EROxXFOUR

VTRNDCO

zmxXTWO

ZEROX 1G

XONE

CMDRB23CMS tcm-DWSTS

9CMDRB24 4CMDR825

MDRB23 9CMDRSE4 w

CMDRB?S 'CMDRS 3 ICM NT4 0OWRBo---3

I

CMDRBE60_CMDR827 5CMD4B28CMORBe& 9

aiSRm o--- !

C- DR,m o--

BT32EN ► 9 3 9CMDEN 1 9 3

DII s it MUM

CAADLNI O 2 DIZ CMID12 CMI63eE1 p

OT93 ^J 9T93EN

B i2 OPIB3E1 3EISME1 1 9 12 9 S NTR4000DCMDLNI CMI332E1 Is l! Dt^ N E15

CTWOOCM'DCLKE9

9DIS CTO

CtrlL H

1 9D14 9

3EIEi'l^EI4 6 15THAL

OPIBMWL

BT32EN 9 N y 9WAITff y CT99

a 2 2CouNTE92

ST63EN D13CTS20 NDFSNE

CIODUMB ^ E^ C 9 y w CT192fl EI2 Il ni^^CMDRCLK

1N— T^?2

WATrf

DCL 136 ---OCMDOL

PNPRX 9i 3 E4

'3 Em—Mi.

ST92

IST14AL

SSHFT

I^6vo-CMCRBBS°—

rVRE CEDING PAGE BLANK NOT FIT-XEB

rGLDG'UT FRANK

X ONE a---.^,^,,, /"B -

CMDR829^

CMS o'C6- 1 9

"2 I9D4 II d FOURX

i_^'F50

1

CWU)RB240 4 i

iW1 ^XD4

TWEEX

CMDR8250 VWDR823CM5WS- 4 0

9

if^^ b ON^A 5 D5

i ONEXC MDR5250 VCMDRS 3

CWBW 0 2 7 Z OX 'D5 u ZEROXp

CM^^S o 19 P ^ J"^CMDRBU ! ^

Py 111 SEVENO XCMDR027o 5CMDRBNB o

CMDRH26 99 X FOURMONO o N D7 o

ca^MGR^6

° Iz{9^ca

IT1'aP6u/

s ., x TWOCh

o0 O IL

CMD^82

v R ,Ao55^4lyl.s

%b )flO XONE

CMORBW°

CM B o 109 '^ ^^ l3'9

XIERO8

9E4

mmmn &T^-W-WVX 9CMDR924TWOX6

FOLDOUT FRAW oZ,

FOURXXZERO

C M05YNC It

x2ER0 DC9R

TwOx o-XZERO07 A,

C3tN I

ONEXXZERO C4 .2 D4 1 DMPM

tEROx 'rC4

G DID P m%SEVEN

CMDRD9

EEROX

XFOUR JIC":4

IOPAGZI%LOCPU

xLOCPUDID ION&

rRNDCO CI^1Cm

EEROX

C5 C D4 CMDAXTWO 0--- 9It 9

Ate' GIEI9

OipinNEROlt- Io 9 , CMDRB I$

Figure A16 (GD1308599) —logic diagram of commend decoding controls.

61

PRECEDING PAGE BLANK NOT FILMED F-OL.DOUT FRAME'

IOBDII12 6 ISCRTE I

'

X PC81 99FI3 I 1 3 F15 b

4

IPPM

RR E-

IOBDiq b DI5CRTEZ

819 F149

o—mv

L

IOg 1t b Dt5CRTE3

'129 XF'CRI3 FI E 9

FI3 to

DI RTE

MKSCL ^—

1oBDe 1x 6 DISCRTFI

X 1P^ '9

g 9 y FIO y

UwaF131

M

MBD7 12 b 015CRTES

X PC91 99 8 F9 9

69 IO^Dj DISCRnS4

AFL

IFPM

POOq AC8162 9 3 Y^ XACIVI

O

10 611

iz N IxX

F1i

GND F/IB9 3

XPC9

EOLDOUT FRAMEFOLDOUT. FRAME

RTES

NFF3

INFFI

PCO I9 PIC4 t o 93 Y

X F'C 811io 6n g

►► PC12.12 q

F ► i

GMDF/189 T-3^CM^W

tXyCt9 t ^

Figure A17 (GD13081M)—Discrete and relay latch logic diaRam.

i

63

WeSTORPI^ROC a

a E5

FS'(Nc0 eEG

p#, tip'.

PREVT: ING PAGE BLANK NOT FILMEr,

Il4LCLOK •DS

108014 • 1as FRAME SYNC INTERRUPT TO GIMBAL INTERRUPT

DADFW

' o^ oclR

OCIEN ^ • wi0BD1

IMYCLOK •

D15

it oDCZR

6NOOIJ^

MEN ^ eD6

181'114I.SO,ustc

DCIEN 0I E4 1

PC91 ^ Ca I CIADPN_ I G7 a

mgmCMDP'N

IKBXN

OCIE"8

DUM

8D4

GN

MQCLOKCMD TRANSFER CONTROL

PCDI 1 4, 1 -4: ---t: 1 1 1CMDPN `--l.,t---

im ^' ^rtt^.lutnsDCIR 1 1 1 1 1!w if

DCIEN ^I 1_ I I I J1i I I^^____

ME SSNi--j—-^s--

i KBXil ^JZJZ►^,^_

LA i T -0-- 6 0 - - r -

042 CLOK

MER

DCUM I 1 I I I I I

S DATA

F5YNC (—^

Figure A181GD1308689►—Logic diagran of Interrupts 4 and 8, and

EOMOUT, FRAME OCDOUT FF

a^E7

8EG

NOT FILMET,

IDS

0As

FRAME SYNC INTERRUPT

10 GIMBAL INTERRUPT

wm

OCIEN E±

PCflI A CMD;"

1 , E3

wtCMD"

i KBXN

DCIEN ► ag D4

GND D480

M42CLOK

CMD TRANSFER CONTROL

K9 1

I ! r—^CMDPN ..^ ^-

--- c^ ^rtr^4,.rtrLrl.rL—tsDCI R ^;.1--^ ^1 1 1 1 ^y 1 1

DCIEN —i ;I 1 I I i -y; 1 I-- I —^r

ME SSN

^7

I K

KOXN

I ^- Rte• a' -4

Fipurt A181C,D13ONW—Looic diagram of Intm. ptf 4 and B, and controls for cummand timWo,

WOMOUT FP,AMr65

cmmp :I ^ L I f ai ^, Gfi I_ II cis904

cR

cm

cm

.- --ft,t:4,4' ^.

I

PRrrMTNr, PArr PT,ANTR NOT M, R,trT

LDSYNC2

CTS ► ► !9

^^; LRDC

OBES t

CneA a s LDOMPAADIompsm !

LOOMPAAtXCCALEMc

C►IKEL rom c

IOBDQ

ENLDOMPOADt 5MV,

NFM ! tDl/►MCTAtA

OMPSTlY o— P-13 ^COSS& DCAR

!

ampo tCTW^ 9

omit ^ CCOLEK,T8mfbb3ii'

M!%

4 S P CMDR875= IOMPM

NI]

CI OMN CL

FOLDOUT. FRAME

i

IKONTU7

9G12

LDSYNCI

LDSYNC2

CONT6tPU

OMPBT32 o., !CT63 O—;

12 I1 1 DMPWD65 II'. i PAREN

3 64 3 G3 9 ^^1

N3Ca9b DMPWD65 2 ! PAREN

DCONTt6 DCOW3

9

9G6

GS

MAWT

^l

CMDDMPCL

9 CNNIS

MunmM)M

WDB14DST

1

VT3?_

i BT329 j1 9 9

a DMPBT32

D" H9

_t^

vClltipq 1 9

MOM 3 He 9

CNBSEL GND RMCM

M 2 EUr CTS 1 M ^8T32

CM S EtS i CT62A 8141 EI2 i

BT43

CM 1t E^ " CTQ3

MR z ^ CrG29

Figure A191GD1308600)—Logic diagram of dump register load and output controls.

67EOLDOUT FRAME

WEND(rO 103

144

CKTV

wM

Tu'i

CHASEL C,, 1

CfD 2 9

DON^AMSJ12

Pa1REN10

CMD P1^/i 12 9DMPMLS / J12

CNBSEL

INC, bl AAN& NUI 141,J.

►

(TO STD 1/0)

CCAACK

VN*—Mft^—D—AM

A

CMt*L E tm

---^ (TO m 1/0)

>^L

CCBACK

1

12 N XTRAWRD

PNJ9

;L

CM^1 t^ a Efi .. t

WWL

Pw3w

19

9 u 9 DMPBLAE9^^ 2 ISJ 1 ,

JIS BLAE1•

pBl0

BIBES 5 115 BLEiES j 5 09 93 DMMBEBI

1 D

0-PMPRQC

AWEL

Foi^ovr Faan^ri

(TO STD 1/0)

CCAACK

VYWO

9

^9 aJq

F MIN

►-0 (TO SM 1/0)

DUMP!

9J7

IDMPM►

9u9 6 CMDDMBLC 13 XCMDDCLR

9 PMPFOC 9

J& CMDDM J5

Figure A20 (GD1308598)–Logic diagram of command dump extra-word control.

W-DOUT FRAME

.Z

NWL

69

i g

PRECELING PAGE BLANK NOT FILL E--

m

of u u CCBA4 CLAM CCBAS CCAAS CCBAA CCAA& CCBA7 CCAA7 CCBA6 CtAA CCBA9 CtAAf CtBAp CtAA

DMPRII OMPRe9 DMPRY7 WPM DMPR2

A 5 A14- -

AK s Mal AIM 0 A9 Ad

rwomR - - - -

IOS

DIIOBDZ IpB3 I0W4

QpI0WS 10806 LOW7 lows

DCOEN I

Q1 1 I I I i I

I08pD91

YDMPR175T OkWM83T Dmpffi73T DMPRIWr IS pM ^R135T MIN 11 11 11 II N 11

DMPRIS DMPRIO OMPR17 DMPR14 DMPR16 DMPR14 DMPM2 DMPR12 O

a u C4 cs CG C7 cs C9 CIO

1 1 M S

4 4 4 4 4 4 4 4 4

^l

IOBD14 IOBD15 IOBWi I08D17 I08D18

DCWN

0 i^^LDSYNC2l0 1 t 4 12

FOLDOUT FRAME

I

CUm

CCUAAS CCAA

I 1

i

eAll

10805 IOBD6

C7

if

DMPM OMPR2 DMPR24 DMPR DMPR DOW

8 8 d 8 d 8 aAla • A9 Ad A7 AG A5 A4 9

DIA OMPRFI

4

10BD7 10808 10809 108DM 108DI1 101302 MOM$

1 9 10 1 12 19 1!

60 8 DOo D7 DI I ID 0 t II

II d S d 2 c II 9

^^ 3ST Ut ST HT DWRM11 M If II (1 11

DMPR13 DMPRIE DMPRII DMPRIS DMPR9 DMPRO DMPR7

CIS 9 0114 D mCe ' C9 CIO G 1 Cl e 9

4 4 4 41 4

idlE10

Figure A21 (GD1308595)—Dump shift register logic diagram.

FOLDOUT FRP ME71

PRLCIMING PAGE BLANK NOT FILML:-

DMPSYNC_j--, 1 i r

ST32

DMPM -- -^

6LNDu

LOSYNC2n t1

lzDMPSHPTP

n n._ n n I1 nDM WRD65

DMPBT32

CONT64 P

CLRDMPR^f

LDOMPAADI rt

DCOR

DMEN ^n

PAREN

PARITY BTL---!

L- _- J

ft)CWLIT, FRAME

-- — io-1L-----tom--n

n r,

r r A

- - - - ---f 1 f ^

^_^ '^

L---J L--- J l-- ^J

Figure A22 (GD13086601—Dump control timing diagram.

t- 15

z 73

PAGE BLANK NOT FILMED

PH PRO t^^^

IDMPM J-1

CMDDMPM

CHBSEL ^-

CCBACK

C CBRAK F-1BLBE9^1

.y

DMPBLBEIR nMME

DUMPI -----

LDDMPBAI

DCOR

XWRDBFIN ^--,

CMDDMBCL r--^

CMDCL

CMDBL r----1

C DN DOMPCL

F figure

b=U31 FRAME

n s

r--- ;

T (-1_ F

F--Iit fi

Figure A23(GI)IM6681-tommand dump control timing diagram.

IftE MOUT FRAN.75

*1 r ^^^^ $ "C" FILMED

APPENDIX B

FORMATS

COMMAND FORMATS

The two experiment command channel- requested by the OBP are used to load OAOexperiment commands into the OBP memory; to control the operation of the computer, andto send cods and data to the computer. The command formats used by the ACMU onOAO 2 are used on OAO C for auxiliary command storage. The only variation betweenformats for the OAO 2 ACMU load and an OAO C OBP auxiliary command load is that onOAO 2, bits 23 through 28 are "don't care" bits in the experiment internal command wordfor ACMU commands, and on OAO C. these hits must become octal 40.

The OBP has been assigned experiment command channels 1 and 2 for the OAO Cflight. Table B1 presents all command formats, and Table B2 shows the formats of codewords used by the operational program. Experiment command channel 2 is used only tohold the second half of an auxiliary command to be stored. This line cannot be used for

= other functions, because the second half of an auxiliary command uses all 30 bits. Bit 31 must always equal one for experiment command channel 1 because it is used for registration

purposes. Bit 32 of experiment commands received on channel 1 is used to distinguishbetween the first half of an auxiliary command and all other OBP commands. A zero in bit32 indicates that bits 4 through 31 on experiment command channel I are the 28 bits of thefirst half of an auxiliary command. As seen in Table B 1, if bits 3 and 32 on experimentcommand channel I are both ones, bits 23 through 28 become a 6-bit function code thatis decoded by the I/O unit. Depending on the function code, the 18-bit word in positions5 through 22 is either used by the 1/0 unit or the CPU, or ignored.

The first two OBP commands listed on Table B 1 have 1/0 function codes of 01 and 02.This command pair, issued consecutively in that order, results in initiation of a CSC in the1/0 unit for a block data transfer with memory. The first command with an octal 01 for an1/0 function code contains a device number (0 through 3), a CSC (A or B), and a blocklength (0 through 4096) in the 18-bit field. The next command (octal 02) contains a 14-bitstarting address. The control for this block transfer is commanded from one of two redundantCSC's in the 1/0 unit. In the true sense, cycle-steal redundancy exists because the assignmentof the CSC is independent of data source/receiver. To load new programs or data from aground station, an 01 /02 command pair must be sent on experiment command channel Ifollowed by the new data to be stored. The new data are in the form of one OBP word per =_experiment command 1 with an octal 30 function code. Thus, to load the numbers 0, 1, 2,

77

and 3 into OBP memory locations 10, 11, 12, and 13 (octal) would require the followingcommand sequence:

34567891011 12 13 14 15 16 17 18 19 20 21 222324252627282930'; 32

1X00000 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 X X X 1

1X00000 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 X X X 1

1X00000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 X X X 1

1X00000 010 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 X X X 1

1X00000 0 0 0 0 0 0 0 0 0 010 1 0 0 1 1 0 0 0 X X X 1

1X00000 0 0 0 0 0 0 0 0 0 010 1 1 0 1 1 0 0 0 X X X 1

The function code 04 in bits 23 through 28 of an experiment command I selects thebank of memory in which "fixed locations" used for I/O and interrupts are to be stored.Since this function can be reassigned to another memory bank, it provides for continuedoperation even if the memory bank containing "fixed locations" w-re to fail. Bank 0 nor-mally contains the "fixed location" information, but this could be transfentd ;- ► anotherbank; of course, some program change and reload would then be required. Function code07 is a master clear that resets both the I/O unit and the CPU. Function codes 10 throia;h13 cause a memory dump of banks 0 through 3 to the wideband transmitter through CSCA,and codes 14 through 17 cause a dump of banks 0 through 3 through CSCB. Function code20 causes interrupt I to occur. This interrupt is used to initiate certain data locations, clearoff all interrupts, and pass control to the executive program; it can be commanded after anew program is loaded and occurs automatically after recovery from under voltage on board.Function code 40 initiates an interrupt 3 request. This interrupt program executes an inputinstruction to bring in bits 5 through 22 of the command I and takes appropriate action afterdeciphering bits 5 through 9 of the input word. Codes that have been defined are given inTable B2. Note that bits 5 through 9 are also ACMU internal command bits on OAO 2 sothat one "appropriate action" might be to respond to an ACMU command. Command ty ?e40's can also be used to initiate block transfers under software control rather than initiatingthe CSC with command types 01 and 02.

Memory dumps can also be initiated under program control by using a command type40. It is seen that other functions can be defined for type-40 commands since these com-mands result in an interrupt request with a 5-bit code and 13-bit program words available foruse by the operational program in the OBP.

Dump Format -!k

Upon command, the OBP dumps a selected bank of memory twice to the widebandtransmitter. The serial bit rate of the dump is 50 kHz, and the data are converted to split- 4phase prior to transmission. A dump transmission requires approximately 5.32 s, since abank is dumped twice and the format is 32 bits per word, 65 words per frame, 64 frames perdump. Each 32-bit word is formatted as follows:

78

1 2 19 20 31 32

1 18-bit OBP word MSB 112 MSB's of memory address MSB I P

It should be noted that a full address word is 14 bits; hence, the 12 most significant addressbits increment by 1 every four words. Bits 20 and 21 can be used to determine which mem-ory bmik is being dumped. Bit 19 of the dump word corresponds to bit 1 of an OBP memoryword, and bit 2 of the dump word holds bit 18 of the word readout of OBP memory. Thisarrangement differs from the manner in which the 18 bits are formatted for ail ACMU dumpon OAO 2: To conserve hardware, the 18-bit word is split into a 3-bit and a 15-bit field onACMU.

Table Bl—Command code formats.

Note , I

Note 2

03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Experiment Command 28-bit first half of command to be storedChannel I

Note 1 Experiment CommandChannel 2 30-bit second halt of command to be stored

Experiment Command 1 X 18-bit word 110 FN codeChannel I

1/0 FN code

Function IFN) use of 18-bit word (octal)

DF"

Set block, length, channel and 1 X X X C X V MSB block length LSD 01 X X X Idevice for block transfer H 1CE

Set starting address 1 X X X X X MSB starting address LSD 02 X X X 1for block transfer

W DH

Set "fixed location" bank 1 X X X X X I N M X X X 1C KH

Dump memory bank 0. Ch A I X

used

10 X X X 1

Dump memory bank 1. Ch A 1 X 11 X X X 1

Dump memory bank 2. Ch A I X 12 X X X 1

Dump memory bank 3, Ch A 1 X 13 X X X 1

Dump memory bank 0. Ch 8 1 X 14 X X X 1

Dump memory bank I, Ch 8 1 X is X X X 1

Dump memory bank 2. Ch 8 1 X 16 X X X 1

Dump memory bank 3. Ch D I X 17 X X X i

Interrupt I I:mtiatel 1 x 20 X X X 1

Data request 1 X 18-bit data word to be 30 X X X 1stored in OOP memory

Imerrup , 3 (code words 1 X 5-bit code 13-bit program word 40 X X X 1

Note 1 Thew two commands must be issued consecutively in the order shown.Note_ See Table A_ for code formats.

79

Table B2—Program code formats.

03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Experiment CommandChannel I

Function (FN) 1 X 5-bit code 13-bit program word 110 FN code X X X 1

Clear Page to 0's 1 X 0 0 0 0 0 Page

Page

Page

Page

PageNot

UsedPage

1 0 0 0 0 0

1 0 0 0 0 0

X X X 1

X X X 1

Set Page to 1's 1 X 0 0 0 0 1

Initiate Page, erase 1 X 0 0 0 1 0

Initiate Page, no erase 1 X 0 0 1 0 0

Initiate Page, set RT mode 1 X 1 1 0 1 0

Transfer Page to PPDS 1 X 1 0 0 0 0

Set relay latch 1 1 X 1 0 0 0 0

Set relay latch 2 1 X 1 0 0 1 0

Set relay latch 3 1 X 1 0 1 0 0

Note: Above functions are related to auxiliary command memory.

Dump bank to wideband 1 X 1 1 0 0 0 Bank No! used 1 0 0 0 0 0 X X X 1

Initiate CSC and set up1 X 0 1 0 0 0 XF Block length LSB 1 0 0 0 0 0 X X X 1

1-word buffer for SA

FN code to programs 1 X 0 1 0 1 1 13-bit code to executive 1 0 0 0 0 0 X X X 1

t

S

80

APPENDIX C

DETAILED DESCRIPTION OF CENTRAL PROCESSOR UNIT

The CPU block diagram shown in Figure C1 illustrates the information flow throughthe various registers and logic units.

The abbreviations used in the logic flow charts and the number of bits contained ineach register are noted within each box, the number of bits appearing in parentheses. Blockscontaining no abbreviation or bit count are considered logic units. Lines with double arrowsindicate that information can flow in either direction between two registers. Heavy linesindicate a bus.

In general, data transfer is parallel. The major exception to this rule is the Accumulator(A) and the Extended Accumulator (EA), where several complex two-way serial data pathsexist as required by the instruction set.

DESCRIPTION OF REGISTERS

Accumulator

The Accumulator, an 18-bit register, contains one operand for all arithmetic, shifting,input/output, and logic functions and is used to retain the results of all arithmetic, shifting,and logic functions

Address Register

The Address Register (ADR) is an 18-bit register used to hold the memory address in-formation for all CPU memory cycles. Although only 14 bits are required for addressing theOBP-2 16K memory, the register is full size in order to allow basic system expansion to 64Kor more and also because it is used to hold the 18-bit divisor during the divide instruction.

Extended Accumulator

• The EA is an 18-bit register that provides the required storage in the multiply anddivide operations. The remainder is stored in the EA after a divide. After a multiply, thelow half of the product is stored in the EA. In addition to these functions, the Accumulatorwith the EA can be normalized and shifted both cyclically and algebraically by means of theappropriate instructions.

81

Subscript Register

The 18-bit Subscript Register (SS) can be loaded, stored, added to, incremented, andtested by the SS instruction. It is used by subscripted (index) instructions to modify theoperand address by adding in the value contained in this register during the formation of aneffective operand address (see "Instruction Execution"). Its ready accessibility makes itavailable for general use.

Scale Register

The 6-bit Scale Register (SCALE) can be loaded and stored by program control. Itsfunction is to denote the position of the binary point associated with a data word. Thisregister makes normalized fractional arithmetic possible by using a setting of zero, and in-teger arithmetic possible by using a setting of 17. Other settings between — 32 and +31 allowa wide, dynamic range for binary point placement.

Storage Limit

The 18-bit Storage Limit Register (SLR) is divided into two fields of nine bits each. Itspurpose is to permit storage in memory only within the range specified for the program.This register can be modified only from the interrupt cells located at the beginning of memory.

Page Register

The 4-bit Page Register (PAGE) is appended to the address field of all instructions and N"

determines in which bank of 4096 words the address field is located. If indexing is used, itcan modify the effective address to the point of changing the addressed bank.

Instruction Register

The 11-bit Instruction Register (IRS) is used to store the operation code and the sub-script bit of the instruction. The output of this register is decoded to determine the instruc-tion type and remains unchanged throughout the execution of that instruction.

Carry Register

The Canty Register (C) is a 1-bit register that is changed by operations such as addition,subtraction, and negation. The setting condition is a carry out of the 17th bit of the two'scomplement adder. If the setting condition is not met, a zero is placed in the Carry Register.

Overflow Register

The 1-bit Overflow Register (OV) is set by arithmetic and shifting instructions if over-flow has occurred. (Overflow is defined as the loss of a significant bit out of the 17th bit ofthe Accumulator.) This register is reset only by testing or by the instruction to reset it.

82

Instruction Counter

The 16-bit Instruction Counter (IC) contains the memory address of the instructionunder execution and performs the updating of this address during all nonbranching instruc-tions. The IC is loaded with the 16 low-order bits from storage upon execution of a branchinstruction or an interrupt.

Memory Operand Register

The 18-bit Memory Operand Register (MOR) is the memory data bus interface registerfor the processor. It provides all data to and receives all data from the memory. In additionto these functions, the MOR holds one operand for the processor in all arithmetic and logicoperations.

Or/And Register

The 1-bit Or/And Register (OA) is cleared or set by the OR and AND instructions,respectively, and is used to determine the setting of the Decision Register (D) when one ormore subsequent test conditions are specified. If the OA is a one, an AND condition isspecified; therefore, both "prior test true" (D = 1) and "present test true" are required toset D. If the OA is a zero, an OR is specified; therefore, ""prior test true" or "present testtrue" will set D. At the conclusion of the conditional transfer, or upon the execution ofan OR instruction, the OA is reset to zero. The execution of an AND instruction will set theOA to one.

Decision Register

The 1-bit Decision Register (D) is set by the test instructions if the proper conditionsas mentioned above are met. If D is a one, the conditional transfer instruction will performthe branch, and D will be set to zero. A "reset D instruction" is also included.

Operation Counter

The 6-bit Operation Counter is required for the multiply, divide, and shift type ofinstructions. The counter may count either up or down and contains a value equal either tothe shift length for a shift instruction or to the Scale Register for the multiply or divideinstruction.

INSTRUCTION EXECUTION

Instructions are stored along with data in the memory of the OBP. The InstructionCounter contains the address of the instruction to be executed. The instruction is fetchedfrom storage into the Instruction Register. The five high-order bits (bits 14 to 18) are usedto determine the major operation code. A major OP CODE of zero is a nonmemory accessinstruction, and the operation to be performed is determined by the minor OP CODE

83

located in bits 1 to 5, as illustrated in Figure C2. While performing the instruction decode,the Instruction Counter is increased by one in order to point to the next instruction to beexecuted.

All other major OP CODE's result in a memory access because they require that anoperand :)e fetched. The 16-bit memory address is formed as shown in Figure C3. To estab-lish an effective address, the content of the Page Register is appended to bits 1 through 12of the instruction.

If subscripting is indicated (i.e., if bit 13 of the instruction is a one), the content of theSubscript Register is added to form the effective address. Once the effective address is com-puted, the operation indicated by the content of bits 14 to 18 is performed. Depending onthe operation, the Instruction Counter is either increased by one or replaced by the contentof the memory word pointed to by the effective address.

Upon completing the execution of one instruction, the processor automatically pro-ceeds to the next. A description of all basic machine operations is presented in the nextsection.

MACHINE VERBS

The following list of machine operations presents a simple description of the executionfor each instruction. The English name for the operation is a so-called verb to reflect theEnglish-like language originally planned to be used to program the OBP; however, in view ofthe fact that these are really machine operations, a corresponding set of three-lettermnemonics has also been assigned. The memory access operations are denoted by nounfollowing the operation name. This indicates that the programmer must specify the nameof an operand for this verb. This name can be any word or group of words except a legiti-mate OBP-1 verb, e.g., OP CODE.

The instruction format and octal representation are shown in the box to the right ofthe programming language specification. The bit pattern of instruction words is shown inFigure C2. The second instruction format, if given, is the octal representation that is pro-duced when the configuration (verb) SUBSCRIPTED (noun) is used in the programminglanguage. The use of subscripting requires 4.00 µs more than the indicated execution timeof the instruction.

Load and Store Instructions

LET noun, IF noun 2 0 n o u n

LET SUBSCRIPTED noun, IF SUBSCRIPTED noun 2 1 in o u n

The content of storage at the effective address is placed in the Accumulator.

Registers altered: Accumulator

Timing: 10.0 µs, 14.0 µs if subscripted

`,.

84

LET LOCATION OF noun 4 0 n oLET LOCATION OF SUBSCRIPTED noun 4 1 n o u In

The effective address is placed in the Accumulator.

Registers altered: Accumulator

Timing: 8.0µs; 12.0 µs if subscripted

YIELD noun, REPLACE noun 6 0 n o u nYIELD SUBSCRIPTED noun, REPLACE SUBSCRIPTED noun 6 1 n o u n

The content of the Accumulator is stored at the effective address unless that address isprotected by the Storage Limit Registers. If storage is protected, no write into mem-ory occurs.

Registers altered: none

Timing: 12.0 µs, 16.0 µs if subscripted

SET EXTENSION WITH noun 15 21 n o unSET EXTENSION WITH SUBSCRIPTED noun 5 31n o u n

The content of storage at the effective address is placed in the Extended Accumulator.

Registers altered: Extended Accumulator;

Timing: 10.0 µs, 14.0 µs if subscripted

SA VE EXTENSION IN noun 11 01n o u nSA VE EXTENSION IN SUBSCRIPTED noun 11 1 n o u n

The content of the Extended Accumulator is stored at the effective address unless thatt address is protected by the Storage Limit Registers. If storage is protected, no write

into memory occurs.

Registers altered: none

Timing: 12.0 µs, 16.0 µs if subscripted

Arithmetic Instructions

PLUS noun 1 0 4 n o u nPLUS SUBSCRIPTED noun 0 5 In o u n

' The content of storage at the effective address is added to the content of the Accumu-lator, and the sum is retained in the Accumulator. If a carry occurs at the input of the18th stage of the two's complement adder, the Carry Register is set to one. Otherwise,the Carry Register is reset to zero. Overflow can occur when two numbers of the samesign are added. Overflow causes the 18th bit of the sum to remain in the sign positionand the Overflow Register to be set to one.

85

Registers altered: Accumulator T

Carry RegisterOverflow Register (conditionally)

Timing: 12.0µs, 14.0µs if subscripted

MINUS noun 2 4 n o u n

MINUS SUBSCRIPTED noun 25 n o u n

The content of storage at the effective address is subtracted from the content of theAccumulator, and the difference is retained in the Accumulator. Subtraction is per-formed by using the one's complement of the content of storage and adding it to theAccumulator with a carry forced into the low-order stage of the adder. If a carry occursat the input of the 18th stage of the two's complement adder, the Carry Register is setto one. Otherwise, the Carry Register is reset to zero. Overflow can occur when twonumbers of different sign are subtracted. Overflow causes the 18th bit of the differenceto remain in the sign position and the Overflow Register to be set to one.

Registers altered: AccumulatorCarry RegisterOverflow Register (conditionally)

Timing: 10.0µs, 14.0 ,us if subscripted

TIMES noun 4 41n o u n

TIMES SUBSCRIPTED noun 4 51n o u n

V

The content of storage at the effective address is multiplied by the content of the Accu-mulator. The high-order 17 bits and sign of the product are retained in the Accumula-tor. The low-order 17 bits and sign of the product are retained in the ExtendedAccumulator. The double-length product is automatically scaled by arithmeticallyshifting the Accumulator and the 17 bits of the product in the Extended Accumulatorthe number of bit positions indicated by the content of the Scale Register. The signbit of the Extended Accumulator is not shifted. If the content of the Scale Register isnegative, the shift is right and the content of the sign fills positions vacated on the leftso that no overflow is possible. If the content of the Scale Register is positive, the shiftis to the left, with zeros filling positions vacated on the right. The Overflow Register isset to one if the sign bit of the Accumulator is changed during the shift.

Registers altered: AccumulatorExtended AccumulatorOverflow Register (conditionally)

Timing: If the content of the Scale Register is less than 17, 37.5 ps + (number of onesin the multiplier + Iscale I) X 1.5 µs; if the content of the Scale Register isequal to or greater than 17, 37.5 µs + (number of ones in the multiplier +scale — 15) X 1.5 µs. Additional 3.0 ps if subscripted.

86

OVER noun, DIVIDED BY noun 6 4 n o_u nOVER SUBSCRIPTED noun, DIVIDED BY SUBSCRIPTED noun 6 5 n o u n

The contents of the Accumulator and Extended Accumulator are automatically scaledby shifting them the number of bit positions indicated by the content of the ScaleRegister. The sign of the Extended Accumulator is ignored and not shifted. If the cor.-tent of the Scale Register is negative, the shift is to the left, with zeros filling positionsvacated on the right, and if the sign bit of the Accumulator is changed during the shift,the Overflow Register is set to one. If the content of the Scale Register is positive, theshift is to the right, and the content of the sign fibs positions vacated on the left so thatoverflow is impossible. The scaled Accumulator and Extended Accumulator form thedividend that is divided by the content of storage at the effective i ddress. The Over-flow Register is set if the content of the Accumulator is greater than or equal to thecontent of storage. The signed quotient is retained in the Accumulator, and the signedremainder is retained in the Extended Accumulator. The remainder has the same signas the dividend and has a magnitude less than the divisor.

Registers altered: AccumulatorExtended AccumulatorOverflow Register (conditionally)

Timing: If the content of the Scale Register is less than 17, 105.0 As + I scale I X 1.5 µs;if the content of the Scale Register is equal to or greater than 17, 105.0 As+ (scale — 15) X 1.5 µs; in either case, add 9.0 As if dividend is less than zero.Additional 3.0 As if subscripted.

PLUS CARRY

0 010 0 0 6

The content of the Carry Register is added to the content of the Accumulator, and thesum is retained in the Accumulator. If a carry occurs at the input of the 18th bit ofthe two's complement adder, the Carry Register is set to one. Otherwise, the CarryRegister is reset to zero. Overflow can occur and will cause the 18th bit of the sum toremain in the sign position and the Overflow Register to be set to one.

Registers altered: AccumulatorCarry RegisterOverflow Register (conditionally)

Timing: 6.0 As

NEGATED

0 010 0104]

The content of the Accumulator is replaced by its two's complement. Negating allzeros yields a result of zero and sets the Carry Register to one. Negating the numberthat has zeros in all bit positions except the sign yields the same number as a result andsets both the Carry Register and the Overflow Register to one. Other than these twospecial cases, the Carry Register is reset to zero.

N-

87

Registers altered: AccumulatorCanty RegisterOverflow Register (conditionally)

Timing: 6.0µs

Logic Instructions

ANDED WITH noun 3 01n o u nANDED WITH SUBSCRIPTED noun 3 1 n o u n

The content of storage at the effective address is anded with the content of the Accu-mulator. The result is retained in the Accumulator. The 18 bits of the result are com-puted independently, with a one occurring in a bit position of the result only if theAccumulator and storage both contained a one in that bit position.

Registers altered: Accumulator

Timing: 7.5 µs, 10.5 ps if subscripted

OR-ED WITH noun 5 01n o u nOR-ED WITH SUBSCRIPTED noun 5 1 In o u n

The content of storage at the effective address is or-gated with the content of theAccumulator. The result is retained in the Accumulator. The 18 bits of the result arecomputed independently, with a one occurring in a bit position of the result if eitherthe Accumulator or storage contained a one in that bit position.

Registers altered: Accumulator

Timing: 7.5 µs, 10.5 µs if subscripted

FOR-ED WITH noun (EXCL USI 3EL Y OR-ED WITH noun) 7 01n o u nFOR-ED WITH SUBSCRIPTED noun (EXCLUSIVELY OR ED 7 1 In o u n

WITH SUBSCRIPTED noun)

The content of storage at the effective address is exclusively or-gated with the contentof the Accumulator. The result is retained in the Accumulator. The 18 bits of the re-sult are computed independently, with a one occurring in a bit position of the result ifeither the Accumulator or storage, but not botti, contained a one in that bit position.

Registers altered: Accumulator

Timing: 7.5 µs, 10.5 µs if subscripted

COMPLEMENTED 10 010 0 1 0

The content of the Accumulator is complemented, and the result is retained in theAccumulator. The 18 bits of the result are computed independently, with a one occur-ring in a bit position of the result only if the Accumulator contained a zero in that position.

88

Registers altered: Accumulator

Timing: 6.0 As

Bit Manipulation Instructions

SHIFTED BY noun 11 41 n o u InSHIFTED BY SUBSCRIPTED noun 1 51n o u

The 6 low-order bits of the content of storage at the effective address are used as atwo's complement shift count. If the count is negative, the Accumulator is shifted tothe right the number of positions specified by the count, with the content of the Accu-mulator sign replacing vacated positions on the left. If the count is positive, the Accu-mulator is shifted to the left the number of positions specified by the count, with zerosfilling vacated positions on the right. The Overflow Register is set to one if the sign bitof the Accumulator is changed during the shift.

Registers altered: AccumulatorOverflow Register (conditionally)

Timing: 7.5 As + 1.5 As per position shifted; if subscripted, 10.5 As + 1.5 As perposition shifted

DOUBLE SHIFTED BY noun 1 3 6 In o u InDOUBLE SHIFTED BY SUBSCRIPTED noun 3 7 n o u

The 6 low-order bits of the content of storage at the effective address are used as atwo's complement shift count. The Accumulator and the Extended Accumulator areshifted together. The Extended Accumulator is shifted to the right of the Accumula-tor, and its sign bit is not shifted. If the count is negative, the accumulators a. „ shiftedto the right the number of positions specified by the count, with the content of theAccumulator sign replacing vacat.-; positions on the left. If the count is positive, theaccumulators are shifted to the left the number of positions specified by the count,with zeros filling vacated positions on the right. The Overflow Register is set to one ifthe sign bit of the Accumulator is changed during the shift.

Registers altered: AccumulatorOverflow Register (conditionally)

Timing: 7.5µs + 1.5 As per position shifted; if subscripted, 10.5 As + 1.5 As perposition shifted

CYCLED BY noun

34nounCYCLED BY SUBSCRIPTED noun

3 Sin oun

The 6 low-order bits of the content of storage at the effective address are used as atwo's complement shift count. If the count is negative, the content of the Accumula-tor is shifted cyclically to the right the number of positions specified by the count,

89

with bits leaving the low-order position entering the sign position. If the count ispositive, the content of the Accumulator is shifted to the left the number of positionsspecified by the count, with bits leaving the sign position entering the low-orderposition.

Timing: 7.5 ps + 1.5 ps per position shifted; if subscripted, 10.5 µs + 1.5 ps perposition shifted

DOUBLE CYCLED BY noun

5 61 a o u nDOUBLE CYCLED BY SUBSCRIPTED noun

57noun

The 6 low-order bits of the content of storage at the effective address are used as atwo's complement shift count. If the count is negative, the content of the Accumulatorand Extended Accumulator is shifted cyclically to the right the number of positionsspecified by the count, with bits leaving the low-order position of the Extended Accu-mulator entering the sign of the Accumulator and bits leaving the low-order positionof the Accumulator entering the si- : of the Extended Accumulator. If the count ispositive, the content of the Accumulator and Extended Accumulator is shifted to theleft the number of positions specified by the count, with bits leaving the sign of theExtended Accumulator entering the low-order position of the Accumulator and bitsleaving the sign position of the Accumulator entering the low-order position of CieExtended Accumulator.

Registers altered: AccumulatorExtended Accumulator

Tuning: 7.5 µs + 1.5 ps per position shifted; if subscripted, 10.5 ps + 1.5 ps perposition shifted

NORMALIZED

0 010 011 4

The content of the Accumulator and Extended Accumulator i shifted to the left untilthe 17th and 18th bits of the Accumulator are different. The sign bit of the ExtendedAccumulator is not shifted. Bits leaving the 17th bit of the Extended Accumulatorenter the low-order position of the Accumulator. Zeros fill the positions vacated onthe right. A count of the number of positions shifted is retained as a 6-bit positivemunber in the Scale Register. If the content of the Accumulator and positions Ithrough 17 of the Extended Accumulator are ze-ro, the Sale Register is set to zero.

Registers altered: AccumulatorExtended AccumulatorSale Register

Timing: 6.0 ps + 1.5 ps per position shifted, or 31.5 ps if Accumulator and ExtendedAccumulator are both zero.

90

CLOSE EXTENSION WITH DECISION 10 0 0 0 1 3

The content of the Accumulator and Extended Accumulator is shifted left one position.The sign of the Extended Accumulator is not shifted, and the vacated, low-order posi-tion of the Extended Accumulatu: is filled with the content of the Decision Register.The Overflow Register is not altered.

Registers altered: AccumulatorExtended Accumulator

Tuning: 4.5 ps

REVERSE BITS OF THE ACCUMULATOR 10 010 0 2 2

The contents of the Accumulator are reversed in order. The (19 — n)th and nth bits areexchanges (for n = 1, 9).

Registers altered: Accumulator

Timing: 4.5 ps

Subscript Instructions

USE SUBSCRIPT noun 5 4 n o u nUSE SUBSCRIPT SUBSCRIPTED noun 1 5 51n o u n

The content of storage at the effective address is placed in the Subscript Register.

Registers altered: Subscript Register

Tuning: 6.0 µs, 9.0 ps if subscripted

SA VE SUBSCRIPT IN nounSA VE SUBSCRIPT IN SUBSCRIPT ED noun

The content of the Subscript Register is stored at the effective address unless thataddress is protected by the Storage Limit Registers. If storage is protected, no writeinto memory occurs.

Registers altered: none

Timing: 9.0 ps, 12.0 µs if subscripted

STEP SUBSCRIPT BY noun 0 21n o u nSTEP SUBSCRIPT BY SUSSCRIPTED noun 0 3 n o u n

The content of storage at the effective address is added to the content of the SubscriptRegister. T mThe I &bit result of the two's complement addition is retained in the Sub-script Register.

Registers altered: Subscript Register

7 41n o u n7 5 n o u n1

91

4

Timing: 7.5 µs, 10.5 ps if subscripted

Transfer Instructions

THEN Gtr TO noun 14 21 n o u nTHEN GO TO SUBSCRIPTED noun 14 31 n o u n

If the content of the Decision Register is zero, the next sequential instruction is exe-cuted. If the content of the Decision Register is one, the content of storage at theeffective address is placed in the Instruction Counter, and execution proceeds from theaddress specified by the Instruction Counter. The Decision Register and Or/And Regis-ter are reset to zero.

Registers altered: Decision RegisterOr/And Register

Timing: 6.0 µs, 9.0 ps if subscripted

GO TO noun, RETURN FROM noun 1 6 21n o u nGO TO SUBSCRIPTED noun, RETURN FROM SUBSCRIPTED noun 1 6 31n o u n

The content of storage at the effective address is placed in the Instruction Counter, andexecution proceeds from the address specified by the Instruction Counter.

Registers altered: none

Timing: 6.0 µs, 9.0 ps if subscripted

TRANSFORMED BY noun, PERFORM noun 1 0 61n o u InTRANSFORMED BY SUBSCRIPTED noun, PERFORM 0 7 n o u

SUBSCRIPTED noun

The content of the Instruction Counter plus one is stored at the effective address unlessthat address is protected by the Storage Limit Registers If storage is protected, nowrite into memory occurs. The content of one location greater than the effectiveaddress is placed in the Instruction Counter, and execution proceeds from the addressspecified by the Instruction Counter.

Registers altered: none

Timing: 12.0 µs, 15.0 µs if subscripted

Test Instructions

AND 1 0 0001 1

The Or/And Register is set to one.

Registers altered: Or/And Register

Timing: 4.5 As

92

OR

0 010 0 1 5

The Or/And Register is set to zero.

Registers altered: Or/And Register

Timing: 4.5 ps

IS LESS THAN noun 12 61 n o u nIS LESS THAN SUBSCRIPTED noun 12 71n o u n

If the content of the Accumulator is less than the content of storage at the effectiveaddress, the test condition is set to one. Otherwise, it is zero. The Or/And Register'sbeing zero specifies that the test condition is to be orated with the content of theDecision Register and that the result is to be retained in the Decision Register. TheOr/And Register's being one specifies that the test condition is to be and-gated with thecontent of the Decision Register and that one result is to be retained in the DecisionRegister.

Registers altered: Decision Register

Timing: 7.5 µs, 10.5 ps if subscripted

IS EQUAL TO noun 14 61n o u nIS EQUAL TO SUBSCRIPTED noun 14 71n o u n

If the content of the Accumulator is equal to the content of storage at the effectiveaddress, the test condition is set to 1. Otherwise it is zero. The Or/And Register'sbeing zero specifies that the test condition is to be or-gated with the content of theDecision Register and that the result is to be retained in the Decision Register. TheOr/And Register's being one specifies that the test condition is to be and-gated with thecontent of the Decision Register and that the result is to be retained in the DecisionRegister.

Registers altered: Decision Register

Timing: 7.5 ps, 10.5 ps if subscripted

IS GREATER THAN noun 16 6 1, n o u dnIS GREATER THAN SUBSCRIPTED noun 6 7 n o u

If the content of the Accumulator is greater than the content of storage at the effectiveaddress, the test condition is set to one. Otherwise, it is zero. The Or/And Register'sbeing zero specifies that the test condition is to be orated with the content of theDecision Register and that the result is to be retained in the Decision Register. TheOr/And Register's being one specifies that the test condition is to be and-gated with thecontent of the Decision Register and that the result is to be retained in the DecisionRegister.

93

Registers altered: Decision Register

Timing: 7.5 µs

IFOVERFLOW 1000001

If the content of the Overflow Register is one, the test condition is set to one. Other-wise, it is zero. The Overflow Register is reset to zero. The Or/And Register's beingzero specifies that the test condition is to be or-gated with the content of the DecisionRegister and that the result is to be retained in the Decision Register. The Or/AndRegister's being one specifies that the test condition is to be and-gated with the contentof the Decision Register and that the result is to be retained in the Decision Register.

Registers altered: Decision RegisterOverflow Register

Timing: 4.5 µs

IF PARITY ODD 0 010 0 0 5

If the number of ones in the 18-bit Accumulator is odd, the test condition is set to one.Otherwise, it is zero. The Or/And Register's being zero specifies that the test conditionis to be or-gated with the content of the Decision Register and that the result is to beretained in the Decision Register. The Or/And Register's being one specifies that thetest condition is to be and-gated with the content of the Decision Register and that theresult is to be retained in the Decision Register.

Registers altered: Decision Register

Timing: 31.5 In

IS POSITIVE 000003

If the sign position (bit 18) of the Accumulator contains a zero, the teat condition is-et to one. Otherwise, it is zero. The Or/And Register's being zero specifies that thetest condition is to be or-gated with the content of the Decision Register and that theresult is to be retained in the Decision Register. The Or/And Register's being one speci-fies that the test condition is to be and-gated with the content of the Decision Registerand that the result is to be retained in the Decision Register.

Registers altered: Decision Register

Timing: 4.5 µs

IS EQUAL TO ZERO 0 0 0 0 2 1

If the value of the contents of the Accumulator is equal to zero, the test condition isset to one. Otherwise, it is zero. The Or/And Register's being zero specifies that thetest condition is to be or-gated with the content of the Decision Register and that the

94

result is to be retained in the Decision Register. The Or/And Register's being onespecifies that the test condition is to be and-gated with the content of the DecisionRegister and that the result is to be retained in the Decision Register.

Registers altered: Decision Register

Timing: 4.5 µs

IF SUBSCRIPT IS NOT GREATER THAN noun 2 2 n o u nIF SUBSCRIPT IS NOT GREATER THAN SUBSCRIPTED noun 2 3 in o u n

If the content of the Subscript Register is less than or equal to the content of storageat the effective address, the test condition is set to one. Otherwise, it is zero. The Or/And Register's being zero specifies that the test condition is to be or-gated with thecontent of the Decision Register and that the result is to be retained in the DecisionRegister. The Or/And Register's being one specifies that the test condition is to beand-gated with the content of the Decision Register and that the result is to be retainedin the Decision Register.

- Registers altered: Decision Register

v. Timing: 7.5 µs, 10.5 µs if subscripted

IS FALSE 100001 7

The Decision Register is complemented.

Registers altered: Decision Register

Timing: 4.5 As

Control Instructions

PASS 1000002

No operation is performed other than the automatic incrementing of the InstructionCounter.

Registers altered: none

Timing: 4.5 As

HALT 1000000

The processor stops indefinitely. An initiate signal must be supplied from an externalsource to start the processor.

Registers altered: none

Timing: none

- 95

EXECUTE noun 1 21n o u nEXECUTE SUBSCRIPTED noun 1 31 o u n

The content of storage at the effective address is used as the address of the instructionto be executed. The Instruction Counter is incremented by one unless it is changed bythe execution of a transfer-type instruction. If the machine attempts to execute anEXECUTE noun, the program proceeds with no operation being performed.

Timing: 6.0µs

Miscellaneous Register Instructions

SET SCALE WITH noun 3 21n o u n

SET SCALE WITH SUBSCRIPTED noun 3 31n o u n

The 6 low-order bits of the content of storage at the effective address are placed in theScale Register.

Registers altered: Scale Register

Timing: 6.0 µs, 9.0 µs if subscripted

LETSCALE 1001001207

The content of the Scale Register is placed in the 6 low-order bits of the Accumulator.The 12 high-order bits of the Accumulator are set to zero.

Registers altered: Accumulator

Timing 4.5 µs

SET PAGE 10 010 011 2

The content of bits 13 through 16 of the Accumulator are placed in the Page Register.

Registers altered: Page Register

Timing: 4.5 µs

RESETOVERFLOW 1 0 00007

The content of the Overflow Register is set to zero.

Registers altered: Overflow Register

Timing: 4.5 µs

RESET DECISION 10 010 012 3

The content of the Decision Register is set to zero.

Registers altered: Decision Register

96

Timing: 4.5 µs

EXIT 0000 1 6

This instruction initiates interrupt number 16 and uses locations octal 200 through 207.Upon completion, execution proceeds normally, using the new value in the InstructionCounter.

Registers altered: Limit RegisterInterrupt Priority RegisterPage RegisterOr/And RegisterOverflow RegisterCarry RegisterDecision RegisterScale Register

Timing: 42.0 ps

RESUME FROM noun 7 21n o u nRESUME FROM SUBSCRIPTED noun 7 31n o u n

The content of storage at the effective address is used as the starting address of aninterrupt storage area. This instruction reloads the registers that were saved at theoccurrence of an interrupt. Upon completion, execution proceeds normally, using thenew value in the Instruction Counter.

Registers altered: Limit RegisterInterrupt Priority RegisterPage RegisterOr/And RegisterOverflow RegisterCarry RegisterDecision RegisterScale Register

Timing: 25.5 µs, 28.5 ps if subscripted

Input/Output Instruction

CONNECT TO noun 1 61n o u nCONNECT TO SUBSCRIPTED noun 1 71n o u n

The content of storage at the effective Address is sent to the I/O unit as a command.This word must have a zero in bits 17 and 18 to denote the establishment of a cycle-steal channel. Bits 1 through 16 specify the data channel and block length. The con-tent of the Accumulator is stored at location 7. The content of location 7 is then out-put as a starting memory address to the I/O unit.

97

Registers altered: none

Timing: 13.5 µs, 16.5 µs if subscripted

LET FUNCTION TO noun 1 6 n o u nLET FUNCTION TO SUBSCRIPTED noun 1 7 n o u n

The content of storage at the effective address is sent to the I/O unit as a command.This word must have a zero in bit 18 and a one in bit 17 to denote that bits 1 through16 are a function code.

Registers altered: none

Timing: 6.0 µs, 9.0 µs if subscripted

OUTPUT TO noun 1 6 n o u nOUTPUT TO SUBSCRIPTED noun 1 71n o u n

The content of storage at the effective address is sent to the I/O unit as a command.This word must have a one in bit 18 and a zero in bit 17. Bits 1 through 16 denote thedata channel for an output device. The content of the Accumulator, stored at location7, is then output as data to the I/O unit.

Registers altered: none

Timing: 13.5 µs, 16.5 µs if subscripted

LET INPUT FROM noun 1 6 n o u nLET INPUT FROM SUBSCRIPTED noun 1 7 n o u n

The content of storage at the effective address is sent to the I/O unit as a command.This word must have a one in bits 17 and 18. Bits 1 through 16 denote the data chan-nel for an input device. The I/O unit stores one word of data at location 7. The con-tent of location 7 is then placed in the Accumulator.

Registers altered: Accumulator

Timing: 13.5 µs, 16.5 µs if subscripted

INTERRUPT PROCESSING

Upon completion of each instruction, the processor senses if any of the 15 externalinterrupts appeared during the execution of the previous instruction (eight interrupts arepossible on the OBP). The order of hardware priority runs from interrupt I as the highestto interrupt 8 as the lowest. Hardware priority is used only to prevent conflict when two ormore interrupts allowed by priority status are waiting to be processed. The lockout statusregister in the I/O unit provides programming control of the order in which interrupts areprocessed.

98

The priority status word, as shown in Figure C4, comprises a data transfer from thememory to the I/O unit in which bits 1 through 8 correspond to the 8 interrupt levels. Theprogrammer determines the bit pattern contained in the interrupt location and thereby setsthe priority status.

When an interrupt arrives at the I/O unit on one of the 8 interrupt lines, it is comparedwith the corresponding bit position of the priority status register. If the current prioritystatus has a one in the respective bit position for that interrupt, the interrupt is temporarilylocked out and cannot get to the processor. A flip-flop in the I/O unit holds the interruptso that if at some later time the priority status is changed and a zero appears in the corre-sponding bit position of the saved interrupt, the interrupt will be honored and allowed topass on to the processor. When the processor receives the interrupt, an acknowledge signalis sent back to the I/O unit, resetting the flip-flop so that another low-priority interrupt maybe saved. Interrupts arriving at the I/O unit on a channel that is currently holding a previousinterrupt naturally will be lost. The priority status is altered when an interrupt, an EXITinstruction, or a RESUME FROM instruction is processed by the processor.

When an interrupt is honored (for example, interrupt n, as illustrated by Figure C5),the following registers are stored into and loaded from the indicated interrupt locations.

Location 8 X n (bits 1 to 16)Location 8 X (n + 1) (bits 1 to 6)Location 8 X (n + 1) (bit 7)Location 8 X (n + 1) (bit 8)Location 8 X (n + 1) (bit 9)Location 8 X (n + 1) (bit 10)Location 8 X (n + 2) (bits 13 to 16)Location 8 X (n + 2) (bits 1 to 18)Location 8 X (n + 3) (bits 1 to 16)Interrupt priority statusScale RegisterCarry RegisterOverflow RegisterOr/And RegisterDecision RegisterPage RegisterStorage Limit RegisterInstruction Counter

ounter, execution proceeds using the new value.)

Interrupt priority statusScale RegisterCarry RegisterOverflow RegisterOr/And RegisterDecision RegisterPage RegisterStorage Limit RegisterInstruction CounterLocation 8 X (n + 4) (bits 1 to 16)Location 8 X (n + 5) (bits 1 to 6)Location 8 X (n + 5) (bit 7)Location 8 X (n + 5) (bit 8)Location 8 X (n + 5) (bit 9)Location 8 X (n + 5) (bit 10)Location 8 X (n + 5) (bits 13 to 16)Location 8 X (n + 6) (bits I to 18)Location 8 X (n + 7) (bits 1 to 16)

(Upon loading of the Instruction C

When the RESUME FROM noun instruction is executed (the user is responsible fordirecting the assembler to preset noun with the value 8 X n), the following registers arerestored.

Location 8 X n (bits 1 to 16) Interrupt priority statusLocation 8 X (n + 1) (bits 1 to 6) Scale Register

99

Location 8 X (n + 1) (bit 7)Location 8 X (n + 1) (bit 8)Location 8 X (n + 1) (bit 9)Location 8 X (n + I) (bit 10)Location 8 X (n + 1) (bits 13 to 16)Location 9 X (n + 2) (bits 1 to 18)Location 8 X (n + 3) (bits 1 to 16)

Carry RegisterOverflow RegisterOr/And RegisterDecision RegisterPage RegisterStorage Limit RegisterInstruction Counter

(Upon completion, execution begins at the new value of the Instruction Counter.)

For an interrupt to function properly, the interrupt locations 8 X (n + 4), 8 X (n + 5),

8 X (n + 6), and 8 X (n + 7) must be preset to the appropriate values during the assembly ofthe user's program. Normally the Page, Decision, Or/And, Overflow, and Carry Registerswill all be zero; therefore, location 8 X (n + 5) may be preset to the desired Scale Registersetting. Location 8 X (n + 7) must contain the instruction address to which the program isto be transferred when the nth interrupt is honored.

The EXIT instruction performs exactly like an interrupt with n = 16.

STORAGE LIMIT CHECKING

The purpose of the SLR is to allow the writing of data into memory only in those areasassigned to the program. This provides storage protection which prevents a program fromwriting into any code area or from accidentally writing into someone else's data area.

The protection is dynamic in that it can be modified by the execution of either of twoprivileged instructions (reserved for the EXEC program) or by the execution of any externalinterrupt.

The SLR is divided into two 9-bit halves which represent an upper limit and lower limit,as shown in Figure C6. The nine most significant bits of the Address Register (ADR) arecompared by special logic with the corresponding upper or lower limits, and both tests in-dicated in the figure must be positive for a write to be allowed. Note that storage may becompletely turned off for a program if the lower limit is greater than the upper limit.

Since the six least significant bits of the ADR are not checked, they are "don't care"bits; hence, the smallest area of definition is 128 words. Any block size in multiples of 128words may be assigned to a program (the OBP-I 16K memory contains a total of 128 blocks).The memory may be mapped into either exclusive or overlapping data blocks in any desiredpattern. As in other areas, the CPU is fully implemented for a 64K memory size; therefore,bits 15 and 16 of the address are used for storage limit checking, although they serve noother purpose with the OBP-I 16K memory size.

The instructions that cause a memory write and which are checked for storage limitsare YIELD, TRANSFORMED BY, SAVE EXTENSION IN, and SA VE SUBSCRIPT IN.Note also that the ADR at the time of the storage limit test contains the effective address,which means that the subscript register value is included if these instructions should besubscripted.

100

If a writt is not permitted because of failure of the storage limit test, a read cycle willactually occur; however, more importantly, at the same time an external interrupt (calledOUTLIMIT) will be generated. This causes a diagnostic routine to be entered which will atleast identify the culprit (from its last IC) and possibly turn it off.

SCALING AND OVERFLOW

• Scaling

The arithmetic unit of the OBP normally regards all numbers as fractional. The ScaleRegister, however, permits the user to consider numbers as integer, fractional, or mixed,because the true value of the number contained in the Accumulator may be considered to be21(n), where s is the value of the number contained in the Scale Register and n is the frac-tional value of the number in the Accumulator. This multiplication is equivalent to a left orright shift of n by s places depending on s being positive or negative, respectively.

The Scale Register is a 6-bit register that indicates the position of the binary point ofthe number contained in the Accumulator. Negative values of the Scale Register are repre-sented in two's complement form, and the uppermost bit of this register is the sign bit.Thus, there are five bits available in the Scale Register to contain a maximum positive valueof 25 — 1 (+31) or a maximum negative value of — 25 (-32). Therefore, the Scale Registerallows the OBP to process numbers in the range of 2 -32 through 2+31 . The size of theAccumulator, however, permits only 17 bits of significance to be maintained. Numbers thathave lost all significance appear as zero.

In addition to indicating the scaling of the content of the Accumulator, the Scale Regis-ter automatically subjects the fractional product and dividend to a shift of lengths, where sis the value contained in the Scale Register. If the value of s is zero, no shift takes place,and the final result is truly fractional. This is known as the fractional mode, with the binarypoint being immediately to the right of the sign bit. A Scale Register setting of 17 is calledthe integer mode, with the binary Point being to the right of the least significant bit of theAccumulator.

PLUS, MINUS, NEGATE, and PLUS CARRY instructions are all independent of thesetting of the Scale Register. The programmer is responsible for obtaining the binary pointposition of the number in. the Accumulator as well as the operand from storage.

In Figures C7 and C8, several examples of scaling, with various values contained in theScale Register and the subsequent location of the binary point, are given for multiplicationand division, respectively. The operations of multiplication and division on A and B can bedescribed symbolically in terms of the fractional values the hardware sees (A and B) and thefixed Scale Register setting (s):

(1) Multiplication:

A • B = 21A - 2:B= 22 -10 • B) = 21C.

s

101

Thus, the fractional result obtained by the hardware isA n nC = 21 (A • B) .

This explains the double-length shift by the value of the Scale Register subsequent tomultiplication.

(2) Division

A n nn nA/B = 2sA 121B = A/B = VC.

Now, A nnC = 2—sA1B .

This explains the double-length shift by the value of the two's complement of the ScaleRegister prior to division.

Overflow and Carry

Overflow, a condition that occurs whenever there is a loss of a significant bit out of the -17th bit position of the Accumulator, is indicative of an erroneous computation due eitherto improper scaling or to too large a number being used or generated. Since all numbers areregarded as fractional during the performance of an arithmetic operation, the condition ofoverflow is equivalent to obtaining a result that is outside the permitted fractional numberrange. In general, overflow will cause the sign of the result to be incorrect. An overflowwill occur—

(1) On a PLUS or PLUS CARRY instruction only if the signs of the two numbers arealike and the magnitude of the sum is greater than 1.0 — 2-1'.

(2) On a MINUS instruction only if the signs differ and the magnitude of the differ-ence is greater than 1.0 — 2-17.

(3) On a NEGATE instruction only when bits 1 through 17 are all zero (i.e., zero, or—1.0).

(4) Multiplication of two fractional numbers produces a fractional number that is lessthan the magnitude of the larger number. Thus, overflow cannot occur during multiplicationwith the Scale Register set less than or equal to zero. An exception is multiplication of —1.0by ­ 1.0 with a Scale Register setting of zero. This results in a product of — 1.0 and an over-flow indication. Positive. Scale Register settings may cause overflow when the product isshifted.

(5) Division of a number by an equal or smaller number yields a fractional resultgreater than or equal to one, thus producing overflow. This condition can be avoided byproper shifting of the numbers involved. Negative Scale Register settings may cause overflowwhen the dividend is shifted prior to fractional division.

(6) Shifting to the right cannot cause overflow since the magnitude of the numberdecreases. However, overflow can occur on a shift or double shift to the left if the sign ofthe Accumulator is changed during the shifting process.

102

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18 .14. ... .5.. .1NONMEMORY TYPEACCESS IDENTIFIER OPERATION

MINOR OP CODE

Figure C2— Instruction word.

18 17 16 13 12 1 18 1 16 1

PAGE OPERAND t SU6SCRiPT . EADDRESSFFECTIVEI

• ADDED ONLY IF BIT 13 OF THEINSTRUCTION WORD IS SET TO ONEFigure C3—Effective address.

4 7h7 ERRUPTADDRESS LINES

i1/013 UNIT

INTERRU`LINE,

PRIORITYSTATUS

MEMORY IUNIT

Figure C4-0b,' •. pirupt block diagram.

104

CENTRALPROCESSOR

UNITCPU

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INTERRUPT LOCATIONSSR 17 16 1'S I^ 13 12 I I 10 9 8 7 6 5 4 3 2 1

0

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Figure C5—Interrupt locations.

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LR2 // \^ LR1

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Figure C6—Storage limit test.

105

OLD INTERRUPT PRIORITY

PAGE 0 C SCALE

OLD STORAGE LIMIT REGISTER

OLD INSTRUCTION COUNTER

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PAGE' DOA OV C SCALE

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106

ACCUMULATOR EXTENDED ACCUMULATOR

0 0--------------0 ---------•01000

18 A I I8 EA ISCALE REGISTER SET AT O 1010 ------------ 0 010----------- 01000 (SCALED)

(FRACTIONAL MODE i18 1 18 MOR 1•

• 0------------010018

A EA

0 0--------------010 0---------------018 (QUOTIENT) I I8 (REMAINDER) I

A EA0 o------------0 1 000 X X X X X X X

18 A 1418 EA

SCALE REGISTER SET AT 17 0 0--------------0 O 0---------01000 (SCALED)(INTEGER MODE)

18 I I8 MOR 1•

• 18 I

A EA

0-------------010 0-------------018 (QUOTIENT) 1 18 (REMAINDER) I

A EA0 000.0------------ 0 0 1 0--- -----0100000

18 A 1 1817 EA I

SCALE REGISTER SET AT+2 0io------------- 0 10 10-------- 01 000 (SCALED)18 1 18

MORI

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18 (QUOTIENT) I 18 (REMAINDER)I

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18 I 18 MOR I• -------0100• 18 I

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18 (QUOTIENT) I 18 (REMAINDER) I

Figure C8—Binary point location in division with scale register settings of 0, 17, +2, and —2.

107

PjjE0ffiMG PAGE BLANK NOT FILM

APPENDIX D

QUALIFICATION/ACCEPTANCE TEST PLAN*

This appendix outlines the environmental and functional tests performed to qualifyand accept the OBP for use in the OAO C spacecraft.

The purpose of the test is to demonstrate the structural strength and functional per-formance of the OBP in accordance with NASA Specification SO-5345-1 and revisionsthereof.

The OBP is a general-purpose, stored-program digital computer with capabilities similarto the SDS-920 or SDS-930 ground systems computers. It contains a 16 384-word, 18-bit-per-word core memory in the form of four modules of 4096 words each. The two largestmodules are the CPU and the I/O unit, with the latter containing all necessary interface hard-ware to connect the OBP to the OAO command and data handling, power, and stabilizationand control subsystems. The remaining module is the power converter, which is mountedin bay G2 separate from the rest of the system, which resides in bay G1 immediately above.Maximum weight of the OBP is 64 lb.

For radio frequency interference and thermal vacuum testing, the test specimen con-sists of seven flight boxes: Six (4 memories, the I/O unit, and the CPU) are mounted on asingle plate, bay G1 door, or equivalent; and the ---.;maining package (the power converter)is mounted on a separate panel simulating bay G2 door.

For vibration and shock testing, the test specimen consists of three independent un-powered modules (the I/O unit, the CPU, and the power converter) which will be tested asindividual "black boxes". Memories will be tested separately at the vendor according toElectronic Memories Inc. Test Plan TA920269.**

Applicable documents are—

NASA Specification SO-S345-1Electronic Memories Inc. Test Plan TA920269**OBP 2 Functional Test ProcedureEMI/RFI Test Procedure for the OBP 2

*Excerpted from "OAO C Onboard Processor Qualification/Acceptance Test Plan", an in-house document by the FlightData Storage Branch, GSFC.

**Electronic Memories Inc., 12621 Chadron Ave., Hawthorne, California.

109

TEST AND FAILURE REPORTING

Failure Rennrt

A failure report for each component failure encountered in acceptance testing shall beprepared in accordance with the OAO failure-reporting format. A failure is defined as anyreading that is not within the tolerances specified by the functional test procedure when theinputs are within limits. All failures shall be reported to the OAO Project Manager or hisrepresentative and shall be fully documented. A decision as to whether the test shall con-tinue following a failure will be made by the Cognizant Engineer and/or the OAO CognizantEnvironmental Engineer.

Failure Analysis

All failures and any erratic performance even within the specification limits will be in-vestigated, and a proposal for corrective action will be submitted to the OAO EnvironmentalCommittee for review. A failure analysis will be conducted when the failure is consideredsufficiently significant to require action. The Failure Analysis Review will be performed bythe Design Engineer, Systems Manager, Quality Control Engineer, Spacecraft Support Man-ager, and Subsystem Engineer.

TPCt Qiimmary

Within 5 working days after completion of the component acceptance, a test summarywill be prepared which will contain the following:

(1) Summary of tests performed.

(2) Description of any deviation in test procedure, together with documentation ofauthority for change.

(3) Cause of failure (if a failure occurred), results of investigations, and remedial stepstaken.

(4) Sample data sheet summarizing the major performance characteristics of the unit.

(5) List of all out-of-specification measurements requiring waiver action.

(6) Vibration plots.

Test Report

Within 30 days after completion of component testing, a test report will be preparedwhich will contain the following:

(1) Summary of results and conclusions.

(2) Description of test performed.

(3) Test conditions.

V

110

(4) List of test equipment used and calibration data.

(5) Any test peculiarities or deviations.

(6) Reduced data and graphs.

(7) Raw data sheets.

SUMMARY OF TESTS

Visual inspection will be performed after fabrication and after the OBP has been sub-jected to each environmental condition.*

A functional test will be performed on the OBP prior to commencement of environ-mental test, upon completion of vibration and shock tests, and during thermal vacuum test.

Environmental tests shall be performed on the OBP in the following sequence:

(1) Baseline functional.

(2) EMI/RFI.L_

(3) Vibration, sinusoidal.**

(4) Vibration, randcm.**

- (5) Shock." }

(6) Thermal vacuum.

TEST CONDITIONS AND EQUIPMENT

Unless otherwise specified, tests shall be conducted under the following conditions:

Temperature 74 ± 10°F (23 ±5°C)Relative humidity 75 percent or lessBarometric pressure 28 to 32 in. Hg

Electromagnetic and radio frequency interference test equipment shall include thefollowing:

(1) OAO Experimenter's Test Control Unit (ETCU).

(2) SDS-930 computer.

(3) EMI/RFI test equipment as specified in the EMI/RFI Tes t Procedure for theOBP 2.

Thermal vacuum test equipment shall include the following:

(1) ETCU.

*Bolt to-r; .es to be checked prior to thermal vacuum.**These sequences may be completed on a per axis basis.

111 -

(2) SDS-930 computer.

(3) OBP test racks (2).

Vibration test equipment shall include the following:

(1) Multimeter (Simpson Model 260).

(2) Polaroid camera.

(3) Accelerometers as required.

Instruments requiring calibration shall have stickers affixed showing calibration datesno more than 6 months old upon completion of the qualification test.

TEST DESCRIPTION

Prior to commencement of tests, the OBP shall be inspected for conformance to theapplicable GSFC drawing. In addition, the OBP shall be inspected for workmanship, finish,and any discernible defects. Visual inspection shall be repeated after each environmentaltest.

The OBP "flight" unit will be connected to the Code 562 computer/spacecraft inter-face equipment and subjected to typical orbital operations, including the exercise of allmodes of operation as specified in functional test procedure.

Electromagnetic and radio frequency interference tests shall be conducted in accord-ance with the EMI/RFI Test Procedure for the OBP 2.

Vibration tests will be conducted on three individual units of the OBP system as blackboxes. The mounting hole pattern is identical for all three of these units. The CPU andI/O unit will weigh approximately 13 lb;, the power converter will weigh about 8 lb. Therewill be no wires or cables connected to any of the units. A limited amount of electricalchecking may be conducted between axes only. Complete functional tests will be run bothbefore and after the vibration test.

Vibration test toleru..ces will be as follows: Sinusoidal vibration amplitude, t 10 per-cent. Vibration frequency, ±2 percent. Random vibration spectral density, ±3 dB.*

The component shall be subjected to sinusoidal vibration in each of the three mutuallyperpendicular axes shown in Figure D1. The amplitude shall be varied with frequency asshown in Table D1 at the rate of 4 octaves per minute. Four control accelerometers shall bemounted on the vibration fixture, one adjacent to each corner. The average shall be used forservo control. An xy-plot of the control level acceleration shall be provided. A I -g low levelsweep stall be performed for each axis prior to the full level sweep.

The component shall be subjected to random vibration over a frequency range of 15 to2000 Hz at the levels given in Table Dl for a period of 2 minutes per axis. An equalization

0+10% total g rms; —5% total g rma.

112

Table nl—Spacecraft acceptance levels.

SinusoidalAll Axes

(4 octaves per minute)

RandomAll Axes

(2 minutes per axis)

FrequencyLevel

FrequencyLevel

(Hz) (Hz)

5 to 20 1/2 in. displacement 15 0.010g2/Hz20 to 110 10.0-g peak 15 to 70 linear increase110 to 2000 5.0-g peak 70 to 100 0.31 g2 /Hz

100 to 400 linear decrease400 to 2000 0.02 g2/Hz

plot shall be recorded for each axis. An xy-plot of the control level acceleration shall beprovided.

The shock pulse shall approximate a half-sine pulse between 10-percent amplitudepoints as follows: amplitude tolerance, f 15 percent of peak g force; duration, t 20 percent.Four shock pulses will be administered along each axis according to the following schedule:x-axis (thrust)—two shocks (±) 30g for 6-ms duration and two shocks (f) 30g for 12-msduration; y-axis (lateral)—two shocks (t) 15g for 6-ms duration and two shocks (±) 15g for12-ms duration; and z-axis (lateral)—same as y-axis. (May be completed during vibrationtesting if expedient.)

The mounting plates of the OBP and power converter will serve as the control surfacesand will be heated by thermal pads placed in contact with the unused sides. The exposedsurfaces shall be covered with 25 layers of spacecraft insulation. Thermocouple temperaturesshall be recorded at 30-minute intervals, and the chamber pressure shall be recorded at30-minute intervals.

The components, with power applied, shall be placed in a temperature-vacuum cham-ber and subjected to a vacuum of 10-6 mm Hg. The heat-sink temperatures will be allowedto stabilize at 800 t5°F, as indicated by an average of the thermocouple readings. After anhour at this temperature, the functional tests shall be performed. After 4 hours at 80°F, thecomponent heat sink temperatures shall be raised to 150° ±5°F at a maximum rate of 3°Fper minute. After I hour of temperature stabilization, the functional tests shall be per-formed. After 8 to 16 hours of temperature stabilization, the functional tests shall berepeated. The total length of time at 150°F shall be no less than 24 hours, with at least oneadditional repeat of the functional test performeu within 8 hours from the end of thisperiod. The heat sink temperatures shall be luwered to — 300 t5°F at a maximum rate of3°F per minute. After I hour of temperature stabilization, the functional tests shall beperformed. After 8 to 16 hours of temperature stabilization, the functional tests shall berepeated. The total length of time at — 30°F shall be no less than 24 hours, with at least one

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additional repeat of the functional test performed within 8 hours from the end of this period.Component heat-sird: temperatures shall be raised to 80 0 t5'F at a maximum rate of 30°Fper minute. The functional tests shaU be performed. The chamber shall be returned toambient conditions and the functional tests shall be performed. This completes the test.

Figure Di—OBP mounting axis orientation.

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