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FDM

S3604AS Pow

erTrench® Pow

er Stage

©2011 Fairchild Semiconductor CorporationFDMS3604AS Rev.C4

www.fairchildsemi.com1

September 2011FDMS3604AS PowerTrench® Power Stage30 V Asymmetric Dual N-Channel MOSFETFeaturesQ1: N-Channel

Max rDS(on) = 8 mΩ at VGS = 10 V, ID = 13 A

Max rDS(on) = 11 mΩ at VGS = 4.5 V, ID = 11 A

Q2: N-Channel

Max rDS(on) = 2.6 mΩ at VGS = 10 V, ID = 23 A

Max rDS(on) = 3.5 mΩ at VGS = 4.5 V, ID = 21 A

Low inductance packaging shortens rise/fall times, resulting in lower switching losses

MOSFET integration enables optimum layout for lower circuit inductance and reduced switch node ringing

RoHS Compliant

General DescriptionThis device includes two specialized N-Channel MOSFETs in a dual PQFN package. The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronousSyncFET (Q2) have been designed to provide optimal power efficiency.

ApplicationsComputing

Communications

General Purpose Point of Load

Notebook VCORE

Sever

MOSFET Maximum Ratings TA = 25 °C unless otherwise noted

Thermal Characteristics

Package Marking and Ordering Information

Symbol Parameter Q1 Q2 UnitsVDS Drain to Source Voltage 30 30 VVGS Gate to Source Voltage (Note 3) ±20 ±20 V

ID

Drain Current -Continuous (Package limited) TC = 25 °C 30 40

A -Continuous (Silicon limited) TC = 25 °C 60 130 -Continuous TA = 25 °C 131a 231b

-Pulsed 40 100EAS Single Pulse Avalanche Energy 404 1125 mJ

PDPower Dissipation for Single Operation TA = 25 °C 2.21a 2.51b

WPower Dissipation for Single Operation TA = 25 °C 1.01c 1.01d

TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C

RθJA Thermal Resistance, Junction to Ambient 571a 501b

°C/WRθJA Thermal Resistance, Junction to Ambient 1251c 1201d

RθJC Thermal Resistance, Junction to Case 3.5 2

Device Marking Device Package Reel Size Tape Width Quantity22CAN7CC FDMS3604AS Power 56 13 ” 12 mm 3000 units

4

3

2

1

5

6

7

8 Q 1

Q 2

Power 56

G1 D1 D1 D1

G2S2S2 S2

D1

PHASE(S1/D2)

S2

S2

S2

G2

D1

D1

D1

G1

Top Bottom

PHASE

FDM

S3604AS Pow

erTrench® Pow

er Stage



Electrical Characteristics TJ = 25 °C unless otherwise noted

Off Characteristics

On Characteristics

Dynamic Characteristics

Switching Characteristics

Symbol Parameter Test Conditions Type Min Typ Max Units

BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 VID = 1 mA, VGS = 0 V

Q1Q2

3030 V

ΔBVDSS ΔTJ

Breakdown Voltage TemperatureCoefficient

ID = 250 μA, referenced to 25 °CID = 10 mA, referenced to 25 °C

Q1Q2 15

12 mV/°C

IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V Q1Q2

1500

μAμA

IGSSGate to Source Leakage Current, Forwad VGS = 20 V, VDS= 0 V Q1

Q2 100100

nAnA

VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μAVGS = VDS, ID = 1 mA

Q1Q2

1.11.1

21.8

2.73 V

ΔVGS(th) ΔTJ

Gate to Source Threshold VoltageTemperature Coefficient

ID = 250 μA, referenced to 25 °CID = 10 mA, referenced to 25 °C

Q1Q2

-6-5 mV/°C

rDS(on) Drain to Source On Resistance

VGS = 10 V, ID = 13 A VGS = 4.5 V, ID = 11 A VGS = 10 V, ID = 13 A , TJ = 125 °C

Q15.88.57.8

811

10.8mΩ

VGS = 10 V, ID = 23 A VGS = 4.5 V, ID = 21 A VGS = 10 V, ID = 23 A , TJ = 125 °C

Q22

2.62.6

2.63.54

gFS Forward Transconductance VDS = 5 V, ID = 13 AVDS = 5 V, ID = 23 A

Q1Q2

61130 S

Ciss Input Capacitance Q1:VDS = 15 V, VGS = 0 V, f = 1 MHZ

Q2: VDS = 15 V, VGS = 0 V, f = 1 MHZ

Q1Q2 1273

307816954095 pF

Coss Output Capacitance Q1Q2

4611169

6151555 pF

Crss Reverse Transfer Capacitance Q1Q2

5098

75150 pF

Rg Gate Resistance Q1Q2

0.20.2

0.60.8

23 Ω

td(on) Turn-On Delay TimeQ1:VDD = 15 V, ID = 13 A, RGEN = 6 Ω

Q2:VDD = 15 V, ID = 23 A, RGEN = 6 Ω

Q1Q2 8.2

131623 ns

tr Rise Time Q1Q2 2.5

4.81010 ns

td(off) Turn-Off Delay Time Q1Q2 20

313250 ns

tf Fall Time Q1Q2 2.2

3.41010 ns

Qg Total Gate Charge VGS = 0 V to 10 V Q1 VDD = 15 V, ID = 13 A

Q2 VDD = 15 V, ID = 23 A

Q1Q2

2147

2966 nC

Qg Total Gate Charge VGS = 0 V to 4.5 V Q1Q2

1022

1431 nC

Qgs Gate to Source Gate Charge Q1Q2 3.9

9 nC

Qgd Gate to Drain “Miller” Charge Q1Q2 3.1

5.5 nC

FDM

S3604AS Pow

erTrench® Pow

er Stage



Electrical Characteristics TJ = 25 °C unless otherwise noted

Drain-Source Diode Characteristics

Symbol Parameter Test Conditions Type Min Typ Max Units

VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 13 A (Note 2)VGS = 0 V, IS = 23A (Note 2)

Q1Q2 0.8

0.81.21.2 V

trr Reverse Recovery Time Q1IF = 13 A, di/dt = 100 A/μsQ2IF = 23 A, di/dt = 300 A/μs

Q1Q2

2532

4051 ns

Qrr Reverse Recovery Charge Q1Q2 9

391862 nC

Notes:1: RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined

by the user's board design.

2: Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.

3: As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.

4: EAS of 40 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 9 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 14 A.

5: EAS of 112 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 15 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 22 A.

a. 57 °C/W when mounted on a 1 in2 pad of 2 oz copper

c. 125 °C/W when mounted on a minimum pad of 2 oz copper

b. 50 °C/W when mounted on a 1 in2 pad of 2 oz copper

d. 120 °C/W when mounted on a minimum pad of 2 oz copper

FDM

S3604AS Pow

erTrench® Pow

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Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted

Figure 1.

0.0 0.2 0.4 0.6 0.8 1.00

10

20

30

40

VGS = 4.5 V

VGS = 3.5 V

VGS = 6 V

VGS = 4 V

PULSE DURATION = 80 μsDUTY CYCLE = 0.5% MAX

VGS = 10 V

I D, D

RA

IN C

UR

REN

T (A

)

VDS, DRAIN TO SOURCE VOLTAGE (V)

On Region Characteristics Figure 2.

0 10 20 30 400

1

2

3

4

VGS = 6 V

VGS = 3.5 V


NO

RM

ALI

ZED

DR

AIN

TO

SO

UR

CE

ON

-RES

ISTA

NC

E

ID, DRAIN CURRENT (A)

VGS = 4 V

VGS = 4.5 V

VGS = 10 V

Normalized On-Resistance vs Drain Current and Gate Voltage

Figure 3. Normalized On Resistance

-75 -50 -25 0 25 50 75 100 125 1500.6

0.8

1.0

1.2

1.4

1.6

ID = 13 AVGS = 10 V

NO

RM

ALI

ZED

DR

AIN

TO

SO

UR

CE

ON

-RES

ISTA

NC

E

TJ, JUNCTION TEMPERATURE (oC)

vs Junction TemperatureFigure 4.

2 4 6 8 100

4

8

12

16

20

TJ = 125 oC

ID = 13 A

TJ = 25 oC

VGS, GATE TO SOURCE VOLTAGE (V)

r DS(

on),

DR

AIN

TO

SO

UR

CE

ON

-RES

ISTA

NC

E (m

Ω) PULSE DURATION = 80 μs

DUTY CYCLE = 0.5% MAX

On-Resistance vs Gate to Source Voltage

Figure 5. Transfer Characteristics

1.5 2.0 2.5 3.0 3.5 4.00

10

20

30

40

TJ = 150 oCVDS = 5 V


TJ = -55 oC

TJ = 25 oC

I D, D

RA

IN C

UR

REN

T (A

)


Figure 6.

0.0 0.2 0.4 0.6 0.8 1.0 1.20.001

0.01

0.1

1

10

40

TJ = -55 oC

TJ = 25 oCTJ = 150 oC

VGS = 0 V

I S, R

EVER

SE D

RA

IN C

UR

REN

T (A

)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Source to Drain Diode Forward Voltage vs Source Current

FDM

S3604AS Pow

erTrench® Pow

er Stage



Figure 7.

0 5 10 15 20 250

2

4

6

8

10ID = 13 A

VDD = 20 V

VDD = 10 V

V GS,

GA

TE T

O S

OU

RC

E VO

LTA

GE

(V)

Qg, GATE CHARGE (nC)

VDD = 15 V

Gate Charge Characteristics Figure 8.

0.1 1 10 3010

100

1000

2000

f = 1 MHzVGS = 0 V

CA

PAC

ITA

NC

E (p

F)


Crss

Coss

Ciss

Capacitance vs Drain to Source Voltage

Figure 9.

0.01 0.1 1 10 1001

10

20

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

I AS,

AVA

LAN

CH

E C

UR

REN

T (A

)

Unclamped Inductive Switching Capability

Figure 10.

25 50 75 100 125 1500

20

40

60

80

100

Limited by Package

VGS = 4.5 V

RθJC = 3.5 oC/W

VGS = 10 VI D

, DR

AIN

CU

RR

ENT

(A)

TC, CASE TEMPERATURE (oC)

Maximum Continuous Drain Current vs Case Temperature

Figure 11. Forward Bias Safe Operating Area

Figure 12. Single Pulse Maximum Power Dissipation


0.01 0.1 1 10 1000.01

0.1

1

10

100

DC

100 ms

10 ms

1 ms

1s

I D, D

RA

IN C

UR

REN

T (A

)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS AREA IS LIMITED BY rDS(on)

SINGLE PULSETJ = MAX RATEDRθJA = 125 oC/WTA = 25 oC

10s

100us

200 10-4 10-3 10-2 10-1 1 10 100 10000.1

1

10

100

1000

SINGLE PULSERθJA = 125 oC/WTA = 25 oC

P(PK

), PE

AK

TR

AN

SIEN

T PO

WER

(W)

t, PULSE WIDTH (sec)

FDM

S3604AS Pow

erTrench® Pow

er Stage



Figure 13. Junction-to-Ambient Transient Thermal Response Curve

10-4 10-3 10-2 10-1 1 10 100 10000.001

0.01

0.1

1

SINGLE PULSERθJA = 125 oC/W(Note 1c)

DUTY CYCLE-DESCENDING ORDER

NO

RM

ALI

ZED

TH

ERM

AL

IMPE

DA

NC

E, Z

θJA

t, RECTANGULAR PULSE DURATION (sec)

D = 0.5 0.2 0.1 0.05 0.02 0.01

2

PDM

t1t2

NOTES:DUTY FACTOR: D = t1/t2PEAK TJ = PDM x ZθJA x RθJA + TA


FDM

S3604AS Pow

erTrench® Pow

er Stage



Typical Characteristics (Q2 N-Channel) TJ = 25 oC unlenss otherwise noted

0.0 0.2 0.4 0.6 0.8 1.00

20

40

60

80

100

VGS = 4.5 V

VGS = 3 V

VGS = 3.5 V

VGS = 4 V


VGS = 10 V

I D, D

RA

IN C

UR

REN

T (A

)


Figure 14. On-Region Characteristics

0 20 40 60 80 1000

2

4

6

8

VGS = 3 V

VGS = 3.5 V


NO

RM

ALI

ZED

DR

AIN

TO

SO

UR

CE

ON

-RES

ISTA

NC

E

ID, DRAIN CURRENT (A)

VGS = 4 V VGS = 4.5 V

VGS = 10 V

Figure 15. Normalized on-Resistance vs Drain Current and Gate Voltage

Figure 16. Normalized On-Resistance vs Junction Temperature

-75 -50 -25 0 25 50 75 100 125 1500.8

1.0

1.2

1.4

1.6

ID = 23 AVGS = 10 V

NO

RM

ALI

ZED

DR

AIN

TO

SO

UR

CE

ON

-RES

ISTA

NC

E

TJ, JUNCTION TEMPERATURE (oC)2 4 6 8 10

0

3

6

9

12

TJ = 125 oC

ID = 23 A

TJ = 25 oC


r DS(

on),

DR

AIN

TO

SO

UR

CE

ON

-RES

ISTA

NC

E (m

Ω) PULSE DURATION = 80 μs

DUTY CYCLE = 0.5% MAX

Figure 17. On-Resistance vs Gate to Source Voltage

Figure 18. Transfer Characteristics

1.5 2.0 2.5 3.0 3.5 4.00

20

40

60

80

100

TJ = 125 oC

VDS = 5 V


TJ = -55 oC

TJ = 25 oC

I D, D

RA

IN C

UR

REN

T (A

)


Figure 19. Source to Drain Diode Forward Voltage vs Source Current

0.0 0.2 0.4 0.6 0.8 1.0 1.20.001

0.01

0.1

1

10

100

TJ = -55 oC

TJ = 25 oC

TJ = 125 oC

VGS = 0 V

I S, R

EVER

SE D

RA

IN C

UR

REN

T (A

)

VSD, BODY DIODE FORWARD VOLTAGE (V)

Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted

Figure 20. Gate Charge Characteristics

0 10 20 30 40 500

2

4

6

8

10ID = 23 A

VDD = 20 V

VDD = 10 V

V GS,

GA

TE T

O S

OU

RC

E VO

LTA

GE

(V)

Qg, GATE CHARGE (nC)

VDD = 15 V

0.1 1 10 3010

100

1000

10000

f = 1 MHzVGS = 0 V

CA

PAC

ITA

NC

E (p

F)


Crss

Coss

Ciss

Figure 21. Capacitance vs Drain to Source Voltage

Figure 22. Unclamped Inductive Switching Capability

0.01 0.1 1 10 100 10001

10

50

TJ = 100 oC

TJ = 25 oC

TJ = 125 oC

tAV, TIME IN AVALANCHE (ms)

I AS,

AVA

LAN

CH

E C

UR

REN

T (A

)

25 50 75 100 125 1500

40

80

120

160RθJC = 2 oC/W

VGS = 4.5 V

Limited by Package

VGS = 10 V

I D, D

RA

IN C

UR

REN

T (A

)

TC, CASE TEMPERATURE (oC)

Figure 23. Maximun Continuous Drain Current vs Case Temperature

Figure 24. Forward Bias Safe Operating Area

Figure 25. Single Pulse Maximum Power Dissipation

FDM

S3604AS Pow

erTrench® Pow

er Stage



0.01 0.1 1 10 1002000.01

0.1

1

10

100200

DC

100 ms

10 ms

1 ms

1s

I D, D

RA

IN C

UR

REN

T (A

)

VDS, DRAIN to SOURCE VOLTAGE (V)

THIS AREA IS LIMITED BY rDS(on)

SINGLE PULSETJ = MAX RATEDRθJA = 120 oC/WTA = 25 oC

10s

10-3 10-2 10-1 1 10 100 10000.1

1

10

100

1000

SINGLE PULSERθJA = 120 oC/WTA = 25 oC

P(PK

), PE

AK

TR

AN

SIEN

T PO

WER

(W)

t, PULSE WIDTH (sec)

FDM

S3604AS Pow

erTrench® Pow

er Stage



Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted

Figure 26. Junction-to-Ambient Transient Thermal Response Curve

10-3 10-2 10-1 1 10 100 10000.001

0.01

0.1

12

SINGLE PULSERθJA = 120 oC/W(Note 1d)

DUTY CYCLE-DESCENDING ORDER

NO

RM

ALI

ZED

TH

ERM

AL

IMPE

DA

NC

E, Z

θJA

t, RECTANGULAR PULSE DURATION (sec)

D = 0.5 0.2 0.1 0.05 0.02 0.01

PDM

t1t2

NOTES:DUTY FACTOR: D = t1/t2PEAK TJ = PDM x ZθJA x RθJA + TA

FDM

S3604AS Pow

erTrench® Pow

er Stage



SyncFET Schottky body diode Characteristics

Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverse recovery characteristic of the FDMS3604AS.

Schottky barrier diodes exhibit significant leakage at high tem-perature and high reverse voltage. This will increase the power in the device.

0 50 100 150 200-5

0

5

10

15

20

25

didt = 300 A/μs

CU

RR

ENT

(A)

TIME (ns)

Typical Characteristics (continued)

Figure 27. FDMS3604AS SyncFET body diode reverse recovery characteristic

Figure 28. SyncFET body diode reverse leakage versus drain-source voltage

0 5 10 15 20 25 3010-6

10-5

10-4

10-3

10-2

TJ = 125 oC

TJ = 100 oC

TJ = 25 oC

I DSS

, REV

ERSE

LEA

KA

GE

CU

RR

ENT

(A)

VDS, REVERSE VOLTAGE (V)

FDM

S3604AS Pow

erTrench® Pow

er Stage



Application Information

1. Switch Node Ringing Suppression Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage solution rings significantly less than competitor solutions under the same set of test conditions.

Power Stage Device Competitors solution

Figure 29. Power Stage phase node rising edge, High Side Turn on

*Patent Pending

FDM

S3604AS Pow

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Figure 30. Shows the Power Stage in a buck converter topology

2. Recommended PCB Layout GuidelinesAs a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2), should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout proce-dure is discussed below to maximize the electrical and thermal performance of the part.

Figure 31. Recommended PCB Layout

FDM

S3604AS Pow

erTrench® Pow

er Stage



Following is a guideline, not a requirement which the PCB designer should consider:

1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected depending upon the application.

2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance between the thermal and electrical performance of Power Stage.

3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be directly in line (as shown in figure 31) with the inductor for space savings and compactness.

4. The PowerTrench® Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen the high-frequency ringing.

5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the MOSFET and turns the devices on and off as efficiently as possible. At higher-frequency operation this impedance can limit the gate current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses. Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This provides a very compact path for the drive signals and improves efficiency of the part.

6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET.

7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction. Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected from the backside via a network of low inductance vias.

3.162.80

CL

LCPKG

PKG

5.104.90

6.255.90

C

3.81

1.020.82

TOP VIEW

SIDE VIEW

BOTTOM VIEW

1 4

8 5

1 2 3 4

8 7 6

0.10 C A B

0.05 C

2.252.05

5

0.650.38

(SCALE: 2X)

0.050.00

0.350.15

0.08 C

SEATING

PLANE

0.10 C

1.100.90

RECOMMENDED LAND PATTERN

0.65 TYP

1 2 3 4

5 6 7 8

1.27

1.341.12

A0.10 C

(2X)B

0.10 C

(2X)

0.0

0

0.00

1.60

2.52

1.21

2.31

1.1

8

1.27 TYP

2.0

0

2.15

0.63

0.630.59

3.18

4.00CL

CL

0.650.38

2.13

3.15

0.450.25

0.700.36

4.083.70

0.440.24

(6X)

0.66±.05

4.16

0.610.31

KEEP OUT AREA

8X

PIN # 1

INDICATOR

5.10

SEE

DETAIL A

(8X)

FOR SAWN / PUNCHED TYPE

(SCALE: 2X)

0.350.15

0.280.08

10°

NOTES: UNLESS OTHERWISE SPECIFIED

A) PACKAGE STANDARD REFERENCE:

JEDEC REGISTRATION, MO-240, VARIATION AA.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE BURRS OR

MOLD FLASH. MOLD FLASH OR BURRS DOES

NOT EXCEED 0.10MM.

D) DIMENSIONING AND TOLERANCING PER

ASME Y14.5M-1994.

E) IT IS RECOMMENDED TO HAVE NO TRACES

OR VIAS WITHIN THE KEEP OUT AREA.

F) DRAWING FILE NAME: PQFN08EREV6.

G) FAIRCHILD SEMICONDUCTOR

CL

LCPKG

PKG

5.104.90

6.255.90

C

3.162.80

3.81

1.020.82

TOP VIEW

SIDE VIEW

1 4

8 5

1 2 3 4

8 7 6

0.10 C A B

0.05 C

5

0.650.38

SEE

DETAIL B

1.27

0.66±.05

1.341.12

(2X)

(2X)

0.650.38

0.450.25

0.700.36

4.083.70

0.440.24

(6X)

5.004.80

5.905.70

0.410.21

(8X)

2.252.05

0.610.31

0.10 C

1.100.90

0.350.15

SEATING

PLANE

8X

SEE

DETAIL C

(SCALE: 2X)

BOTTOM VIEW

(8X)

0.10 C

0.10 C

0.08 C

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Fairchild® Fairchild Semiconductor® FACT Quiet Series FACT® FastvCore FETBench FPS

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and Better™

MegaBuck MICROCOUPLER MicroFET MicroPak MicroPak2 MillerDrive MotionMax MotionGrid® MTi® MTx® MVN® mWSaver® OptoHiT OPTOLOGIC®

OPTOPLANAR®

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Power Supply WebDesigner PowerTrench®

PowerXS™ Programmable Active Droop QFET® QS Quiet Series RapidConfigure

Saving our world, 1mW/W/kW at a time™ SignalWise SmartMax SMART START Solutions for Your Success SPM® STEALTH SuperFET® SuperSOT-3 SuperSOT-6 SuperSOT-8 SupreMOS® SyncFET Sync-Lock™

®*

TinyBoost® TinyBuck® TinyCalc TinyLogic® TINYOPTO TinyPower TinyPWM TinyWire TranSiC TriFault Detect TRUECURRENT®* SerDes

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DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. TO OBTAIN THE LATEST, MOST UP-TO-DATE DATASHEET AND PRODUCT INFORMATION, VISIT OUR WEBSITE AT HTTP://WWW.FAIRCHILDSEMI.COM. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

AUTHORIZED USE

Unless otherwise specified in this data sheet, this product is a standard commercial product and is not intended for use in applications that require extraordinary levels of quality and reliability. This product may not be used in the following applications, unless specifically approved in writing by a Fairchild officer: (1) automotive or other transportation, (2) military/aerospace, (3) any safety critical application – including life critical medical equipment – where the failure of the Fairchild product reasonably would be expected to result in personal injury, death or property damage. Customer’s use of this product is subject to agreement of this Authorized Use policy. In the event of an unauthorized use of Fairchild’s product, Fairchild accepts no liability in the event of product failure. In other respects, this product shall be subject to Fairchild’s Worldwide Terms and Conditions of Sale, unless a separate agreement has been signed by both Parties.

ANTI-COUNTERFEITING POLICY

Fairchild Semiconductor Corporation's Anti-Counterfeiting Policy. Fairchild's Anti-Counterfeiting Policy is also stated on our external website, www.fairchildsemi.com, under Terms of Use

Counterfeiting of semiconductor parts is a growing problem in the industry. All manufacturers of semiconductor products are experiencing counterfeiting of their parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed applications, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild's quality standards for handling and storage and provide access to Fairchild's full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address any warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.

Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.

Rev. I77

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Documents

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