Embed Size (px)
Citation preview
GA-M59SLI-S5 introduction
2 Date1120419 Dept
By Eddie
nForce 500 Series Chipset
nForce 500 Series nForce 590 SLI nForce 570 SLI nForce 570 Ultra nForce 550
Features
Segment Enthusiast SLI (2x16) Performance SLI SLI (2x8) Performance non-SLI Mainstream
CPU Athlon 64 FX Athlon 64 X2 At
hlon 64Athlon 64 FX Athlon 64 X2 At
hlon 64Athlon 64 FX Athlon 64 X2 Athl
on 64Athlon 64 FX Athlon 64 X2 Se
mpron
NVIDIA LinkBoosttrade technology Yes No No No
NVIDIAreg SLItrade TechnologyYes Yes
No No2 x 16 1 x16 2 x 8
PCI Express Lanes 46 lanes 28 lanes 20 lanes 20 lanes
PCI Express Links 9 links 6 links 5 links 5 links
Configuration 16 16 8 1 1 11 1 1 16 8 1 1 11 16 1 1 11 16 1 1 11
SATAPATA drives6 SATA2 PATA
6 SATA2 PATA
6 SATA2 PATA
4 SATA2 PATA
SATA speed 3Gbs 3Gbs 3Gbs 3Gbs
RAID 010+15 010+15 010+15 010+1
Native Ethernet Connection 2 x 101001000 2 x 101001000 2 x 101001000 1 x 101001000
NVIDIA FirstPackettrade technology Yes Yes Yes No
NVIDIA DualNetreg technology Yes Yes Yes No
Teaming Yes Yes Yes No
TCPIP Acceleration Yes Yes Yes No
NVIDIA nTunetrade Utility Yes Yes Yes Yes
USB ports 10 10 10 10
PCI Slots 5 5 5 5
Audio HDA HDA HDA HDA
3 Date1120419 Dept
By Eddie
nForce 550 Block Diagram
4 Date1120419 Dept
By Eddie
nForce 570 Ultra Block Diagram
5 Date1120419 Dept
By Eddie
nForce 570 SLI Block Diagram
6 Date1120419 Dept
By Eddie
nForce 590 Block Diagram
7 Date1120419 Dept
By Eddie
MCP55PXE Diagram
ATA 133
USB 20 EHCI USB 11 OHCI
NVIDIA MAC 1
High Definition Audio
Management Processor
PCI Bridge
LPC Bridge
ACPIPM SMBUS2010
RTC
Legacy
8259APCI82378254
Clock Synthesizer
LPC SuperIO
LPC Flash
SATA3 Gbs PHY
SATA3 Gbs PHY
SATA 3Gbs
SATA 3Gbs
SATA3 Gbs PHY
NVIDIA MAC 0
PCI Express
Controller 1
Controller 2
Controller 3
Controller 4
Controller 5
Controller 6
SerialPort
Hyper TransportInterface
SATA 3Gbs
PCI-33
LPC BUS
Serial ATA3 Gb s
Serial ATA3 Gb s
Serial ATA3 Gb s
RS232
PCI Express
2 Drives
10 Ports
RGMIIMII
RGMII
SMBus
HDA
Hyper Transport Link
NVIDIA SPP
Inte
rnal B
us
The NVIDIA MCP55PXE integrates the following features1048713 1 GHz HyperTransport x16 up and down links to the AMD Socket AM2 CPUs1048713 Six separate and independent PCI Express controllers and twenty eight PCI Express lanes1048713 Three separate SATA controllers each with integrated dual PHYs that are capable of operating at 15 Gbps and 30 Gbps speeds1048713 Fast ATA-133 IDE controller Support for a master device and a slave device1048713 NVIDIA MediaShieldtrade RAID with support for RAID 0 RAID 1 RAID 0+1 RAID 5 and JBOD1048713 Dual IEEE 8023 NVIDIA MACs for 1000BASE-T100BASE-T10BASE-T GigabitFast EthernetEthernet with TCP Offload Engine (TOE)1048713 RGMII for GigabitFast EthernetEthernet OR MII for Fast EthernetEthernet
1048713 IPMI 20 pass through support for remote management1048713 Integrated management processor with dedicated SMBUS and dedicated GPIOs1048713 USB 20 EHCI and USB 11 OHCI Supports up to ten ports1048713 PCI 23 interface Supports up to 5 PCI slots with dedicated REQGNT pairs1048713 Dual SMBus 20 interfaces1048713 UAA (Universal Audio Architecture) High Definition Audio interface1048713 Supports up to 3 external UAA High Definition Audio codecs for 71 channel audio1048713 Supports 32-bit 192 kHz audio functionality1048713 LPC bus 10 compatible interface1048713 Integrated AT legacy controllers1048713 Integrated clock synthesizer with spread spectrum capability1048713 Programmable active power management unit1048713 Integrated serial port1048713 AMD Socket AM2 CPUs power sequencing protection logic1048713 33 mm times 33 mm 1 mm ball pitch PBGA
8 Date1120419 Dept
By Eddie
C51XE Diagram
Hyper TransportInterface
Hyper TransportInterface
AMD Athlon 64Athlon 64 FX
Processors
PCI Expressx1 Root Port
PCI Expressx1 Root Port
PCI Expressx16 Root Port
ExternalPCI Express
Device
ExternalPCI Express
Device
ExternalPCI Express
Device
Hyper Transport Link 1 GHz
Hyper Transport Link 1 GHz
x1
x16
x1
MCP51XE
Inte
rnal B
us
IntegratedClock Synthesizer
Active PowerManagement
The NVIDIA C51XE includes the following features1048713 Primary HyperTransport link up to 10 GHz to the CPU1048713 Secondary HyperTransport link up to 10 GHz1048713 PCI Express 16 lane link interface for external graphics processors1048713 Dual PCI Express single lane link interface with dedicated controller for other peripherals1048713 Integrated power management processor1048713 Programmable clock synthesizer1048713 25 mm times 25 mm 10 mm ball pitch PBGA
9 Date1120419 Dept
By Eddie
GA-M59SLI-S5 BLOCK DIAGRAM
KBMS
FAN
DDR2 CHANNEL B
CKG
CKG
AUDIO
C51XE
IDE
RJ45
SUPER IO
GIGABYTE
33MHz
DUAL
RGMII-1BUS
FDD
100MHz
COM
SATAII 6 PORTS
PCI-E X16
TI1394a 3ports
MCP55XE
SATAII
100MHz
PCI SLOT
100MHz
LPC BUS
100MHz
AMD M2 Processor
33MHz
100MHz
PCI Express
DDR2 DIMM SLOT
PCI-E X1
HT LINK
DDR2 DIMM SLOT
PCI Express
PCI SLOT
PCI-E X1
DDR2 CHANNEL A
PCI Express
100MHz
1GHz
DDR2 DIMM SLOT
PCI Express
HT clock
88E1116
1GHz
CPU clock
ITE 8716
200MHz
PCI-E X8
PCI-E X16
SATAII 2 PORTS
USB 10 PORTS
33MHz
PCI Express
PCI BUS
ALC888DD
88E1116
RGMII-2BUS
BIOS
PCI Express
HT LINK
HD signal
DDR2 DIMM SLOT
200MHz
RJ45
10 Date1120419 Dept
By Eddie
PS ON-IO_PSON-PWRBTSW
PW
RB
TS
W
SLP
_S3
PSIN
IT8716
nVIDIAVIDIA
MCP55P
5VSBSystem
On-Off
Button
5VSBrarr5VDUAL
3VDUAL
BATTERY
3VDUAL
RTC
VD
D
-RTC
RSTV
BA
T
32768KHZ
Pow
er O
n O
ff
Circ
uitry
SB
_PW
OK
ATXPower Supply
2500MHZ
VCC12DUAL
11 Date1120419 Dept
By Eddie
System Reset Map
IDE
PCI SLOT
PCIE_16_1
MCP55P
C51XEAMD K8
AM2
ATX
SB_PWOK
PWRGD
SLP_S3
HTMCP_PWRGD
HTMCP_RST
PS ON
PWOK
1394RST
MII_RST
ACZ_RST
PPCIRST_SLOT1
PPCIRST_SLOT2
HT_CPU_PWRGD
HT_CPU_RST
LPCRST_SIO LPCRST_FLASH
IDERST
PCIE_RST
IEEE 1394TSB43AB23
MARVELL88E1116
ALC888
ITE8716GBCX
DUALBIOS
PCIE_16_2
PCIE_8
PCIE_1
PCIE_2
MARVELL88E1116
12 Date1120419 Dept
By Eddie
ROM
AMD K8
AM2
C51XE
MCP55P
PCIRST
HT_VDD_EN
CPU_VDD_EN
SLP_S3
SLP_S5
LPC_PD
HT_VLD
CPU_VLD
MEM_VLD
SB_PWOK
CK8_PWOK
HT
_ST
OP
HT
_RE
Q
HT
_MC
P_P
WR
GD
HT
_MC
P_R
ST
HT
_MC
P_D
NH
T_M
CP
_U
P
HT
_CP
U_D
NH
T_C
PU
_U
P
HT
_CP
U_R
ST
HT
_CP
U_P
WR
GD
CP
U_C
LK
PRSNT
PERST
PE_REFCLK
CR
_R
EF
_C
LK
C51XEMCP55PXE Power Sequencing Block Diagram
13 Date1120419 Dept
By Eddie
GA-M59SLI-S5 System Clock
HT_CPU_TX_CLK[01]_NHT_CPU_RX_CLK[01]_P
CLKOUT 200MHZ_N
CLKIN 200MHZ_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_N
CLKOUT 200MHZ_P
CLKIN 200MHZ_N
HT_CPU_RX_CLK[01]_P
HT_CPU_TX_CLK[01]_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_P
HT_MCP_TX_CLK[01]_PHT_MCP_TX_CLK[01]_N
HT_MCP_TX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
CLKIN_25MHZ
CLKIN 200MHZ_PCLKIN 200MHZ_N
CLKOUT_25MHZCLKOUT 200MHZ_P
CLKOUT 200MHZ_N
HT_MCP_TX_CLK[01]_P
LPC_CLK1
HDA_BCLK
MA0_CLK[20]_N
MB0_CLK[20]_N
MA1_CLK[20]_NMA1_CLK[20]_P
MA0_CLK[20]_P
MB0_CLK[20]_P
MB1_CLK[20]_PMB1_CLK[20]_N
DIMM 0 MEM_B0
DIMM 0 MEM_B1
DIMM 0 MEM_A0
DIMM 0 MEM_A1
BUF_SIO_CLKLPC_CLK0
PCI_CLK0
PCI_CLK3PCI_CLK2PCI_CLK1
PCI_CLK4
PCI_CLKINPCI_CLK5
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PE1_REFCLK_N
PE2_REFCLK_N
PE2_REFCLK_P
PE1_REFCLK_P
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PEX X 8PE5_REFCLK_NPE5_REFCLK_P
PE1_REFCLK_PPE1_REFCLK_N PEX X 1
PE3_REFCLK_PPE3_REFCLK_N PEX X 1
PE2_REFCLK_NPE2_REFCLK_P
GIGABYTESATA 2
Super IO
PCICLK1
PCICLK2TPM
1394CLK
BIOSHDA
CODECXTALIN
XTALOUT
XTALIN_RTCXTALOUT_RTC
14 Date1120419 Dept
By Eddie
Power-Up Sequence
Core Planes include+12V Core+15V_PLL_HT +33V_PLL_HT+15V_PE_PLL_AVDD +15V_PE_PLL_DVDD +15V_PE_PLL_CORE+15V_PE_D +15V_PE_A +33V_PE_PLL_CORE+15V_SP_PLL_AVDD +15V_SP_PLL_DVDD +15V_SP_PLL_CORE+15V_SP_D +15V_SP_A +33V_SP_PLL_CORE+33V_PLL_CPU +33V_PLL_USB+33V +50V_CLAMP
15 Date1120419 Dept
By Eddie
AMD Socket 939 Architecture
16 Date1120419 Dept
By Eddie
AMD Socket 940 Architecture
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
2 Date1120419 Dept
By Eddie
nForce 500 Series Chipset
nForce 500 Series nForce 590 SLI nForce 570 SLI nForce 570 Ultra nForce 550
Features
Segment Enthusiast SLI (2x16) Performance SLI SLI (2x8) Performance non-SLI Mainstream
CPU Athlon 64 FX Athlon 64 X2 At
hlon 64Athlon 64 FX Athlon 64 X2 At
hlon 64Athlon 64 FX Athlon 64 X2 Athl
on 64Athlon 64 FX Athlon 64 X2 Se
mpron
NVIDIA LinkBoosttrade technology Yes No No No
NVIDIAreg SLItrade TechnologyYes Yes
No No2 x 16 1 x16 2 x 8
PCI Express Lanes 46 lanes 28 lanes 20 lanes 20 lanes
PCI Express Links 9 links 6 links 5 links 5 links
Configuration 16 16 8 1 1 11 1 1 16 8 1 1 11 16 1 1 11 16 1 1 11
SATAPATA drives6 SATA2 PATA
6 SATA2 PATA
6 SATA2 PATA
4 SATA2 PATA
SATA speed 3Gbs 3Gbs 3Gbs 3Gbs
RAID 010+15 010+15 010+15 010+1
Native Ethernet Connection 2 x 101001000 2 x 101001000 2 x 101001000 1 x 101001000
NVIDIA FirstPackettrade technology Yes Yes Yes No
NVIDIA DualNetreg technology Yes Yes Yes No
Teaming Yes Yes Yes No
TCPIP Acceleration Yes Yes Yes No
NVIDIA nTunetrade Utility Yes Yes Yes Yes
USB ports 10 10 10 10
PCI Slots 5 5 5 5
Audio HDA HDA HDA HDA
3 Date1120419 Dept
By Eddie
nForce 550 Block Diagram
4 Date1120419 Dept
By Eddie
nForce 570 Ultra Block Diagram
5 Date1120419 Dept
By Eddie
nForce 570 SLI Block Diagram
6 Date1120419 Dept
By Eddie
nForce 590 Block Diagram
7 Date1120419 Dept
By Eddie
MCP55PXE Diagram
ATA 133
USB 20 EHCI USB 11 OHCI
NVIDIA MAC 1
High Definition Audio
Management Processor
PCI Bridge
LPC Bridge
ACPIPM SMBUS2010
RTC
Legacy
8259APCI82378254
Clock Synthesizer
LPC SuperIO
LPC Flash
SATA3 Gbs PHY
SATA3 Gbs PHY
SATA 3Gbs
SATA 3Gbs
SATA3 Gbs PHY
NVIDIA MAC 0
PCI Express
Controller 1
Controller 2
Controller 3
Controller 4
Controller 5
Controller 6
SerialPort
Hyper TransportInterface
SATA 3Gbs
PCI-33
LPC BUS
Serial ATA3 Gb s
Serial ATA3 Gb s
Serial ATA3 Gb s
RS232
PCI Express
2 Drives
10 Ports
RGMIIMII
RGMII
SMBus
HDA
Hyper Transport Link
NVIDIA SPP
Inte
rnal B
us
The NVIDIA MCP55PXE integrates the following features1048713 1 GHz HyperTransport x16 up and down links to the AMD Socket AM2 CPUs1048713 Six separate and independent PCI Express controllers and twenty eight PCI Express lanes1048713 Three separate SATA controllers each with integrated dual PHYs that are capable of operating at 15 Gbps and 30 Gbps speeds1048713 Fast ATA-133 IDE controller Support for a master device and a slave device1048713 NVIDIA MediaShieldtrade RAID with support for RAID 0 RAID 1 RAID 0+1 RAID 5 and JBOD1048713 Dual IEEE 8023 NVIDIA MACs for 1000BASE-T100BASE-T10BASE-T GigabitFast EthernetEthernet with TCP Offload Engine (TOE)1048713 RGMII for GigabitFast EthernetEthernet OR MII for Fast EthernetEthernet
1048713 IPMI 20 pass through support for remote management1048713 Integrated management processor with dedicated SMBUS and dedicated GPIOs1048713 USB 20 EHCI and USB 11 OHCI Supports up to ten ports1048713 PCI 23 interface Supports up to 5 PCI slots with dedicated REQGNT pairs1048713 Dual SMBus 20 interfaces1048713 UAA (Universal Audio Architecture) High Definition Audio interface1048713 Supports up to 3 external UAA High Definition Audio codecs for 71 channel audio1048713 Supports 32-bit 192 kHz audio functionality1048713 LPC bus 10 compatible interface1048713 Integrated AT legacy controllers1048713 Integrated clock synthesizer with spread spectrum capability1048713 Programmable active power management unit1048713 Integrated serial port1048713 AMD Socket AM2 CPUs power sequencing protection logic1048713 33 mm times 33 mm 1 mm ball pitch PBGA
8 Date1120419 Dept
By Eddie
C51XE Diagram
Hyper TransportInterface
Hyper TransportInterface
AMD Athlon 64Athlon 64 FX
Processors
PCI Expressx1 Root Port
PCI Expressx1 Root Port
PCI Expressx16 Root Port
ExternalPCI Express
Device
ExternalPCI Express
Device
ExternalPCI Express
Device
Hyper Transport Link 1 GHz
Hyper Transport Link 1 GHz
x1
x16
x1
MCP51XE
Inte
rnal B
us
IntegratedClock Synthesizer
Active PowerManagement
The NVIDIA C51XE includes the following features1048713 Primary HyperTransport link up to 10 GHz to the CPU1048713 Secondary HyperTransport link up to 10 GHz1048713 PCI Express 16 lane link interface for external graphics processors1048713 Dual PCI Express single lane link interface with dedicated controller for other peripherals1048713 Integrated power management processor1048713 Programmable clock synthesizer1048713 25 mm times 25 mm 10 mm ball pitch PBGA
9 Date1120419 Dept
By Eddie
GA-M59SLI-S5 BLOCK DIAGRAM
KBMS
FAN
DDR2 CHANNEL B
CKG
CKG
AUDIO
C51XE
IDE
RJ45
SUPER IO
GIGABYTE
33MHz
DUAL
RGMII-1BUS
FDD
100MHz
COM
SATAII 6 PORTS
PCI-E X16
TI1394a 3ports
MCP55XE
SATAII
100MHz
PCI SLOT
100MHz
LPC BUS
100MHz
AMD M2 Processor
33MHz
100MHz
PCI Express
DDR2 DIMM SLOT
PCI-E X1
HT LINK
DDR2 DIMM SLOT
PCI Express
PCI SLOT
PCI-E X1
DDR2 CHANNEL A
PCI Express
100MHz
1GHz
DDR2 DIMM SLOT
PCI Express
HT clock
88E1116
1GHz
CPU clock
ITE 8716
200MHz
PCI-E X8
PCI-E X16
SATAII 2 PORTS
USB 10 PORTS
33MHz
PCI Express
PCI BUS
ALC888DD
88E1116
RGMII-2BUS
BIOS
PCI Express
HT LINK
HD signal
DDR2 DIMM SLOT
200MHz
RJ45
10 Date1120419 Dept
By Eddie
PS ON-IO_PSON-PWRBTSW
PW
RB
TS
W
SLP
_S3
PSIN
IT8716
nVIDIAVIDIA
MCP55P
5VSBSystem
On-Off
Button
5VSBrarr5VDUAL
3VDUAL
BATTERY
3VDUAL
RTC
VD
D
-RTC
RSTV
BA
T
32768KHZ
Pow
er O
n O
ff
Circ
uitry
SB
_PW
OK
ATXPower Supply
2500MHZ
VCC12DUAL
11 Date1120419 Dept
By Eddie
System Reset Map
IDE
PCI SLOT
PCIE_16_1
MCP55P
C51XEAMD K8
AM2
ATX
SB_PWOK
PWRGD
SLP_S3
HTMCP_PWRGD
HTMCP_RST
PS ON
PWOK
1394RST
MII_RST
ACZ_RST
PPCIRST_SLOT1
PPCIRST_SLOT2
HT_CPU_PWRGD
HT_CPU_RST
LPCRST_SIO LPCRST_FLASH
IDERST
PCIE_RST
IEEE 1394TSB43AB23
MARVELL88E1116
ALC888
ITE8716GBCX
DUALBIOS
PCIE_16_2
PCIE_8
PCIE_1
PCIE_2
MARVELL88E1116
12 Date1120419 Dept
By Eddie
ROM
AMD K8
AM2
C51XE
MCP55P
PCIRST
HT_VDD_EN
CPU_VDD_EN
SLP_S3
SLP_S5
LPC_PD
HT_VLD
CPU_VLD
MEM_VLD
SB_PWOK
CK8_PWOK
HT
_ST
OP
HT
_RE
Q
HT
_MC
P_P
WR
GD
HT
_MC
P_R
ST
HT
_MC
P_D
NH
T_M
CP
_U
P
HT
_CP
U_D
NH
T_C
PU
_U
P
HT
_CP
U_R
ST
HT
_CP
U_P
WR
GD
CP
U_C
LK
PRSNT
PERST
PE_REFCLK
CR
_R
EF
_C
LK
C51XEMCP55PXE Power Sequencing Block Diagram
13 Date1120419 Dept
By Eddie
GA-M59SLI-S5 System Clock
HT_CPU_TX_CLK[01]_NHT_CPU_RX_CLK[01]_P
CLKOUT 200MHZ_N
CLKIN 200MHZ_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_N
CLKOUT 200MHZ_P
CLKIN 200MHZ_N
HT_CPU_RX_CLK[01]_P
HT_CPU_TX_CLK[01]_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_P
HT_MCP_TX_CLK[01]_PHT_MCP_TX_CLK[01]_N
HT_MCP_TX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
CLKIN_25MHZ
CLKIN 200MHZ_PCLKIN 200MHZ_N
CLKOUT_25MHZCLKOUT 200MHZ_P
CLKOUT 200MHZ_N
HT_MCP_TX_CLK[01]_P
LPC_CLK1
HDA_BCLK
MA0_CLK[20]_N
MB0_CLK[20]_N
MA1_CLK[20]_NMA1_CLK[20]_P
MA0_CLK[20]_P
MB0_CLK[20]_P
MB1_CLK[20]_PMB1_CLK[20]_N
DIMM 0 MEM_B0
DIMM 0 MEM_B1
DIMM 0 MEM_A0
DIMM 0 MEM_A1
BUF_SIO_CLKLPC_CLK0
PCI_CLK0
PCI_CLK3PCI_CLK2PCI_CLK1
PCI_CLK4
PCI_CLKINPCI_CLK5
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PE1_REFCLK_N
PE2_REFCLK_N
PE2_REFCLK_P
PE1_REFCLK_P
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PEX X 8PE5_REFCLK_NPE5_REFCLK_P
PE1_REFCLK_PPE1_REFCLK_N PEX X 1
PE3_REFCLK_PPE3_REFCLK_N PEX X 1
PE2_REFCLK_NPE2_REFCLK_P
GIGABYTESATA 2
Super IO
PCICLK1
PCICLK2TPM
1394CLK
BIOSHDA
CODECXTALIN
XTALOUT
XTALIN_RTCXTALOUT_RTC
14 Date1120419 Dept
By Eddie
Power-Up Sequence
Core Planes include+12V Core+15V_PLL_HT +33V_PLL_HT+15V_PE_PLL_AVDD +15V_PE_PLL_DVDD +15V_PE_PLL_CORE+15V_PE_D +15V_PE_A +33V_PE_PLL_CORE+15V_SP_PLL_AVDD +15V_SP_PLL_DVDD +15V_SP_PLL_CORE+15V_SP_D +15V_SP_A +33V_SP_PLL_CORE+33V_PLL_CPU +33V_PLL_USB+33V +50V_CLAMP
15 Date1120419 Dept
By Eddie
AMD Socket 939 Architecture
16 Date1120419 Dept
By Eddie
AMD Socket 940 Architecture
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
3 Date1120419 Dept
By Eddie
nForce 550 Block Diagram
4 Date1120419 Dept
By Eddie
nForce 570 Ultra Block Diagram
5 Date1120419 Dept
By Eddie
nForce 570 SLI Block Diagram
6 Date1120419 Dept
By Eddie
nForce 590 Block Diagram
7 Date1120419 Dept
By Eddie
MCP55PXE Diagram
ATA 133
USB 20 EHCI USB 11 OHCI
NVIDIA MAC 1
High Definition Audio
Management Processor
PCI Bridge
LPC Bridge
ACPIPM SMBUS2010
RTC
Legacy
8259APCI82378254
Clock Synthesizer
LPC SuperIO
LPC Flash
SATA3 Gbs PHY
SATA3 Gbs PHY
SATA 3Gbs
SATA 3Gbs
SATA3 Gbs PHY
NVIDIA MAC 0
PCI Express
Controller 1
Controller 2
Controller 3
Controller 4
Controller 5
Controller 6
SerialPort
Hyper TransportInterface
SATA 3Gbs
PCI-33
LPC BUS
Serial ATA3 Gb s
Serial ATA3 Gb s
Serial ATA3 Gb s
RS232
PCI Express
2 Drives
10 Ports
RGMIIMII
RGMII
SMBus
HDA
Hyper Transport Link
NVIDIA SPP
Inte
rnal B
us
The NVIDIA MCP55PXE integrates the following features1048713 1 GHz HyperTransport x16 up and down links to the AMD Socket AM2 CPUs1048713 Six separate and independent PCI Express controllers and twenty eight PCI Express lanes1048713 Three separate SATA controllers each with integrated dual PHYs that are capable of operating at 15 Gbps and 30 Gbps speeds1048713 Fast ATA-133 IDE controller Support for a master device and a slave device1048713 NVIDIA MediaShieldtrade RAID with support for RAID 0 RAID 1 RAID 0+1 RAID 5 and JBOD1048713 Dual IEEE 8023 NVIDIA MACs for 1000BASE-T100BASE-T10BASE-T GigabitFast EthernetEthernet with TCP Offload Engine (TOE)1048713 RGMII for GigabitFast EthernetEthernet OR MII for Fast EthernetEthernet
1048713 IPMI 20 pass through support for remote management1048713 Integrated management processor with dedicated SMBUS and dedicated GPIOs1048713 USB 20 EHCI and USB 11 OHCI Supports up to ten ports1048713 PCI 23 interface Supports up to 5 PCI slots with dedicated REQGNT pairs1048713 Dual SMBus 20 interfaces1048713 UAA (Universal Audio Architecture) High Definition Audio interface1048713 Supports up to 3 external UAA High Definition Audio codecs for 71 channel audio1048713 Supports 32-bit 192 kHz audio functionality1048713 LPC bus 10 compatible interface1048713 Integrated AT legacy controllers1048713 Integrated clock synthesizer with spread spectrum capability1048713 Programmable active power management unit1048713 Integrated serial port1048713 AMD Socket AM2 CPUs power sequencing protection logic1048713 33 mm times 33 mm 1 mm ball pitch PBGA
8 Date1120419 Dept
By Eddie
C51XE Diagram
Hyper TransportInterface
Hyper TransportInterface
AMD Athlon 64Athlon 64 FX
Processors
PCI Expressx1 Root Port
PCI Expressx1 Root Port
PCI Expressx16 Root Port
ExternalPCI Express
Device
ExternalPCI Express
Device
ExternalPCI Express
Device
Hyper Transport Link 1 GHz
Hyper Transport Link 1 GHz
x1
x16
x1
MCP51XE
Inte
rnal B
us
IntegratedClock Synthesizer
Active PowerManagement
The NVIDIA C51XE includes the following features1048713 Primary HyperTransport link up to 10 GHz to the CPU1048713 Secondary HyperTransport link up to 10 GHz1048713 PCI Express 16 lane link interface for external graphics processors1048713 Dual PCI Express single lane link interface with dedicated controller for other peripherals1048713 Integrated power management processor1048713 Programmable clock synthesizer1048713 25 mm times 25 mm 10 mm ball pitch PBGA
9 Date1120419 Dept
By Eddie
GA-M59SLI-S5 BLOCK DIAGRAM
KBMS
FAN
DDR2 CHANNEL B
CKG
CKG
AUDIO
C51XE
IDE
RJ45
SUPER IO
GIGABYTE
33MHz
DUAL
RGMII-1BUS
FDD
100MHz
COM
SATAII 6 PORTS
PCI-E X16
TI1394a 3ports
MCP55XE
SATAII
100MHz
PCI SLOT
100MHz
LPC BUS
100MHz
AMD M2 Processor
33MHz
100MHz
PCI Express
DDR2 DIMM SLOT
PCI-E X1
HT LINK
DDR2 DIMM SLOT
PCI Express
PCI SLOT
PCI-E X1
DDR2 CHANNEL A
PCI Express
100MHz
1GHz
DDR2 DIMM SLOT
PCI Express
HT clock
88E1116
1GHz
CPU clock
ITE 8716
200MHz
PCI-E X8
PCI-E X16
SATAII 2 PORTS
USB 10 PORTS
33MHz
PCI Express
PCI BUS
ALC888DD
88E1116
RGMII-2BUS
BIOS
PCI Express
HT LINK
HD signal
DDR2 DIMM SLOT
200MHz
RJ45
10 Date1120419 Dept
By Eddie
PS ON-IO_PSON-PWRBTSW
PW
RB
TS
W
SLP
_S3
PSIN
IT8716
nVIDIAVIDIA
MCP55P
5VSBSystem
On-Off
Button
5VSBrarr5VDUAL
3VDUAL
BATTERY
3VDUAL
RTC
VD
D
-RTC
RSTV
BA
T
32768KHZ
Pow
er O
n O
ff
Circ
uitry
SB
_PW
OK
ATXPower Supply
2500MHZ
VCC12DUAL
11 Date1120419 Dept
By Eddie
System Reset Map
IDE
PCI SLOT
PCIE_16_1
MCP55P
C51XEAMD K8
AM2
ATX
SB_PWOK
PWRGD
SLP_S3
HTMCP_PWRGD
HTMCP_RST
PS ON
PWOK
1394RST
MII_RST
ACZ_RST
PPCIRST_SLOT1
PPCIRST_SLOT2
HT_CPU_PWRGD
HT_CPU_RST
LPCRST_SIO LPCRST_FLASH
IDERST
PCIE_RST
IEEE 1394TSB43AB23
MARVELL88E1116
ALC888
ITE8716GBCX
DUALBIOS
PCIE_16_2
PCIE_8
PCIE_1
PCIE_2
MARVELL88E1116
12 Date1120419 Dept
By Eddie
ROM
AMD K8
AM2
C51XE
MCP55P
PCIRST
HT_VDD_EN
CPU_VDD_EN
SLP_S3
SLP_S5
LPC_PD
HT_VLD
CPU_VLD
MEM_VLD
SB_PWOK
CK8_PWOK
HT
_ST
OP
HT
_RE
Q
HT
_MC
P_P
WR
GD
HT
_MC
P_R
ST
HT
_MC
P_D
NH
T_M
CP
_U
P
HT
_CP
U_D
NH
T_C
PU
_U
P
HT
_CP
U_R
ST
HT
_CP
U_P
WR
GD
CP
U_C
LK
PRSNT
PERST
PE_REFCLK
CR
_R
EF
_C
LK
C51XEMCP55PXE Power Sequencing Block Diagram
13 Date1120419 Dept
By Eddie
GA-M59SLI-S5 System Clock
HT_CPU_TX_CLK[01]_NHT_CPU_RX_CLK[01]_P
CLKOUT 200MHZ_N
CLKIN 200MHZ_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_N
CLKOUT 200MHZ_P
CLKIN 200MHZ_N
HT_CPU_RX_CLK[01]_P
HT_CPU_TX_CLK[01]_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_P
HT_MCP_TX_CLK[01]_PHT_MCP_TX_CLK[01]_N
HT_MCP_TX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
CLKIN_25MHZ
CLKIN 200MHZ_PCLKIN 200MHZ_N
CLKOUT_25MHZCLKOUT 200MHZ_P
CLKOUT 200MHZ_N
HT_MCP_TX_CLK[01]_P
LPC_CLK1
HDA_BCLK
MA0_CLK[20]_N
MB0_CLK[20]_N
MA1_CLK[20]_NMA1_CLK[20]_P
MA0_CLK[20]_P
MB0_CLK[20]_P
MB1_CLK[20]_PMB1_CLK[20]_N
DIMM 0 MEM_B0
DIMM 0 MEM_B1
DIMM 0 MEM_A0
DIMM 0 MEM_A1
BUF_SIO_CLKLPC_CLK0
PCI_CLK0
PCI_CLK3PCI_CLK2PCI_CLK1
PCI_CLK4
PCI_CLKINPCI_CLK5
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PE1_REFCLK_N
PE2_REFCLK_N
PE2_REFCLK_P
PE1_REFCLK_P
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PEX X 8PE5_REFCLK_NPE5_REFCLK_P
PE1_REFCLK_PPE1_REFCLK_N PEX X 1
PE3_REFCLK_PPE3_REFCLK_N PEX X 1
PE2_REFCLK_NPE2_REFCLK_P
GIGABYTESATA 2
Super IO
PCICLK1
PCICLK2TPM
1394CLK
BIOSHDA
CODECXTALIN
XTALOUT
XTALIN_RTCXTALOUT_RTC
14 Date1120419 Dept
By Eddie
Power-Up Sequence
Core Planes include+12V Core+15V_PLL_HT +33V_PLL_HT+15V_PE_PLL_AVDD +15V_PE_PLL_DVDD +15V_PE_PLL_CORE+15V_PE_D +15V_PE_A +33V_PE_PLL_CORE+15V_SP_PLL_AVDD +15V_SP_PLL_DVDD +15V_SP_PLL_CORE+15V_SP_D +15V_SP_A +33V_SP_PLL_CORE+33V_PLL_CPU +33V_PLL_USB+33V +50V_CLAMP
15 Date1120419 Dept
By Eddie
AMD Socket 939 Architecture
16 Date1120419 Dept
By Eddie
AMD Socket 940 Architecture
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
4 Date1120419 Dept
By Eddie
nForce 570 Ultra Block Diagram
5 Date1120419 Dept
By Eddie
nForce 570 SLI Block Diagram
6 Date1120419 Dept
By Eddie
nForce 590 Block Diagram
7 Date1120419 Dept
By Eddie
MCP55PXE Diagram
ATA 133
USB 20 EHCI USB 11 OHCI
NVIDIA MAC 1
High Definition Audio
Management Processor
PCI Bridge
LPC Bridge
ACPIPM SMBUS2010
RTC
Legacy
8259APCI82378254
Clock Synthesizer
LPC SuperIO
LPC Flash
SATA3 Gbs PHY
SATA3 Gbs PHY
SATA 3Gbs
SATA 3Gbs
SATA3 Gbs PHY
NVIDIA MAC 0
PCI Express
Controller 1
Controller 2
Controller 3
Controller 4
Controller 5
Controller 6
SerialPort
Hyper TransportInterface
SATA 3Gbs
PCI-33
LPC BUS
Serial ATA3 Gb s
Serial ATA3 Gb s
Serial ATA3 Gb s
RS232
PCI Express
2 Drives
10 Ports
RGMIIMII
RGMII
SMBus
HDA
Hyper Transport Link
NVIDIA SPP
Inte
rnal B
us
The NVIDIA MCP55PXE integrates the following features1048713 1 GHz HyperTransport x16 up and down links to the AMD Socket AM2 CPUs1048713 Six separate and independent PCI Express controllers and twenty eight PCI Express lanes1048713 Three separate SATA controllers each with integrated dual PHYs that are capable of operating at 15 Gbps and 30 Gbps speeds1048713 Fast ATA-133 IDE controller Support for a master device and a slave device1048713 NVIDIA MediaShieldtrade RAID with support for RAID 0 RAID 1 RAID 0+1 RAID 5 and JBOD1048713 Dual IEEE 8023 NVIDIA MACs for 1000BASE-T100BASE-T10BASE-T GigabitFast EthernetEthernet with TCP Offload Engine (TOE)1048713 RGMII for GigabitFast EthernetEthernet OR MII for Fast EthernetEthernet
1048713 IPMI 20 pass through support for remote management1048713 Integrated management processor with dedicated SMBUS and dedicated GPIOs1048713 USB 20 EHCI and USB 11 OHCI Supports up to ten ports1048713 PCI 23 interface Supports up to 5 PCI slots with dedicated REQGNT pairs1048713 Dual SMBus 20 interfaces1048713 UAA (Universal Audio Architecture) High Definition Audio interface1048713 Supports up to 3 external UAA High Definition Audio codecs for 71 channel audio1048713 Supports 32-bit 192 kHz audio functionality1048713 LPC bus 10 compatible interface1048713 Integrated AT legacy controllers1048713 Integrated clock synthesizer with spread spectrum capability1048713 Programmable active power management unit1048713 Integrated serial port1048713 AMD Socket AM2 CPUs power sequencing protection logic1048713 33 mm times 33 mm 1 mm ball pitch PBGA
8 Date1120419 Dept
By Eddie
C51XE Diagram
Hyper TransportInterface
Hyper TransportInterface
AMD Athlon 64Athlon 64 FX
Processors
PCI Expressx1 Root Port
PCI Expressx1 Root Port
PCI Expressx16 Root Port
ExternalPCI Express
Device
ExternalPCI Express
Device
ExternalPCI Express
Device
Hyper Transport Link 1 GHz
Hyper Transport Link 1 GHz
x1
x16
x1
MCP51XE
Inte
rnal B
us
IntegratedClock Synthesizer
Active PowerManagement
The NVIDIA C51XE includes the following features1048713 Primary HyperTransport link up to 10 GHz to the CPU1048713 Secondary HyperTransport link up to 10 GHz1048713 PCI Express 16 lane link interface for external graphics processors1048713 Dual PCI Express single lane link interface with dedicated controller for other peripherals1048713 Integrated power management processor1048713 Programmable clock synthesizer1048713 25 mm times 25 mm 10 mm ball pitch PBGA
9 Date1120419 Dept
By Eddie
GA-M59SLI-S5 BLOCK DIAGRAM
KBMS
FAN
DDR2 CHANNEL B
CKG
CKG
AUDIO
C51XE
IDE
RJ45
SUPER IO
GIGABYTE
33MHz
DUAL
RGMII-1BUS
FDD
100MHz
COM
SATAII 6 PORTS
PCI-E X16
TI1394a 3ports
MCP55XE
SATAII
100MHz
PCI SLOT
100MHz
LPC BUS
100MHz
AMD M2 Processor
33MHz
100MHz
PCI Express
DDR2 DIMM SLOT
PCI-E X1
HT LINK
DDR2 DIMM SLOT
PCI Express
PCI SLOT
PCI-E X1
DDR2 CHANNEL A
PCI Express
100MHz
1GHz
DDR2 DIMM SLOT
PCI Express
HT clock
88E1116
1GHz
CPU clock
ITE 8716
200MHz
PCI-E X8
PCI-E X16
SATAII 2 PORTS
USB 10 PORTS
33MHz
PCI Express
PCI BUS
ALC888DD
88E1116
RGMII-2BUS
BIOS
PCI Express
HT LINK
HD signal
DDR2 DIMM SLOT
200MHz
RJ45
10 Date1120419 Dept
By Eddie
PS ON-IO_PSON-PWRBTSW
PW
RB
TS
W
SLP
_S3
PSIN
IT8716
nVIDIAVIDIA
MCP55P
5VSBSystem
On-Off
Button
5VSBrarr5VDUAL
3VDUAL
BATTERY
3VDUAL
RTC
VD
D
-RTC
RSTV
BA
T
32768KHZ
Pow
er O
n O
ff
Circ
uitry
SB
_PW
OK
ATXPower Supply
2500MHZ
VCC12DUAL
11 Date1120419 Dept
By Eddie
System Reset Map
IDE
PCI SLOT
PCIE_16_1
MCP55P
C51XEAMD K8
AM2
ATX
SB_PWOK
PWRGD
SLP_S3
HTMCP_PWRGD
HTMCP_RST
PS ON
PWOK
1394RST
MII_RST
ACZ_RST
PPCIRST_SLOT1
PPCIRST_SLOT2
HT_CPU_PWRGD
HT_CPU_RST
LPCRST_SIO LPCRST_FLASH
IDERST
PCIE_RST
IEEE 1394TSB43AB23
MARVELL88E1116
ALC888
ITE8716GBCX
DUALBIOS
PCIE_16_2
PCIE_8
PCIE_1
PCIE_2
MARVELL88E1116
12 Date1120419 Dept
By Eddie
ROM
AMD K8
AM2
C51XE
MCP55P
PCIRST
HT_VDD_EN
CPU_VDD_EN
SLP_S3
SLP_S5
LPC_PD
HT_VLD
CPU_VLD
MEM_VLD
SB_PWOK
CK8_PWOK
HT
_ST
OP
HT
_RE
Q
HT
_MC
P_P
WR
GD
HT
_MC
P_R
ST
HT
_MC
P_D
NH
T_M
CP
_U
P
HT
_CP
U_D
NH
T_C
PU
_U
P
HT
_CP
U_R
ST
HT
_CP
U_P
WR
GD
CP
U_C
LK
PRSNT
PERST
PE_REFCLK
CR
_R
EF
_C
LK
C51XEMCP55PXE Power Sequencing Block Diagram
13 Date1120419 Dept
By Eddie
GA-M59SLI-S5 System Clock
HT_CPU_TX_CLK[01]_NHT_CPU_RX_CLK[01]_P
CLKOUT 200MHZ_N
CLKIN 200MHZ_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_N
CLKOUT 200MHZ_P
CLKIN 200MHZ_N
HT_CPU_RX_CLK[01]_P
HT_CPU_TX_CLK[01]_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_P
HT_MCP_TX_CLK[01]_PHT_MCP_TX_CLK[01]_N
HT_MCP_TX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
CLKIN_25MHZ
CLKIN 200MHZ_PCLKIN 200MHZ_N
CLKOUT_25MHZCLKOUT 200MHZ_P
CLKOUT 200MHZ_N
HT_MCP_TX_CLK[01]_P
LPC_CLK1
HDA_BCLK
MA0_CLK[20]_N
MB0_CLK[20]_N
MA1_CLK[20]_NMA1_CLK[20]_P
MA0_CLK[20]_P
MB0_CLK[20]_P
MB1_CLK[20]_PMB1_CLK[20]_N
DIMM 0 MEM_B0
DIMM 0 MEM_B1
DIMM 0 MEM_A0
DIMM 0 MEM_A1
BUF_SIO_CLKLPC_CLK0
PCI_CLK0
PCI_CLK3PCI_CLK2PCI_CLK1
PCI_CLK4
PCI_CLKINPCI_CLK5
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PE1_REFCLK_N
PE2_REFCLK_N
PE2_REFCLK_P
PE1_REFCLK_P
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PEX X 8PE5_REFCLK_NPE5_REFCLK_P
PE1_REFCLK_PPE1_REFCLK_N PEX X 1
PE3_REFCLK_PPE3_REFCLK_N PEX X 1
PE2_REFCLK_NPE2_REFCLK_P
GIGABYTESATA 2
Super IO
PCICLK1
PCICLK2TPM
1394CLK
BIOSHDA
CODECXTALIN
XTALOUT
XTALIN_RTCXTALOUT_RTC
14 Date1120419 Dept
By Eddie
Power-Up Sequence
Core Planes include+12V Core+15V_PLL_HT +33V_PLL_HT+15V_PE_PLL_AVDD +15V_PE_PLL_DVDD +15V_PE_PLL_CORE+15V_PE_D +15V_PE_A +33V_PE_PLL_CORE+15V_SP_PLL_AVDD +15V_SP_PLL_DVDD +15V_SP_PLL_CORE+15V_SP_D +15V_SP_A +33V_SP_PLL_CORE+33V_PLL_CPU +33V_PLL_USB+33V +50V_CLAMP
15 Date1120419 Dept
By Eddie
AMD Socket 939 Architecture
16 Date1120419 Dept
By Eddie
AMD Socket 940 Architecture
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
5 Date1120419 Dept
By Eddie
nForce 570 SLI Block Diagram
6 Date1120419 Dept
By Eddie
nForce 590 Block Diagram
7 Date1120419 Dept
By Eddie
MCP55PXE Diagram
ATA 133
USB 20 EHCI USB 11 OHCI
NVIDIA MAC 1
High Definition Audio
Management Processor
PCI Bridge
LPC Bridge
ACPIPM SMBUS2010
RTC
Legacy
8259APCI82378254
Clock Synthesizer
LPC SuperIO
LPC Flash
SATA3 Gbs PHY
SATA3 Gbs PHY
SATA 3Gbs
SATA 3Gbs
SATA3 Gbs PHY
NVIDIA MAC 0
PCI Express
Controller 1
Controller 2
Controller 3
Controller 4
Controller 5
Controller 6
SerialPort
Hyper TransportInterface
SATA 3Gbs
PCI-33
LPC BUS
Serial ATA3 Gb s
Serial ATA3 Gb s
Serial ATA3 Gb s
RS232
PCI Express
2 Drives
10 Ports
RGMIIMII
RGMII
SMBus
HDA
Hyper Transport Link
NVIDIA SPP
Inte
rnal B
us
The NVIDIA MCP55PXE integrates the following features1048713 1 GHz HyperTransport x16 up and down links to the AMD Socket AM2 CPUs1048713 Six separate and independent PCI Express controllers and twenty eight PCI Express lanes1048713 Three separate SATA controllers each with integrated dual PHYs that are capable of operating at 15 Gbps and 30 Gbps speeds1048713 Fast ATA-133 IDE controller Support for a master device and a slave device1048713 NVIDIA MediaShieldtrade RAID with support for RAID 0 RAID 1 RAID 0+1 RAID 5 and JBOD1048713 Dual IEEE 8023 NVIDIA MACs for 1000BASE-T100BASE-T10BASE-T GigabitFast EthernetEthernet with TCP Offload Engine (TOE)1048713 RGMII for GigabitFast EthernetEthernet OR MII for Fast EthernetEthernet
1048713 IPMI 20 pass through support for remote management1048713 Integrated management processor with dedicated SMBUS and dedicated GPIOs1048713 USB 20 EHCI and USB 11 OHCI Supports up to ten ports1048713 PCI 23 interface Supports up to 5 PCI slots with dedicated REQGNT pairs1048713 Dual SMBus 20 interfaces1048713 UAA (Universal Audio Architecture) High Definition Audio interface1048713 Supports up to 3 external UAA High Definition Audio codecs for 71 channel audio1048713 Supports 32-bit 192 kHz audio functionality1048713 LPC bus 10 compatible interface1048713 Integrated AT legacy controllers1048713 Integrated clock synthesizer with spread spectrum capability1048713 Programmable active power management unit1048713 Integrated serial port1048713 AMD Socket AM2 CPUs power sequencing protection logic1048713 33 mm times 33 mm 1 mm ball pitch PBGA
8 Date1120419 Dept
By Eddie
C51XE Diagram
Hyper TransportInterface
Hyper TransportInterface
AMD Athlon 64Athlon 64 FX
Processors
PCI Expressx1 Root Port
PCI Expressx1 Root Port
PCI Expressx16 Root Port
ExternalPCI Express
Device
ExternalPCI Express
Device
ExternalPCI Express
Device
Hyper Transport Link 1 GHz
Hyper Transport Link 1 GHz
x1
x16
x1
MCP51XE
Inte
rnal B
us
IntegratedClock Synthesizer
Active PowerManagement
The NVIDIA C51XE includes the following features1048713 Primary HyperTransport link up to 10 GHz to the CPU1048713 Secondary HyperTransport link up to 10 GHz1048713 PCI Express 16 lane link interface for external graphics processors1048713 Dual PCI Express single lane link interface with dedicated controller for other peripherals1048713 Integrated power management processor1048713 Programmable clock synthesizer1048713 25 mm times 25 mm 10 mm ball pitch PBGA
9 Date1120419 Dept
By Eddie
GA-M59SLI-S5 BLOCK DIAGRAM
KBMS
FAN
DDR2 CHANNEL B
CKG
CKG
AUDIO
C51XE
IDE
RJ45
SUPER IO
GIGABYTE
33MHz
DUAL
RGMII-1BUS
FDD
100MHz
COM
SATAII 6 PORTS
PCI-E X16
TI1394a 3ports
MCP55XE
SATAII
100MHz
PCI SLOT
100MHz
LPC BUS
100MHz
AMD M2 Processor
33MHz
100MHz
PCI Express
DDR2 DIMM SLOT
PCI-E X1
HT LINK
DDR2 DIMM SLOT
PCI Express
PCI SLOT
PCI-E X1
DDR2 CHANNEL A
PCI Express
100MHz
1GHz
DDR2 DIMM SLOT
PCI Express
HT clock
88E1116
1GHz
CPU clock
ITE 8716
200MHz
PCI-E X8
PCI-E X16
SATAII 2 PORTS
USB 10 PORTS
33MHz
PCI Express
PCI BUS
ALC888DD
88E1116
RGMII-2BUS
BIOS
PCI Express
HT LINK
HD signal
DDR2 DIMM SLOT
200MHz
RJ45
10 Date1120419 Dept
By Eddie
PS ON-IO_PSON-PWRBTSW
PW
RB
TS
W
SLP
_S3
PSIN
IT8716
nVIDIAVIDIA
MCP55P
5VSBSystem
On-Off
Button
5VSBrarr5VDUAL
3VDUAL
BATTERY
3VDUAL
RTC
VD
D
-RTC
RSTV
BA
T
32768KHZ
Pow
er O
n O
ff
Circ
uitry
SB
_PW
OK
ATXPower Supply
2500MHZ
VCC12DUAL
11 Date1120419 Dept
By Eddie
System Reset Map
IDE
PCI SLOT
PCIE_16_1
MCP55P
C51XEAMD K8
AM2
ATX
SB_PWOK
PWRGD
SLP_S3
HTMCP_PWRGD
HTMCP_RST
PS ON
PWOK
1394RST
MII_RST
ACZ_RST
PPCIRST_SLOT1
PPCIRST_SLOT2
HT_CPU_PWRGD
HT_CPU_RST
LPCRST_SIO LPCRST_FLASH
IDERST
PCIE_RST
IEEE 1394TSB43AB23
MARVELL88E1116
ALC888
ITE8716GBCX
DUALBIOS
PCIE_16_2
PCIE_8
PCIE_1
PCIE_2
MARVELL88E1116
12 Date1120419 Dept
By Eddie
ROM
AMD K8
AM2
C51XE
MCP55P
PCIRST
HT_VDD_EN
CPU_VDD_EN
SLP_S3
SLP_S5
LPC_PD
HT_VLD
CPU_VLD
MEM_VLD
SB_PWOK
CK8_PWOK
HT
_ST
OP
HT
_RE
Q
HT
_MC
P_P
WR
GD
HT
_MC
P_R
ST
HT
_MC
P_D
NH
T_M
CP
_U
P
HT
_CP
U_D
NH
T_C
PU
_U
P
HT
_CP
U_R
ST
HT
_CP
U_P
WR
GD
CP
U_C
LK
PRSNT
PERST
PE_REFCLK
CR
_R
EF
_C
LK
C51XEMCP55PXE Power Sequencing Block Diagram
13 Date1120419 Dept
By Eddie
GA-M59SLI-S5 System Clock
HT_CPU_TX_CLK[01]_NHT_CPU_RX_CLK[01]_P
CLKOUT 200MHZ_N
CLKIN 200MHZ_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_N
CLKOUT 200MHZ_P
CLKIN 200MHZ_N
HT_CPU_RX_CLK[01]_P
HT_CPU_TX_CLK[01]_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_P
HT_MCP_TX_CLK[01]_PHT_MCP_TX_CLK[01]_N
HT_MCP_TX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
CLKIN_25MHZ
CLKIN 200MHZ_PCLKIN 200MHZ_N
CLKOUT_25MHZCLKOUT 200MHZ_P
CLKOUT 200MHZ_N
HT_MCP_TX_CLK[01]_P
LPC_CLK1
HDA_BCLK
MA0_CLK[20]_N
MB0_CLK[20]_N
MA1_CLK[20]_NMA1_CLK[20]_P
MA0_CLK[20]_P
MB0_CLK[20]_P
MB1_CLK[20]_PMB1_CLK[20]_N
DIMM 0 MEM_B0
DIMM 0 MEM_B1
DIMM 0 MEM_A0
DIMM 0 MEM_A1
BUF_SIO_CLKLPC_CLK0
PCI_CLK0
PCI_CLK3PCI_CLK2PCI_CLK1
PCI_CLK4
PCI_CLKINPCI_CLK5
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PE1_REFCLK_N
PE2_REFCLK_N
PE2_REFCLK_P
PE1_REFCLK_P
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PEX X 8PE5_REFCLK_NPE5_REFCLK_P
PE1_REFCLK_PPE1_REFCLK_N PEX X 1
PE3_REFCLK_PPE3_REFCLK_N PEX X 1
PE2_REFCLK_NPE2_REFCLK_P
GIGABYTESATA 2
Super IO
PCICLK1
PCICLK2TPM
1394CLK
BIOSHDA
CODECXTALIN
XTALOUT
XTALIN_RTCXTALOUT_RTC
14 Date1120419 Dept
By Eddie
Power-Up Sequence
Core Planes include+12V Core+15V_PLL_HT +33V_PLL_HT+15V_PE_PLL_AVDD +15V_PE_PLL_DVDD +15V_PE_PLL_CORE+15V_PE_D +15V_PE_A +33V_PE_PLL_CORE+15V_SP_PLL_AVDD +15V_SP_PLL_DVDD +15V_SP_PLL_CORE+15V_SP_D +15V_SP_A +33V_SP_PLL_CORE+33V_PLL_CPU +33V_PLL_USB+33V +50V_CLAMP
15 Date1120419 Dept
By Eddie
AMD Socket 939 Architecture
16 Date1120419 Dept
By Eddie
AMD Socket 940 Architecture
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
6 Date1120419 Dept
By Eddie
nForce 590 Block Diagram
7 Date1120419 Dept
By Eddie
MCP55PXE Diagram
ATA 133
USB 20 EHCI USB 11 OHCI
NVIDIA MAC 1
High Definition Audio
Management Processor
PCI Bridge
LPC Bridge
ACPIPM SMBUS2010
RTC
Legacy
8259APCI82378254
Clock Synthesizer
LPC SuperIO
LPC Flash
SATA3 Gbs PHY
SATA3 Gbs PHY
SATA 3Gbs
SATA 3Gbs
SATA3 Gbs PHY
NVIDIA MAC 0
PCI Express
Controller 1
Controller 2
Controller 3
Controller 4
Controller 5
Controller 6
SerialPort
Hyper TransportInterface
SATA 3Gbs
PCI-33
LPC BUS
Serial ATA3 Gb s
Serial ATA3 Gb s
Serial ATA3 Gb s
RS232
PCI Express
2 Drives
10 Ports
RGMIIMII
RGMII
SMBus
HDA
Hyper Transport Link
NVIDIA SPP
Inte
rnal B
us
The NVIDIA MCP55PXE integrates the following features1048713 1 GHz HyperTransport x16 up and down links to the AMD Socket AM2 CPUs1048713 Six separate and independent PCI Express controllers and twenty eight PCI Express lanes1048713 Three separate SATA controllers each with integrated dual PHYs that are capable of operating at 15 Gbps and 30 Gbps speeds1048713 Fast ATA-133 IDE controller Support for a master device and a slave device1048713 NVIDIA MediaShieldtrade RAID with support for RAID 0 RAID 1 RAID 0+1 RAID 5 and JBOD1048713 Dual IEEE 8023 NVIDIA MACs for 1000BASE-T100BASE-T10BASE-T GigabitFast EthernetEthernet with TCP Offload Engine (TOE)1048713 RGMII for GigabitFast EthernetEthernet OR MII for Fast EthernetEthernet
1048713 IPMI 20 pass through support for remote management1048713 Integrated management processor with dedicated SMBUS and dedicated GPIOs1048713 USB 20 EHCI and USB 11 OHCI Supports up to ten ports1048713 PCI 23 interface Supports up to 5 PCI slots with dedicated REQGNT pairs1048713 Dual SMBus 20 interfaces1048713 UAA (Universal Audio Architecture) High Definition Audio interface1048713 Supports up to 3 external UAA High Definition Audio codecs for 71 channel audio1048713 Supports 32-bit 192 kHz audio functionality1048713 LPC bus 10 compatible interface1048713 Integrated AT legacy controllers1048713 Integrated clock synthesizer with spread spectrum capability1048713 Programmable active power management unit1048713 Integrated serial port1048713 AMD Socket AM2 CPUs power sequencing protection logic1048713 33 mm times 33 mm 1 mm ball pitch PBGA
8 Date1120419 Dept
By Eddie
C51XE Diagram
Hyper TransportInterface
Hyper TransportInterface
AMD Athlon 64Athlon 64 FX
Processors
PCI Expressx1 Root Port
PCI Expressx1 Root Port
PCI Expressx16 Root Port
ExternalPCI Express
Device
ExternalPCI Express
Device
ExternalPCI Express
Device
Hyper Transport Link 1 GHz
Hyper Transport Link 1 GHz
x1
x16
x1
MCP51XE
Inte
rnal B
us
IntegratedClock Synthesizer
Active PowerManagement
The NVIDIA C51XE includes the following features1048713 Primary HyperTransport link up to 10 GHz to the CPU1048713 Secondary HyperTransport link up to 10 GHz1048713 PCI Express 16 lane link interface for external graphics processors1048713 Dual PCI Express single lane link interface with dedicated controller for other peripherals1048713 Integrated power management processor1048713 Programmable clock synthesizer1048713 25 mm times 25 mm 10 mm ball pitch PBGA
9 Date1120419 Dept
By Eddie
GA-M59SLI-S5 BLOCK DIAGRAM
KBMS
FAN
DDR2 CHANNEL B
CKG
CKG
AUDIO
C51XE
IDE
RJ45
SUPER IO
GIGABYTE
33MHz
DUAL
RGMII-1BUS
FDD
100MHz
COM
SATAII 6 PORTS
PCI-E X16
TI1394a 3ports
MCP55XE
SATAII
100MHz
PCI SLOT
100MHz
LPC BUS
100MHz
AMD M2 Processor
33MHz
100MHz
PCI Express
DDR2 DIMM SLOT
PCI-E X1
HT LINK
DDR2 DIMM SLOT
PCI Express
PCI SLOT
PCI-E X1
DDR2 CHANNEL A
PCI Express
100MHz
1GHz
DDR2 DIMM SLOT
PCI Express
HT clock
88E1116
1GHz
CPU clock
ITE 8716
200MHz
PCI-E X8
PCI-E X16
SATAII 2 PORTS
USB 10 PORTS
33MHz
PCI Express
PCI BUS
ALC888DD
88E1116
RGMII-2BUS
BIOS
PCI Express
HT LINK
HD signal
DDR2 DIMM SLOT
200MHz
RJ45
10 Date1120419 Dept
By Eddie
PS ON-IO_PSON-PWRBTSW
PW
RB
TS
W
SLP
_S3
PSIN
IT8716
nVIDIAVIDIA
MCP55P
5VSBSystem
On-Off
Button
5VSBrarr5VDUAL
3VDUAL
BATTERY
3VDUAL
RTC
VD
D
-RTC
RSTV
BA
T
32768KHZ
Pow
er O
n O
ff
Circ
uitry
SB
_PW
OK
ATXPower Supply
2500MHZ
VCC12DUAL
11 Date1120419 Dept
By Eddie
System Reset Map
IDE
PCI SLOT
PCIE_16_1
MCP55P
C51XEAMD K8
AM2
ATX
SB_PWOK
PWRGD
SLP_S3
HTMCP_PWRGD
HTMCP_RST
PS ON
PWOK
1394RST
MII_RST
ACZ_RST
PPCIRST_SLOT1
PPCIRST_SLOT2
HT_CPU_PWRGD
HT_CPU_RST
LPCRST_SIO LPCRST_FLASH
IDERST
PCIE_RST
IEEE 1394TSB43AB23
MARVELL88E1116
ALC888
ITE8716GBCX
DUALBIOS
PCIE_16_2
PCIE_8
PCIE_1
PCIE_2
MARVELL88E1116
12 Date1120419 Dept
By Eddie
ROM
AMD K8
AM2
C51XE
MCP55P
PCIRST
HT_VDD_EN
CPU_VDD_EN
SLP_S3
SLP_S5
LPC_PD
HT_VLD
CPU_VLD
MEM_VLD
SB_PWOK
CK8_PWOK
HT
_ST
OP
HT
_RE
Q
HT
_MC
P_P
WR
GD
HT
_MC
P_R
ST
HT
_MC
P_D
NH
T_M
CP
_U
P
HT
_CP
U_D
NH
T_C
PU
_U
P
HT
_CP
U_R
ST
HT
_CP
U_P
WR
GD
CP
U_C
LK
PRSNT
PERST
PE_REFCLK
CR
_R
EF
_C
LK
C51XEMCP55PXE Power Sequencing Block Diagram
13 Date1120419 Dept
By Eddie
GA-M59SLI-S5 System Clock
HT_CPU_TX_CLK[01]_NHT_CPU_RX_CLK[01]_P
CLKOUT 200MHZ_N
CLKIN 200MHZ_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_N
CLKOUT 200MHZ_P
CLKIN 200MHZ_N
HT_CPU_RX_CLK[01]_P
HT_CPU_TX_CLK[01]_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_P
HT_MCP_TX_CLK[01]_PHT_MCP_TX_CLK[01]_N
HT_MCP_TX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
CLKIN_25MHZ
CLKIN 200MHZ_PCLKIN 200MHZ_N
CLKOUT_25MHZCLKOUT 200MHZ_P
CLKOUT 200MHZ_N
HT_MCP_TX_CLK[01]_P
LPC_CLK1
HDA_BCLK
MA0_CLK[20]_N
MB0_CLK[20]_N
MA1_CLK[20]_NMA1_CLK[20]_P
MA0_CLK[20]_P
MB0_CLK[20]_P
MB1_CLK[20]_PMB1_CLK[20]_N
DIMM 0 MEM_B0
DIMM 0 MEM_B1
DIMM 0 MEM_A0
DIMM 0 MEM_A1
BUF_SIO_CLKLPC_CLK0
PCI_CLK0
PCI_CLK3PCI_CLK2PCI_CLK1
PCI_CLK4
PCI_CLKINPCI_CLK5
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PE1_REFCLK_N
PE2_REFCLK_N
PE2_REFCLK_P
PE1_REFCLK_P
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PEX X 8PE5_REFCLK_NPE5_REFCLK_P
PE1_REFCLK_PPE1_REFCLK_N PEX X 1
PE3_REFCLK_PPE3_REFCLK_N PEX X 1
PE2_REFCLK_NPE2_REFCLK_P
GIGABYTESATA 2
Super IO
PCICLK1
PCICLK2TPM
1394CLK
BIOSHDA
CODECXTALIN
XTALOUT
XTALIN_RTCXTALOUT_RTC
14 Date1120419 Dept
By Eddie
Power-Up Sequence
Core Planes include+12V Core+15V_PLL_HT +33V_PLL_HT+15V_PE_PLL_AVDD +15V_PE_PLL_DVDD +15V_PE_PLL_CORE+15V_PE_D +15V_PE_A +33V_PE_PLL_CORE+15V_SP_PLL_AVDD +15V_SP_PLL_DVDD +15V_SP_PLL_CORE+15V_SP_D +15V_SP_A +33V_SP_PLL_CORE+33V_PLL_CPU +33V_PLL_USB+33V +50V_CLAMP
15 Date1120419 Dept
By Eddie
AMD Socket 939 Architecture
16 Date1120419 Dept
By Eddie
AMD Socket 940 Architecture
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
7 Date1120419 Dept
By Eddie
MCP55PXE Diagram
ATA 133
USB 20 EHCI USB 11 OHCI
NVIDIA MAC 1
High Definition Audio
Management Processor
PCI Bridge
LPC Bridge
ACPIPM SMBUS2010
RTC
Legacy
8259APCI82378254
Clock Synthesizer
LPC SuperIO
LPC Flash
SATA3 Gbs PHY
SATA3 Gbs PHY
SATA 3Gbs
SATA 3Gbs
SATA3 Gbs PHY
NVIDIA MAC 0
PCI Express
Controller 1
Controller 2
Controller 3
Controller 4
Controller 5
Controller 6
SerialPort
Hyper TransportInterface
SATA 3Gbs
PCI-33
LPC BUS
Serial ATA3 Gb s
Serial ATA3 Gb s
Serial ATA3 Gb s
RS232
PCI Express
2 Drives
10 Ports
RGMIIMII
RGMII
SMBus
HDA
Hyper Transport Link
NVIDIA SPP
Inte
rnal B
us
The NVIDIA MCP55PXE integrates the following features1048713 1 GHz HyperTransport x16 up and down links to the AMD Socket AM2 CPUs1048713 Six separate and independent PCI Express controllers and twenty eight PCI Express lanes1048713 Three separate SATA controllers each with integrated dual PHYs that are capable of operating at 15 Gbps and 30 Gbps speeds1048713 Fast ATA-133 IDE controller Support for a master device and a slave device1048713 NVIDIA MediaShieldtrade RAID with support for RAID 0 RAID 1 RAID 0+1 RAID 5 and JBOD1048713 Dual IEEE 8023 NVIDIA MACs for 1000BASE-T100BASE-T10BASE-T GigabitFast EthernetEthernet with TCP Offload Engine (TOE)1048713 RGMII for GigabitFast EthernetEthernet OR MII for Fast EthernetEthernet
1048713 IPMI 20 pass through support for remote management1048713 Integrated management processor with dedicated SMBUS and dedicated GPIOs1048713 USB 20 EHCI and USB 11 OHCI Supports up to ten ports1048713 PCI 23 interface Supports up to 5 PCI slots with dedicated REQGNT pairs1048713 Dual SMBus 20 interfaces1048713 UAA (Universal Audio Architecture) High Definition Audio interface1048713 Supports up to 3 external UAA High Definition Audio codecs for 71 channel audio1048713 Supports 32-bit 192 kHz audio functionality1048713 LPC bus 10 compatible interface1048713 Integrated AT legacy controllers1048713 Integrated clock synthesizer with spread spectrum capability1048713 Programmable active power management unit1048713 Integrated serial port1048713 AMD Socket AM2 CPUs power sequencing protection logic1048713 33 mm times 33 mm 1 mm ball pitch PBGA
8 Date1120419 Dept
By Eddie
C51XE Diagram
Hyper TransportInterface
Hyper TransportInterface
AMD Athlon 64Athlon 64 FX
Processors
PCI Expressx1 Root Port
PCI Expressx1 Root Port
PCI Expressx16 Root Port
ExternalPCI Express
Device
ExternalPCI Express
Device
ExternalPCI Express
Device
Hyper Transport Link 1 GHz
Hyper Transport Link 1 GHz
x1
x16
x1
MCP51XE
Inte
rnal B
us
IntegratedClock Synthesizer
Active PowerManagement
The NVIDIA C51XE includes the following features1048713 Primary HyperTransport link up to 10 GHz to the CPU1048713 Secondary HyperTransport link up to 10 GHz1048713 PCI Express 16 lane link interface for external graphics processors1048713 Dual PCI Express single lane link interface with dedicated controller for other peripherals1048713 Integrated power management processor1048713 Programmable clock synthesizer1048713 25 mm times 25 mm 10 mm ball pitch PBGA
9 Date1120419 Dept
By Eddie
GA-M59SLI-S5 BLOCK DIAGRAM
KBMS
FAN
DDR2 CHANNEL B
CKG
CKG
AUDIO
C51XE
IDE
RJ45
SUPER IO
GIGABYTE
33MHz
DUAL
RGMII-1BUS
FDD
100MHz
COM
SATAII 6 PORTS
PCI-E X16
TI1394a 3ports
MCP55XE
SATAII
100MHz
PCI SLOT
100MHz
LPC BUS
100MHz
AMD M2 Processor
33MHz
100MHz
PCI Express
DDR2 DIMM SLOT
PCI-E X1
HT LINK
DDR2 DIMM SLOT
PCI Express
PCI SLOT
PCI-E X1
DDR2 CHANNEL A
PCI Express
100MHz
1GHz
DDR2 DIMM SLOT
PCI Express
HT clock
88E1116
1GHz
CPU clock
ITE 8716
200MHz
PCI-E X8
PCI-E X16
SATAII 2 PORTS
USB 10 PORTS
33MHz
PCI Express
PCI BUS
ALC888DD
88E1116
RGMII-2BUS
BIOS
PCI Express
HT LINK
HD signal
DDR2 DIMM SLOT
200MHz
RJ45
10 Date1120419 Dept
By Eddie
PS ON-IO_PSON-PWRBTSW
PW
RB
TS
W
SLP
_S3
PSIN
IT8716
nVIDIAVIDIA
MCP55P
5VSBSystem
On-Off
Button
5VSBrarr5VDUAL
3VDUAL
BATTERY
3VDUAL
RTC
VD
D
-RTC
RSTV
BA
T
32768KHZ
Pow
er O
n O
ff
Circ
uitry
SB
_PW
OK
ATXPower Supply
2500MHZ
VCC12DUAL
11 Date1120419 Dept
By Eddie
System Reset Map
IDE
PCI SLOT
PCIE_16_1
MCP55P
C51XEAMD K8
AM2
ATX
SB_PWOK
PWRGD
SLP_S3
HTMCP_PWRGD
HTMCP_RST
PS ON
PWOK
1394RST
MII_RST
ACZ_RST
PPCIRST_SLOT1
PPCIRST_SLOT2
HT_CPU_PWRGD
HT_CPU_RST
LPCRST_SIO LPCRST_FLASH
IDERST
PCIE_RST
IEEE 1394TSB43AB23
MARVELL88E1116
ALC888
ITE8716GBCX
DUALBIOS
PCIE_16_2
PCIE_8
PCIE_1
PCIE_2
MARVELL88E1116
12 Date1120419 Dept
By Eddie
ROM
AMD K8
AM2
C51XE
MCP55P
PCIRST
HT_VDD_EN
CPU_VDD_EN
SLP_S3
SLP_S5
LPC_PD
HT_VLD
CPU_VLD
MEM_VLD
SB_PWOK
CK8_PWOK
HT
_ST
OP
HT
_RE
Q
HT
_MC
P_P
WR
GD
HT
_MC
P_R
ST
HT
_MC
P_D
NH
T_M
CP
_U
P
HT
_CP
U_D
NH
T_C
PU
_U
P
HT
_CP
U_R
ST
HT
_CP
U_P
WR
GD
CP
U_C
LK
PRSNT
PERST
PE_REFCLK
CR
_R
EF
_C
LK
C51XEMCP55PXE Power Sequencing Block Diagram
13 Date1120419 Dept
By Eddie
GA-M59SLI-S5 System Clock
HT_CPU_TX_CLK[01]_NHT_CPU_RX_CLK[01]_P
CLKOUT 200MHZ_N
CLKIN 200MHZ_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_N
CLKOUT 200MHZ_P
CLKIN 200MHZ_N
HT_CPU_RX_CLK[01]_P
HT_CPU_TX_CLK[01]_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_P
HT_MCP_TX_CLK[01]_PHT_MCP_TX_CLK[01]_N
HT_MCP_TX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
CLKIN_25MHZ
CLKIN 200MHZ_PCLKIN 200MHZ_N
CLKOUT_25MHZCLKOUT 200MHZ_P
CLKOUT 200MHZ_N
HT_MCP_TX_CLK[01]_P
LPC_CLK1
HDA_BCLK
MA0_CLK[20]_N
MB0_CLK[20]_N
MA1_CLK[20]_NMA1_CLK[20]_P
MA0_CLK[20]_P
MB0_CLK[20]_P
MB1_CLK[20]_PMB1_CLK[20]_N
DIMM 0 MEM_B0
DIMM 0 MEM_B1
DIMM 0 MEM_A0
DIMM 0 MEM_A1
BUF_SIO_CLKLPC_CLK0
PCI_CLK0
PCI_CLK3PCI_CLK2PCI_CLK1
PCI_CLK4
PCI_CLKINPCI_CLK5
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PE1_REFCLK_N
PE2_REFCLK_N
PE2_REFCLK_P
PE1_REFCLK_P
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PEX X 8PE5_REFCLK_NPE5_REFCLK_P
PE1_REFCLK_PPE1_REFCLK_N PEX X 1
PE3_REFCLK_PPE3_REFCLK_N PEX X 1
PE2_REFCLK_NPE2_REFCLK_P
GIGABYTESATA 2
Super IO
PCICLK1
PCICLK2TPM
1394CLK
BIOSHDA
CODECXTALIN
XTALOUT
XTALIN_RTCXTALOUT_RTC
14 Date1120419 Dept
By Eddie
Power-Up Sequence
Core Planes include+12V Core+15V_PLL_HT +33V_PLL_HT+15V_PE_PLL_AVDD +15V_PE_PLL_DVDD +15V_PE_PLL_CORE+15V_PE_D +15V_PE_A +33V_PE_PLL_CORE+15V_SP_PLL_AVDD +15V_SP_PLL_DVDD +15V_SP_PLL_CORE+15V_SP_D +15V_SP_A +33V_SP_PLL_CORE+33V_PLL_CPU +33V_PLL_USB+33V +50V_CLAMP
15 Date1120419 Dept
By Eddie
AMD Socket 939 Architecture
16 Date1120419 Dept
By Eddie
AMD Socket 940 Architecture
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
8 Date1120419 Dept
By Eddie
C51XE Diagram
Hyper TransportInterface
Hyper TransportInterface
AMD Athlon 64Athlon 64 FX
Processors
PCI Expressx1 Root Port
PCI Expressx1 Root Port
PCI Expressx16 Root Port
ExternalPCI Express
Device
ExternalPCI Express
Device
ExternalPCI Express
Device
Hyper Transport Link 1 GHz
Hyper Transport Link 1 GHz
x1
x16
x1
MCP51XE
Inte
rnal B
us
IntegratedClock Synthesizer
Active PowerManagement
The NVIDIA C51XE includes the following features1048713 Primary HyperTransport link up to 10 GHz to the CPU1048713 Secondary HyperTransport link up to 10 GHz1048713 PCI Express 16 lane link interface for external graphics processors1048713 Dual PCI Express single lane link interface with dedicated controller for other peripherals1048713 Integrated power management processor1048713 Programmable clock synthesizer1048713 25 mm times 25 mm 10 mm ball pitch PBGA
9 Date1120419 Dept
By Eddie
GA-M59SLI-S5 BLOCK DIAGRAM
KBMS
FAN
DDR2 CHANNEL B
CKG
CKG
AUDIO
C51XE
IDE
RJ45
SUPER IO
GIGABYTE
33MHz
DUAL
RGMII-1BUS
FDD
100MHz
COM
SATAII 6 PORTS
PCI-E X16
TI1394a 3ports
MCP55XE
SATAII
100MHz
PCI SLOT
100MHz
LPC BUS
100MHz
AMD M2 Processor
33MHz
100MHz
PCI Express
DDR2 DIMM SLOT
PCI-E X1
HT LINK
DDR2 DIMM SLOT
PCI Express
PCI SLOT
PCI-E X1
DDR2 CHANNEL A
PCI Express
100MHz
1GHz
DDR2 DIMM SLOT
PCI Express
HT clock
88E1116
1GHz
CPU clock
ITE 8716
200MHz
PCI-E X8
PCI-E X16
SATAII 2 PORTS
USB 10 PORTS
33MHz
PCI Express
PCI BUS
ALC888DD
88E1116
RGMII-2BUS
BIOS
PCI Express
HT LINK
HD signal
DDR2 DIMM SLOT
200MHz
RJ45
10 Date1120419 Dept
By Eddie
PS ON-IO_PSON-PWRBTSW
PW
RB
TS
W
SLP
_S3
PSIN
IT8716
nVIDIAVIDIA
MCP55P
5VSBSystem
On-Off
Button
5VSBrarr5VDUAL
3VDUAL
BATTERY
3VDUAL
RTC
VD
D
-RTC
RSTV
BA
T
32768KHZ
Pow
er O
n O
ff
Circ
uitry
SB
_PW
OK
ATXPower Supply
2500MHZ
VCC12DUAL
11 Date1120419 Dept
By Eddie
System Reset Map
IDE
PCI SLOT
PCIE_16_1
MCP55P
C51XEAMD K8
AM2
ATX
SB_PWOK
PWRGD
SLP_S3
HTMCP_PWRGD
HTMCP_RST
PS ON
PWOK
1394RST
MII_RST
ACZ_RST
PPCIRST_SLOT1
PPCIRST_SLOT2
HT_CPU_PWRGD
HT_CPU_RST
LPCRST_SIO LPCRST_FLASH
IDERST
PCIE_RST
IEEE 1394TSB43AB23
MARVELL88E1116
ALC888
ITE8716GBCX
DUALBIOS
PCIE_16_2
PCIE_8
PCIE_1
PCIE_2
MARVELL88E1116
12 Date1120419 Dept
By Eddie
ROM
AMD K8
AM2
C51XE
MCP55P
PCIRST
HT_VDD_EN
CPU_VDD_EN
SLP_S3
SLP_S5
LPC_PD
HT_VLD
CPU_VLD
MEM_VLD
SB_PWOK
CK8_PWOK
HT
_ST
OP
HT
_RE
Q
HT
_MC
P_P
WR
GD
HT
_MC
P_R
ST
HT
_MC
P_D
NH
T_M
CP
_U
P
HT
_CP
U_D
NH
T_C
PU
_U
P
HT
_CP
U_R
ST
HT
_CP
U_P
WR
GD
CP
U_C
LK
PRSNT
PERST
PE_REFCLK
CR
_R
EF
_C
LK
C51XEMCP55PXE Power Sequencing Block Diagram
13 Date1120419 Dept
By Eddie
GA-M59SLI-S5 System Clock
HT_CPU_TX_CLK[01]_NHT_CPU_RX_CLK[01]_P
CLKOUT 200MHZ_N
CLKIN 200MHZ_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_N
CLKOUT 200MHZ_P
CLKIN 200MHZ_N
HT_CPU_RX_CLK[01]_P
HT_CPU_TX_CLK[01]_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_P
HT_MCP_TX_CLK[01]_PHT_MCP_TX_CLK[01]_N
HT_MCP_TX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
CLKIN_25MHZ
CLKIN 200MHZ_PCLKIN 200MHZ_N
CLKOUT_25MHZCLKOUT 200MHZ_P
CLKOUT 200MHZ_N
HT_MCP_TX_CLK[01]_P
LPC_CLK1
HDA_BCLK
MA0_CLK[20]_N
MB0_CLK[20]_N
MA1_CLK[20]_NMA1_CLK[20]_P
MA0_CLK[20]_P
MB0_CLK[20]_P
MB1_CLK[20]_PMB1_CLK[20]_N
DIMM 0 MEM_B0
DIMM 0 MEM_B1
DIMM 0 MEM_A0
DIMM 0 MEM_A1
BUF_SIO_CLKLPC_CLK0
PCI_CLK0
PCI_CLK3PCI_CLK2PCI_CLK1
PCI_CLK4
PCI_CLKINPCI_CLK5
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PE1_REFCLK_N
PE2_REFCLK_N
PE2_REFCLK_P
PE1_REFCLK_P
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PEX X 8PE5_REFCLK_NPE5_REFCLK_P
PE1_REFCLK_PPE1_REFCLK_N PEX X 1
PE3_REFCLK_PPE3_REFCLK_N PEX X 1
PE2_REFCLK_NPE2_REFCLK_P
GIGABYTESATA 2
Super IO
PCICLK1
PCICLK2TPM
1394CLK
BIOSHDA
CODECXTALIN
XTALOUT
XTALIN_RTCXTALOUT_RTC
14 Date1120419 Dept
By Eddie
Power-Up Sequence
Core Planes include+12V Core+15V_PLL_HT +33V_PLL_HT+15V_PE_PLL_AVDD +15V_PE_PLL_DVDD +15V_PE_PLL_CORE+15V_PE_D +15V_PE_A +33V_PE_PLL_CORE+15V_SP_PLL_AVDD +15V_SP_PLL_DVDD +15V_SP_PLL_CORE+15V_SP_D +15V_SP_A +33V_SP_PLL_CORE+33V_PLL_CPU +33V_PLL_USB+33V +50V_CLAMP
15 Date1120419 Dept
By Eddie
AMD Socket 939 Architecture
16 Date1120419 Dept
By Eddie
AMD Socket 940 Architecture
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
9 Date1120419 Dept
By Eddie
GA-M59SLI-S5 BLOCK DIAGRAM
KBMS
FAN
DDR2 CHANNEL B
CKG
CKG
AUDIO
C51XE
IDE
RJ45
SUPER IO
GIGABYTE
33MHz
DUAL
RGMII-1BUS
FDD
100MHz
COM
SATAII 6 PORTS
PCI-E X16
TI1394a 3ports
MCP55XE
SATAII
100MHz
PCI SLOT
100MHz
LPC BUS
100MHz
AMD M2 Processor
33MHz
100MHz
PCI Express
DDR2 DIMM SLOT
PCI-E X1
HT LINK
DDR2 DIMM SLOT
PCI Express
PCI SLOT
PCI-E X1
DDR2 CHANNEL A
PCI Express
100MHz
1GHz
DDR2 DIMM SLOT
PCI Express
HT clock
88E1116
1GHz
CPU clock
ITE 8716
200MHz
PCI-E X8
PCI-E X16
SATAII 2 PORTS
USB 10 PORTS
33MHz
PCI Express
PCI BUS
ALC888DD
88E1116
RGMII-2BUS
BIOS
PCI Express
HT LINK
HD signal
DDR2 DIMM SLOT
200MHz
RJ45
10 Date1120419 Dept
By Eddie
PS ON-IO_PSON-PWRBTSW
PW
RB
TS
W
SLP
_S3
PSIN
IT8716
nVIDIAVIDIA
MCP55P
5VSBSystem
On-Off
Button
5VSBrarr5VDUAL
3VDUAL
BATTERY
3VDUAL
RTC
VD
D
-RTC
RSTV
BA
T
32768KHZ
Pow
er O
n O
ff
Circ
uitry
SB
_PW
OK
ATXPower Supply
2500MHZ
VCC12DUAL
11 Date1120419 Dept
By Eddie
System Reset Map
IDE
PCI SLOT
PCIE_16_1
MCP55P
C51XEAMD K8
AM2
ATX
SB_PWOK
PWRGD
SLP_S3
HTMCP_PWRGD
HTMCP_RST
PS ON
PWOK
1394RST
MII_RST
ACZ_RST
PPCIRST_SLOT1
PPCIRST_SLOT2
HT_CPU_PWRGD
HT_CPU_RST
LPCRST_SIO LPCRST_FLASH
IDERST
PCIE_RST
IEEE 1394TSB43AB23
MARVELL88E1116
ALC888
ITE8716GBCX
DUALBIOS
PCIE_16_2
PCIE_8
PCIE_1
PCIE_2
MARVELL88E1116
12 Date1120419 Dept
By Eddie
ROM
AMD K8
AM2
C51XE
MCP55P
PCIRST
HT_VDD_EN
CPU_VDD_EN
SLP_S3
SLP_S5
LPC_PD
HT_VLD
CPU_VLD
MEM_VLD
SB_PWOK
CK8_PWOK
HT
_ST
OP
HT
_RE
Q
HT
_MC
P_P
WR
GD
HT
_MC
P_R
ST
HT
_MC
P_D
NH
T_M
CP
_U
P
HT
_CP
U_D
NH
T_C
PU
_U
P
HT
_CP
U_R
ST
HT
_CP
U_P
WR
GD
CP
U_C
LK
PRSNT
PERST
PE_REFCLK
CR
_R
EF
_C
LK
C51XEMCP55PXE Power Sequencing Block Diagram
13 Date1120419 Dept
By Eddie
GA-M59SLI-S5 System Clock
HT_CPU_TX_CLK[01]_NHT_CPU_RX_CLK[01]_P
CLKOUT 200MHZ_N
CLKIN 200MHZ_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_N
CLKOUT 200MHZ_P
CLKIN 200MHZ_N
HT_CPU_RX_CLK[01]_P
HT_CPU_TX_CLK[01]_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_P
HT_MCP_TX_CLK[01]_PHT_MCP_TX_CLK[01]_N
HT_MCP_TX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
CLKIN_25MHZ
CLKIN 200MHZ_PCLKIN 200MHZ_N
CLKOUT_25MHZCLKOUT 200MHZ_P
CLKOUT 200MHZ_N
HT_MCP_TX_CLK[01]_P
LPC_CLK1
HDA_BCLK
MA0_CLK[20]_N
MB0_CLK[20]_N
MA1_CLK[20]_NMA1_CLK[20]_P
MA0_CLK[20]_P
MB0_CLK[20]_P
MB1_CLK[20]_PMB1_CLK[20]_N
DIMM 0 MEM_B0
DIMM 0 MEM_B1
DIMM 0 MEM_A0
DIMM 0 MEM_A1
BUF_SIO_CLKLPC_CLK0
PCI_CLK0
PCI_CLK3PCI_CLK2PCI_CLK1
PCI_CLK4
PCI_CLKINPCI_CLK5
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PE1_REFCLK_N
PE2_REFCLK_N
PE2_REFCLK_P
PE1_REFCLK_P
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PEX X 8PE5_REFCLK_NPE5_REFCLK_P
PE1_REFCLK_PPE1_REFCLK_N PEX X 1
PE3_REFCLK_PPE3_REFCLK_N PEX X 1
PE2_REFCLK_NPE2_REFCLK_P
GIGABYTESATA 2
Super IO
PCICLK1
PCICLK2TPM
1394CLK
BIOSHDA
CODECXTALIN
XTALOUT
XTALIN_RTCXTALOUT_RTC
14 Date1120419 Dept
By Eddie
Power-Up Sequence
Core Planes include+12V Core+15V_PLL_HT +33V_PLL_HT+15V_PE_PLL_AVDD +15V_PE_PLL_DVDD +15V_PE_PLL_CORE+15V_PE_D +15V_PE_A +33V_PE_PLL_CORE+15V_SP_PLL_AVDD +15V_SP_PLL_DVDD +15V_SP_PLL_CORE+15V_SP_D +15V_SP_A +33V_SP_PLL_CORE+33V_PLL_CPU +33V_PLL_USB+33V +50V_CLAMP
15 Date1120419 Dept
By Eddie
AMD Socket 939 Architecture
16 Date1120419 Dept
By Eddie
AMD Socket 940 Architecture
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
10 Date1120419 Dept
By Eddie
PS ON-IO_PSON-PWRBTSW
PW
RB
TS
W
SLP
_S3
PSIN
IT8716
nVIDIAVIDIA
MCP55P
5VSBSystem
On-Off
Button
5VSBrarr5VDUAL
3VDUAL
BATTERY
3VDUAL
RTC
VD
D
-RTC
RSTV
BA
T
32768KHZ
Pow
er O
n O
ff
Circ
uitry
SB
_PW
OK
ATXPower Supply
2500MHZ
VCC12DUAL
11 Date1120419 Dept
By Eddie
System Reset Map
IDE
PCI SLOT
PCIE_16_1
MCP55P
C51XEAMD K8
AM2
ATX
SB_PWOK
PWRGD
SLP_S3
HTMCP_PWRGD
HTMCP_RST
PS ON
PWOK
1394RST
MII_RST
ACZ_RST
PPCIRST_SLOT1
PPCIRST_SLOT2
HT_CPU_PWRGD
HT_CPU_RST
LPCRST_SIO LPCRST_FLASH
IDERST
PCIE_RST
IEEE 1394TSB43AB23
MARVELL88E1116
ALC888
ITE8716GBCX
DUALBIOS
PCIE_16_2
PCIE_8
PCIE_1
PCIE_2
MARVELL88E1116
12 Date1120419 Dept
By Eddie
ROM
AMD K8
AM2
C51XE
MCP55P
PCIRST
HT_VDD_EN
CPU_VDD_EN
SLP_S3
SLP_S5
LPC_PD
HT_VLD
CPU_VLD
MEM_VLD
SB_PWOK
CK8_PWOK
HT
_ST
OP
HT
_RE
Q
HT
_MC
P_P
WR
GD
HT
_MC
P_R
ST
HT
_MC
P_D
NH
T_M
CP
_U
P
HT
_CP
U_D
NH
T_C
PU
_U
P
HT
_CP
U_R
ST
HT
_CP
U_P
WR
GD
CP
U_C
LK
PRSNT
PERST
PE_REFCLK
CR
_R
EF
_C
LK
C51XEMCP55PXE Power Sequencing Block Diagram
13 Date1120419 Dept
By Eddie
GA-M59SLI-S5 System Clock
HT_CPU_TX_CLK[01]_NHT_CPU_RX_CLK[01]_P
CLKOUT 200MHZ_N
CLKIN 200MHZ_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_N
CLKOUT 200MHZ_P
CLKIN 200MHZ_N
HT_CPU_RX_CLK[01]_P
HT_CPU_TX_CLK[01]_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_P
HT_MCP_TX_CLK[01]_PHT_MCP_TX_CLK[01]_N
HT_MCP_TX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
CLKIN_25MHZ
CLKIN 200MHZ_PCLKIN 200MHZ_N
CLKOUT_25MHZCLKOUT 200MHZ_P
CLKOUT 200MHZ_N
HT_MCP_TX_CLK[01]_P
LPC_CLK1
HDA_BCLK
MA0_CLK[20]_N
MB0_CLK[20]_N
MA1_CLK[20]_NMA1_CLK[20]_P
MA0_CLK[20]_P
MB0_CLK[20]_P
MB1_CLK[20]_PMB1_CLK[20]_N
DIMM 0 MEM_B0
DIMM 0 MEM_B1
DIMM 0 MEM_A0
DIMM 0 MEM_A1
BUF_SIO_CLKLPC_CLK0
PCI_CLK0
PCI_CLK3PCI_CLK2PCI_CLK1
PCI_CLK4
PCI_CLKINPCI_CLK5
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PE1_REFCLK_N
PE2_REFCLK_N
PE2_REFCLK_P
PE1_REFCLK_P
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PEX X 8PE5_REFCLK_NPE5_REFCLK_P
PE1_REFCLK_PPE1_REFCLK_N PEX X 1
PE3_REFCLK_PPE3_REFCLK_N PEX X 1
PE2_REFCLK_NPE2_REFCLK_P
GIGABYTESATA 2
Super IO
PCICLK1
PCICLK2TPM
1394CLK
BIOSHDA
CODECXTALIN
XTALOUT
XTALIN_RTCXTALOUT_RTC
14 Date1120419 Dept
By Eddie
Power-Up Sequence
Core Planes include+12V Core+15V_PLL_HT +33V_PLL_HT+15V_PE_PLL_AVDD +15V_PE_PLL_DVDD +15V_PE_PLL_CORE+15V_PE_D +15V_PE_A +33V_PE_PLL_CORE+15V_SP_PLL_AVDD +15V_SP_PLL_DVDD +15V_SP_PLL_CORE+15V_SP_D +15V_SP_A +33V_SP_PLL_CORE+33V_PLL_CPU +33V_PLL_USB+33V +50V_CLAMP
15 Date1120419 Dept
By Eddie
AMD Socket 939 Architecture
16 Date1120419 Dept
By Eddie
AMD Socket 940 Architecture
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
11 Date1120419 Dept
By Eddie
System Reset Map
IDE
PCI SLOT
PCIE_16_1
MCP55P
C51XEAMD K8
AM2
ATX
SB_PWOK
PWRGD
SLP_S3
HTMCP_PWRGD
HTMCP_RST
PS ON
PWOK
1394RST
MII_RST
ACZ_RST
PPCIRST_SLOT1
PPCIRST_SLOT2
HT_CPU_PWRGD
HT_CPU_RST
LPCRST_SIO LPCRST_FLASH
IDERST
PCIE_RST
IEEE 1394TSB43AB23
MARVELL88E1116
ALC888
ITE8716GBCX
DUALBIOS
PCIE_16_2
PCIE_8
PCIE_1
PCIE_2
MARVELL88E1116
12 Date1120419 Dept
By Eddie
ROM
AMD K8
AM2
C51XE
MCP55P
PCIRST
HT_VDD_EN
CPU_VDD_EN
SLP_S3
SLP_S5
LPC_PD
HT_VLD
CPU_VLD
MEM_VLD
SB_PWOK
CK8_PWOK
HT
_ST
OP
HT
_RE
Q
HT
_MC
P_P
WR
GD
HT
_MC
P_R
ST
HT
_MC
P_D
NH
T_M
CP
_U
P
HT
_CP
U_D
NH
T_C
PU
_U
P
HT
_CP
U_R
ST
HT
_CP
U_P
WR
GD
CP
U_C
LK
PRSNT
PERST
PE_REFCLK
CR
_R
EF
_C
LK
C51XEMCP55PXE Power Sequencing Block Diagram
13 Date1120419 Dept
By Eddie
GA-M59SLI-S5 System Clock
HT_CPU_TX_CLK[01]_NHT_CPU_RX_CLK[01]_P
CLKOUT 200MHZ_N
CLKIN 200MHZ_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_N
CLKOUT 200MHZ_P
CLKIN 200MHZ_N
HT_CPU_RX_CLK[01]_P
HT_CPU_TX_CLK[01]_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_P
HT_MCP_TX_CLK[01]_PHT_MCP_TX_CLK[01]_N
HT_MCP_TX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
CLKIN_25MHZ
CLKIN 200MHZ_PCLKIN 200MHZ_N
CLKOUT_25MHZCLKOUT 200MHZ_P
CLKOUT 200MHZ_N
HT_MCP_TX_CLK[01]_P
LPC_CLK1
HDA_BCLK
MA0_CLK[20]_N
MB0_CLK[20]_N
MA1_CLK[20]_NMA1_CLK[20]_P
MA0_CLK[20]_P
MB0_CLK[20]_P
MB1_CLK[20]_PMB1_CLK[20]_N
DIMM 0 MEM_B0
DIMM 0 MEM_B1
DIMM 0 MEM_A0
DIMM 0 MEM_A1
BUF_SIO_CLKLPC_CLK0
PCI_CLK0
PCI_CLK3PCI_CLK2PCI_CLK1
PCI_CLK4
PCI_CLKINPCI_CLK5
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PE1_REFCLK_N
PE2_REFCLK_N
PE2_REFCLK_P
PE1_REFCLK_P
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PEX X 8PE5_REFCLK_NPE5_REFCLK_P
PE1_REFCLK_PPE1_REFCLK_N PEX X 1
PE3_REFCLK_PPE3_REFCLK_N PEX X 1
PE2_REFCLK_NPE2_REFCLK_P
GIGABYTESATA 2
Super IO
PCICLK1
PCICLK2TPM
1394CLK
BIOSHDA
CODECXTALIN
XTALOUT
XTALIN_RTCXTALOUT_RTC
14 Date1120419 Dept
By Eddie
Power-Up Sequence
Core Planes include+12V Core+15V_PLL_HT +33V_PLL_HT+15V_PE_PLL_AVDD +15V_PE_PLL_DVDD +15V_PE_PLL_CORE+15V_PE_D +15V_PE_A +33V_PE_PLL_CORE+15V_SP_PLL_AVDD +15V_SP_PLL_DVDD +15V_SP_PLL_CORE+15V_SP_D +15V_SP_A +33V_SP_PLL_CORE+33V_PLL_CPU +33V_PLL_USB+33V +50V_CLAMP
15 Date1120419 Dept
By Eddie
AMD Socket 939 Architecture
16 Date1120419 Dept
By Eddie
AMD Socket 940 Architecture
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
12 Date1120419 Dept
By Eddie
ROM
AMD K8
AM2
C51XE
MCP55P
PCIRST
HT_VDD_EN
CPU_VDD_EN
SLP_S3
SLP_S5
LPC_PD
HT_VLD
CPU_VLD
MEM_VLD
SB_PWOK
CK8_PWOK
HT
_ST
OP
HT
_RE
Q
HT
_MC
P_P
WR
GD
HT
_MC
P_R
ST
HT
_MC
P_D
NH
T_M
CP
_U
P
HT
_CP
U_D
NH
T_C
PU
_U
P
HT
_CP
U_R
ST
HT
_CP
U_P
WR
GD
CP
U_C
LK
PRSNT
PERST
PE_REFCLK
CR
_R
EF
_C
LK
C51XEMCP55PXE Power Sequencing Block Diagram
13 Date1120419 Dept
By Eddie
GA-M59SLI-S5 System Clock
HT_CPU_TX_CLK[01]_NHT_CPU_RX_CLK[01]_P
CLKOUT 200MHZ_N
CLKIN 200MHZ_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_N
CLKOUT 200MHZ_P
CLKIN 200MHZ_N
HT_CPU_RX_CLK[01]_P
HT_CPU_TX_CLK[01]_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_P
HT_MCP_TX_CLK[01]_PHT_MCP_TX_CLK[01]_N
HT_MCP_TX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
CLKIN_25MHZ
CLKIN 200MHZ_PCLKIN 200MHZ_N
CLKOUT_25MHZCLKOUT 200MHZ_P
CLKOUT 200MHZ_N
HT_MCP_TX_CLK[01]_P
LPC_CLK1
HDA_BCLK
MA0_CLK[20]_N
MB0_CLK[20]_N
MA1_CLK[20]_NMA1_CLK[20]_P
MA0_CLK[20]_P
MB0_CLK[20]_P
MB1_CLK[20]_PMB1_CLK[20]_N
DIMM 0 MEM_B0
DIMM 0 MEM_B1
DIMM 0 MEM_A0
DIMM 0 MEM_A1
BUF_SIO_CLKLPC_CLK0
PCI_CLK0
PCI_CLK3PCI_CLK2PCI_CLK1
PCI_CLK4
PCI_CLKINPCI_CLK5
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PE1_REFCLK_N
PE2_REFCLK_N
PE2_REFCLK_P
PE1_REFCLK_P
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PEX X 8PE5_REFCLK_NPE5_REFCLK_P
PE1_REFCLK_PPE1_REFCLK_N PEX X 1
PE3_REFCLK_PPE3_REFCLK_N PEX X 1
PE2_REFCLK_NPE2_REFCLK_P
GIGABYTESATA 2
Super IO
PCICLK1
PCICLK2TPM
1394CLK
BIOSHDA
CODECXTALIN
XTALOUT
XTALIN_RTCXTALOUT_RTC
14 Date1120419 Dept
By Eddie
Power-Up Sequence
Core Planes include+12V Core+15V_PLL_HT +33V_PLL_HT+15V_PE_PLL_AVDD +15V_PE_PLL_DVDD +15V_PE_PLL_CORE+15V_PE_D +15V_PE_A +33V_PE_PLL_CORE+15V_SP_PLL_AVDD +15V_SP_PLL_DVDD +15V_SP_PLL_CORE+15V_SP_D +15V_SP_A +33V_SP_PLL_CORE+33V_PLL_CPU +33V_PLL_USB+33V +50V_CLAMP
15 Date1120419 Dept
By Eddie
AMD Socket 939 Architecture
16 Date1120419 Dept
By Eddie
AMD Socket 940 Architecture
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
13 Date1120419 Dept
By Eddie
GA-M59SLI-S5 System Clock
HT_CPU_TX_CLK[01]_NHT_CPU_RX_CLK[01]_P
CLKOUT 200MHZ_N
CLKIN 200MHZ_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_N
CLKOUT 200MHZ_P
CLKIN 200MHZ_N
HT_CPU_RX_CLK[01]_P
HT_CPU_TX_CLK[01]_P
HT_CPU_RX_CLK[01]_N
HT_CPU_TX_CLK[01]_P
HT_MCP_TX_CLK[01]_PHT_MCP_TX_CLK[01]_N
HT_MCP_TX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_N
HT_MCP_RX_CLK[01]_P
CLKIN_25MHZ
CLKIN 200MHZ_PCLKIN 200MHZ_N
CLKOUT_25MHZCLKOUT 200MHZ_P
CLKOUT 200MHZ_N
HT_MCP_TX_CLK[01]_P
LPC_CLK1
HDA_BCLK
MA0_CLK[20]_N
MB0_CLK[20]_N
MA1_CLK[20]_NMA1_CLK[20]_P
MA0_CLK[20]_P
MB0_CLK[20]_P
MB1_CLK[20]_PMB1_CLK[20]_N
DIMM 0 MEM_B0
DIMM 0 MEM_B1
DIMM 0 MEM_A0
DIMM 0 MEM_A1
BUF_SIO_CLKLPC_CLK0
PCI_CLK0
PCI_CLK3PCI_CLK2PCI_CLK1
PCI_CLK4
PCI_CLKINPCI_CLK5
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PE1_REFCLK_N
PE2_REFCLK_N
PE2_REFCLK_P
PE1_REFCLK_P
PE0_REFCLK_NPE0_REFCLK_P
PEX X 16
PEX X 8PE5_REFCLK_NPE5_REFCLK_P
PE1_REFCLK_PPE1_REFCLK_N PEX X 1
PE3_REFCLK_PPE3_REFCLK_N PEX X 1
PE2_REFCLK_NPE2_REFCLK_P
GIGABYTESATA 2
Super IO
PCICLK1
PCICLK2TPM
1394CLK
BIOSHDA
CODECXTALIN
XTALOUT
XTALIN_RTCXTALOUT_RTC
14 Date1120419 Dept
By Eddie
Power-Up Sequence
Core Planes include+12V Core+15V_PLL_HT +33V_PLL_HT+15V_PE_PLL_AVDD +15V_PE_PLL_DVDD +15V_PE_PLL_CORE+15V_PE_D +15V_PE_A +33V_PE_PLL_CORE+15V_SP_PLL_AVDD +15V_SP_PLL_DVDD +15V_SP_PLL_CORE+15V_SP_D +15V_SP_A +33V_SP_PLL_CORE+33V_PLL_CPU +33V_PLL_USB+33V +50V_CLAMP
15 Date1120419 Dept
By Eddie
AMD Socket 939 Architecture
16 Date1120419 Dept
By Eddie
AMD Socket 940 Architecture
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
14 Date1120419 Dept
By Eddie
Power-Up Sequence
Core Planes include+12V Core+15V_PLL_HT +33V_PLL_HT+15V_PE_PLL_AVDD +15V_PE_PLL_DVDD +15V_PE_PLL_CORE+15V_PE_D +15V_PE_A +33V_PE_PLL_CORE+15V_SP_PLL_AVDD +15V_SP_PLL_DVDD +15V_SP_PLL_CORE+15V_SP_D +15V_SP_A +33V_SP_PLL_CORE+33V_PLL_CPU +33V_PLL_USB+33V +50V_CLAMP
15 Date1120419 Dept
By Eddie
AMD Socket 939 Architecture
16 Date1120419 Dept
By Eddie
AMD Socket 940 Architecture
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
15 Date1120419 Dept
By Eddie
AMD Socket 939 Architecture
16 Date1120419 Dept
By Eddie
AMD Socket 940 Architecture
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
16 Date1120419 Dept
By Eddie
AMD Socket 940 Architecture
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
17 Date1120419 Dept
By Eddie
L0_CADOUT_L11
L0_CLKOUT_L1
L0_CADIN_H14
L0_CADIN_H0
L0_CADOUT_H7
L0_CADIN_H13
L0_CADIN_L1
L0_CADOUT_L12
L0_CADOUT_L3
L0_CADIN_L0
TP26149941R1942
L0_CADIN_L9
L0_CADOUT_L0
L0_CADOUT_H8
L0_CADIN_H1
VCC12_HT
L0_CADOUT_H12
L0_CLKIN_H0
L0_CTLIN_H011
L0_CADIN_L4
L0_CADOUT_H1
L0_CTLOUT_L0 11
L0_CADIN_L13
L0_CADIN_H5
L0_CADOUT_L8
L0_CADOUT_H6
L0_CADIN_H4
L0_CADIN_L12
L0_CADIN_L10
L0_CADIN_H6
L0_CADOUT_L13
L0_CLKIN_L1
L0_CADOUT_H15
HYPERTRANSPORT
SOCKET_M2A
CPU-SK940AM2S15u
N6P6N3N2
V4V5U1V1
U6V6T4T5
R6T6P4P5M4M5L6
M6K4K5J6K6
U3U2R1T1
R3R2N1P1L1
M1L3L2J1K1J3J2
Y1W1AA2AA3AB1AA1AC2AC3AE2AE3AF1AE1AG2AG3AH1AG1
Y5Y4AB6AA6AB5AB4AD6AC6AF6AE6AF5AF4AH6AG6AH5AH4
Y6W6W2W3
AD5AD4AD1AC1
L0_CLKIN_H(1)L0_CLKIN_L(1)L0_CLKIN_H(0)L0_CLKIN_L(0)
L0_CTLIN_H(1)L0_CTLIN_L(1)L0_CTLIN_H(0)L0_CTLIN_L(0)
L0_CADIN_H(15)L0_CADIN_L(15)L0_CADIN_H(14)L0_CADIN_L(14)L0_CADIN_H(13)L0_CADIN_L(13)L0_CADIN_H(12)L0_CADIN_L(12)L0_CADIN_H(11)L0_CADIN_L(11)L0_CADIN_H(10)L0_CADIN_L(10)L0_CADIN_H(9)L0_CADIN_L(9)L0_CADIN_H(8)L0_CADIN_L(8)
L0_CADIN_H(7)L0_CADIN_L(7)L0_CADIN_H(6)L0_CADIN_L(6)L0_CADIN_H(5)L0_CADIN_L(5)L0_CADIN_H(4)L0_CADIN_L(4)L0_CADIN_H(3)L0_CADIN_L(3)L0_CADIN_H(2)L0_CADIN_L(2)L0_CADIN_H(1)L0_CADIN_L(1)L0_CADIN_H(0)L0_CADIN_L(0)
L0_CADOUT_H(7)L0_CADOUT_L(7)
L0_CADOUT_H(6)L0_CADOUT_L(6)
L0_CADOUT_H(5)L0_CADOUT_L(5)
L0_CADOUT_H(4)L0_CADOUT_L(4)
L0_CADOUT_H(3)L0_CADOUT_L(3)
L0_CADOUT_H(2)L0_CADOUT_L(2)
L0_CADOUT_H(1)L0_CADOUT_L(1)
L0_CADOUT_H(0)L0_CADOUT_L(0)
L0_CADOUT_H(15)L0_CADOUT_L(15)
L0_CADOUT_H(14)L0_CADOUT_L(14)
L0_CADOUT_H(13)L0_CADOUT_L(13)
L0_CADOUT_H(12)L0_CADOUT_L(12)
L0_CADOUT_H(11)L0_CADOUT_L(11)
L0_CADOUT_H(10)L0_CADOUT_L(10)L0_CADOUT_H(9)L0_CADOUT_L(9)
L0_CADOUT_H(8)L0_CADOUT_L(8)
L0_CTLOUT_H(1)L0_CTLOUT_L(1)
L0_CTLOUT_H(0)L0_CTLOUT_L(0)
L0_CLKOUT_H(1)L0_CLKOUT_L(1)
L0_CLKOUT_H(0)L0_CLKOUT_L(0)
L0_CLKIN_L0
TP251
L0_CADOUT_H3
L0_CADOUT_H4
L0_CLKOUT_H0
L0_CADIN_H7
L0_CADOUT_L5
49941R1941
L0_CADIN_H9
L0_CADIN_H15
L0_CADOUT_L4L0_CADIN_H3
L0_CADIN_H10
L0_CTLIN_L0
L0_CADIN_L11
L0_CADIN_L3
L0_CADOUT_H10
L0_CADOUT_H9
L0_CLKIN_H1
L0_CADOUT_L6
L0_CLKOUT_L0
L0_CADOUT_L15
L0_CADIN_L8
L0_CADOUT_L10
L0_CADOUT_H0
L0_CADIN_H12
L0_CADOUT_L1
GND
L0_CADIN_H11
L0_CADIN_L2
L0_CTLOUT_H0
L0_CADIN_L5
L0_CADIN_L15
L0_CADOUT_L2
L0_CADOUT_H14
L0_CLKOUT_H1
L0_CADOUT_L9
L0_CADOUT_L14
L0_CADOUT_H11
L0_CADIN_H8
L0_CADOUT_H2
L0_CADIN_L14
L0_CTLIN_H0
L0_CADIN_H2
L0_CADOUT_L7L0_CADIN_L7
L0_CTLIN_L011
L0_CADOUT_H5
L0_CADOUT_H13
L0_CADIN_L6
L0_CTLOUT_H0 11L0_CTLOUT_L0
CPU HYPER TRANSPORT INTERFACE
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
18 Date1120419 Dept
By Eddie
Hyper Transport Link Interconnect
HT_RXCAD[158]_PHT_RXCAD[158]_L
HT_RXCLK1_P
HT_RXCLK1_N
VCC12_HT
HT_TXCTL_P
HT_TXCTL_N
HT_TXCAD[70]_P
HT_TXCAD[70]_L
HT_TXCLK0_P
HT_TXCLK0_L
HT_TXCAD[158]_P
HT_TXCAD[158]_L
HT_TXCLK1_P
HT_TXCLK1_L
HT_RXCTL_P
HT_RXCTL_N
CTLOUT0_H
CTLOUT0_L
HT_RXCAD[70]_P
HT_RXCAD[70]_L
HT_RXCLK0_P
HT_RXCLK0_L
CADOUT(70)_H
CADOUT(70)_L
CLKOUT0_H
CLKOUT0_L
CTLOUT1_H
CTLOUT1_L
CADOUT(158)_H
CADOUT(158)_L
CLKOUT1_H
CLKOUT1_L
CTLIN0_H
CTLIN0_L
CADIN(70)_H
CADIN(70)_L
CLKIN0_H
CLKIN0_L
CADIN(158)_H
CADIN(158)_L
CLKIN1_H
CLKIN1_L
AMD CPU
GND
LDTRST_L (-CPURST)
PWROK (CPU_PWRGD)
LDTSTOP_L (HTSTOP_L)
Signal Name Type Description
L0_CLKIN_HL[10] I- HT Link 0 Clock Input
L0_CTLIN_HL[10] I- HT Link 0 Control Input
L0_CADIN_HL[150] I- HT Link 0 CommandAddressData Input
L0_CLKOUT_HL[10] O- HT Link 0 Clock Outputs
L0_CTLOUT_HL[10] O- HT Link 0 Control Output
L0_CADOUT_HL[150] O- HT Link 0 CommandAddressData Outputs
L0_REF1 A Compensation Resistor to VLDT
L0_REF0 A Compensation Resistor to VSS
NotesT he unused L0_CTLIN_HL[1] pins must be properly terminated such that the true pin is pulledHigh and the complement is pulled Low
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
19 Date1120419 Dept
By Eddie
Memory Interface Channel A
-DCLKA4910
-DQSA3
-DCLKA1810
MDA16
DQSA3
DCLKA3910
MDA5
MEMORY INTERFACE A
SOCKET_M2B
CPU-SK940AM2S15u
AG21AG20
G19H19U27U26
AC25AA24
AC28
AE20AE19
G20G21V27
W27
AD27AA25
AC27
AB25AB27AA26
N25Y27
AA27
L27M25
M27N24
AC26N26P25Y25N27R24P27R25R26R27T25
U25T27
W24
AD15AE15AG18AG19AG24AG25AG27AG28
D29C29C25D25E19F19F15G15
AF15AF19AJ25
AH29B29E24E18H15
J28J27
J25
K25J26G28G27L24K27H29H27
AE14AG14AG16AD17AD13AE13AG15AE16AG17AE18AD21AG22AE17AF17AF21AE21AF23AE23AJ26AG26AE22AG23AH25AF25AJ28AJ29AF29AE26AJ27AH27AG29AF27E29E28D27C27G26F27C28E27F25E25E23D23E26C26G23F23E22E21F17G17G22F21G18E17G16E15G13H13H17E16E14G14
MA0_CLK_H(2)MA0_CLK_L(2)MA0_CLK_H(1)MA0_CLK_L(1)MA0_CLK_H(0)MA0_CLK_L(0)
MA0_CS_L(1)MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)MA1_CLK_L(2)MA1_CLK_H(1)MA1_CLK_L(1)MA1_CLK_H(0)MA1_CLK_L(0)
MA1_CS_L(1)MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_LMA_WE_LMA_RAS_L
MA_BANK(2)MA_BANK(1)MA_BANK(0)
MA_CKE(1)MA_CKE(0)
MA_ADD(15)MA_ADD(14)MA_ADD(13)MA_ADD(12)MA_ADD(11)MA_ADD(10)MA_ADD(9)MA_ADD(8)MA_ADD(7)MA_ADD(6)MA_ADD(5)MA_ADD(4)MA_ADD(3)MA_ADD(2)MA_ADD(1)MA_ADD(0)
MA_DQS_H(7)MA_DQS_L(7)MA_DQS_H(6)MA_DQS_L(6)MA_DQS_H(5)MA_DQS_L(5)MA_DQS_H(4)MA_DQS_L(4)MA_DQS_H(3)MA_DQS_L(3)MA_DQS_H(2)MA_DQS_L(2)MA_DQS_H(1)MA_DQS_L(1)MA_DQS_H(0)MA_DQS_L(0)
MA_DM(7)MA_DM(6)MA_DM(5)MA_DM(4)MA_DM(3)MA_DM(2)MA_DM(1)MA_DM(0)
MA_DQS_H(8)MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)MA_CHECK(6)MA_CHECK(5)MA_CHECK(4)MA_CHECK(3)MA_CHECK(2)MA_CHECK(1)MA_CHECK(0)
MA_DATA(63)MA_DATA(62)MA_DATA(61)MA_DATA(60)MA_DATA(59)MA_DATA(58)MA_DATA(57)MA_DATA(56)MA_DATA(55)MA_DATA(54)MA_DATA(53)MA_DATA(52)MA_DATA(51)MA_DATA(50)MA_DATA(49)MA_DATA(48)MA_DATA(47)MA_DATA(46)MA_DATA(45)MA_DATA(44)MA_DATA(43)MA_DATA(42)MA_DATA(41)MA_DATA(40)MA_DATA(39)MA_DATA(38)MA_DATA(37)MA_DATA(36)MA_DATA(35)MA_DATA(34)MA_DATA(33)MA_DATA(32)MA_DATA(31)MA_DATA(30)MA_DATA(29)MA_DATA(28)MA_DATA(27)MA_DATA(26)MA_DATA(25)MA_DATA(24)MA_DATA(23)MA_DATA(22)MA_DATA(21)MA_DATA(20)MA_DATA(19)MA_DATA(18)MA_DATA(17)MA_DATA(16)MA_DATA(15)MA_DATA(14)MA_DATA(13)MA_DATA(12)MA_DATA(11)MA_DATA(10)
MA_DATA(9)MA_DATA(8)MA_DATA(7)MA_DATA(6)MA_DATA(5)MA_DATA(4)MA_DATA(3)MA_DATA(2)MA_DATA(1)MA_DATA(0)
DCLKA1
MDA56
MDA54
DCLKA0
-DQSA5
MDA22
DCLKA1810
MDA55
-DCLKA3910
-DQSA2
MDA39
MDA17
DMA0
SBAA18910
MAAA9
-DCLKA0
MAAA10
SACB0
-SWEA
MODT_A0810
SBAA1
MDA30
DCLKA2810
MDA44
-DQSA8
MDA8
MDA18
DMA5
MDA15
DQSA1
MDA47
MDA13
MDA0
DQSA0
MDA19
SBAA28910
MDA[063] 89
MDA42
MDA2
MODT_A1910
SACB1
-DQSA[08] 89
MAAA5
DCLKA5
MAAA2
-DCLKA2810
DMA[08] 89
MDA29
MAAA8
MAAA12
-DQSA7DQSA6
MDA31
MDA50
-SCASA
MDA21
MDA10
MDA48
DQSA[08] 89
-DCLKA2
-DQSA6
MDA4
MDA12
SACB2
-DCLKA5
DMA4
-DCLKA4
-SRASA8910
MAAA0
CKEA1
MDA60
SACB5
DQSA7
MDA58
MDA27
DMA6
MDA35
-DQSA[08]
MDA23
MDA32
-SCASA8910
MDA11
MDA59
MAAA6
MDA38
MDA9
MDA37
MAAA7
DCLKA2
MODT_A1
-DQSA0
MAAA1
DCLKA4
DQSA5
-CSA0810
CKEA0810
MAAA15
MDA51
-SWEA8910
SBAA0
SACB7
-DCLKA5910
SACB[07]
DMA8
CKEA1910
MDA53
MDA43
SACB6
MDA34
DMA1
MDA14
-CSA3910
MDA20
MAAA11
MDA6
MDA33
MDA28
-DCLKA1
MDA57
MDA63
DMA3
MDA36
-CSA1810
MAAA[015]8910
MAAA4
MAAA13
DCLKA3
DMA7
MDA46
DQSA2
MDA3DQSA4
DQSA[08]
MDA49
DCLKA5910
MAAA3
CKEA0
MDA7
MDA52
DMA[08]
MODT_A0
-CSA2910
SACB3
-DQSA4
MDA24
MDA61
MDA26
-DCLKA0810
MAAA14
MDA1
DCLKA4910
SACB[07] 89
-DCLKA3
DQSA8-DQSA1
MDA25
-SRASA
MDA41MDA40
DCLKA0810
SBAA08910
MDA45
MDA62
SBAA2
DMA2
SACB4
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
20 Date1120419 Dept
By Eddie
MDB47
-DQSB[08] 89
MAAB0
DQSB0
MDB50-DCLKB5
SBAB0
MAAB6
MAAB15
MDB57
DMB8
SBCB2
-CSB1810
-CSB3910
MDB[063] 89
-DCLKB0
MODT_B1
DQSB[08]
MDB10
MDB20
MDB32
MDB63
DCLKB3
-DQSB5 MDB5
SBCB0
MDB16
MDB22
MDB30
DQSB[08] 89
MDB39
DMB6
DCLKB3910
MDB44
-DQSB0
DCLKB5
CKEB0
MDB49
SBAB1
MAAB5
DQSB3
SBCB[07]
MDB54
MAAB10
SBCB4
DCLKB4910
MODT_B0810
DCLKB0810
-DCLKB3910
DCLKB0
MDB9
MDB19
-DQSB[08]
-DQSB7
-DCLKB2
MAAB4
DMB2
-DCLKB4
MDB0
MDB29
MDB41
MODT_B0
MDB15
MDB21
MAAB14
SBAB08910
MDB28
MDB36
DMB7
-DCLKB4910
MDB43
DQSB2
MODT_B1910
CKEB1910 CKEB1
MDB46
DMB[08]
-DCLKB0810
MDB4
DQSB6
-DCLKB1810
MDB53
MAAB9
MEMORY INTERFACE B
SOCKET_M2C
CPU-SK940AM2S15u
AJ19AK19
A18A19U31U30
AE30AC31
AD29
AL19AL18
C19D19
W29W28
AE29AB31
AD31
AC29AC30AB29
N31AA31AA28
M31M29
N28N29
AE31N30P29
AA29P31R29R28R31R30T31T29
U29U28
AA30
AK13AJ13AK17AJ17AK23AL23AL28AL29
D31C31C24C23D17C17C14C13
AJ14AH17AJ23AK29
C30A23B17B13
AH13AL13AL15AJ15AF13AG13AL14AK15AL16AL17AK21AL21AH15AJ16AH19AL20AJ22AL22AL24AK25AJ21AH21AH23AJ24AL27AK27AH31AG30AL25AL26AJ30AJ31E31E30B27A27F29F31A29A28A25A24C22D21A26B25B23A22B21A20C16D15C21A21A17A16B15A14E13F13C15A15A13D13
J31J30
J29
K29K31G30G29L29L28H31G31
MB0_CLK_H(2)MB0_CLK_L(2)MB0_CLK_H(1)MB0_CLK_L(1)MB0_CLK_H(0)MB0_CLK_L(0)
MB0_CS_L(1)MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)MB1_CLK_L(2)MB1_CLK_H(1)MB1_CLK_L(1)MB1_CLK_H(0)MB1_CLK_L(0)
MB1_CS_L(1)MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_LMB_WE_LMB_RAS_L
MB_BANK(2)MB_BANK(1)MB_BANK(0)
MB_CKE(1)MB_CKE(0)
MB_ADD(15)MB_ADD(14)MB_ADD(13)MB_ADD(12)MB_ADD(11)MB_ADD(10)MB_ADD(9)MB_ADD(8)MB_ADD(7)MB_ADD(6)MB_ADD(5)MB_ADD(4)MB_ADD(3)MB_ADD(2)MB_ADD(1)MB_ADD(0)
MB_DQS_H(7)MB_DQS_L(7)MB_DQS_H(6)MB_DQS_L(6)MB_DQS_H(5)MB_DQS_L(5)MB_DQS_H(4)MB_DQS_L(4)MB_DQS_H(3)MB_DQS_L(3)MB_DQS_H(2)MB_DQS_L(2)MB_DQS_H(1)MB_DQS_L(1)MB_DQS_H(0)MB_DQS_L(0)
MB_DM(7)MB_DM(6)MB_DM(5)MB_DM(4)MB_DM(3)MB_DM(2)MB_DM(1)MB_DM(0)
MB_DATA(63)MB_DATA(62)MB_DATA(61)MB_DATA(60)MB_DATA(59)MB_DATA(58)MB_DATA(57)MB_DATA(56)MB_DATA(55)MB_DATA(54)MB_DATA(53)MB_DATA(52)MB_DATA(51)MB_DATA(50)MB_DATA(49)MB_DATA(48)MB_DATA(47)MB_DATA(46)MB_DATA(45)MB_DATA(44)MB_DATA(43)MB_DATA(42)MB_DATA(41)MB_DATA(40)MB_DATA(39)MB_DATA(38)MB_DATA(37)MB_DATA(36)MB_DATA(35)MB_DATA(34)MB_DATA(33)MB_DATA(32)MB_DATA(31)MB_DATA(30)MB_DATA(29)MB_DATA(28)MB_DATA(27)MB_DATA(26)MB_DATA(25)MB_DATA(24)MB_DATA(23)MB_DATA(22)MB_DATA(21)MB_DATA(20)MB_DATA(19)MB_DATA(18)MB_DATA(17)MB_DATA(16)MB_DATA(15)MB_DATA(14)MB_DATA(13)MB_DATA(12)MB_DATA(11)MB_DATA(10)
MB_DATA(9)MB_DATA(8)MB_DATA(7)MB_DATA(6)MB_DATA(5)MB_DATA(4)MB_DATA(3)MB_DATA(2)MB_DATA(1)MB_DATA(0)
MB_DQS_H(8)MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)MB_CHECK(6)MB_CHECK(5)MB_CHECK(4)MB_CHECK(3)MB_CHECK(2)MB_CHECK(1)MB_CHECK(0)
SBAB18910
MDB60
MDB8
DQSB7
-DCLKB5910
DCLKB2
MAAB3
MDB18
-SRASB
DMB3
SBCB5
SBAB28910
DCLKB4
DCLKB5910
CKEB0810
SBCB[07]89
MDB12
MDB24MAAB13
MDB17
MDB27
MDB35
MDB42
DCLKB1810
DCLKB2810
MDB38
SBAB2
MDB45
MDB3
MDB56
-DQSB6
MAAB8
MDB7
MDB59
SBCB1
MDB51
DQSB8-DQSB1
-DQSB2
DMB1
-SWEB8910
-DCLKB1
MAAB2
MDB62
-SWEB
MAAB[015]8910
SBCB6
-SCASB8910
MDB11
MDB23
-DCLKB3
-DCLKB2810
-DQSB4
MAAB12
MDB14
MDB26
MDB34
MDB31
MDB37
DMB4
MDB2
MDB48
MDB55
DQSB5
-SRASB8910
MAAB7
MDB58
-DQSB8
DQSB4
DQSB1
SBCB3
DMB[08] 89
DMB0
DCLKB1
MAAB1
MDB61
-SCASB
-CSB0810
SBCB7
MDB6
-DQSB3
MAAB11
MDB13
MDB25
MDB33
-CSB2910
MDB40
DMB5
MDB1
MDB52
Memory Interface Channel B
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
21 Date1120419 Dept
By Eddie
DDR2 SDRAM Memory Interface Pin Descriptions
Signal Name Type Description
M[B A][10]_CLK_HL[20] O-IOD DRAM Differential Clock
M[B A][10]_CS_L[10] O-IOS DRAM Chip Selects
M[B A][10]_ODT[0] O-IOS DRAM Enable Pin for On Die Termination
M[B A]_CKE[10] O-IOS DRAM Clock Enable
M[B A]_DQS_HL[80] B-IOD DRAM Differential Data Strobe
M[B A]_DATA[630] B-IOS DRAM Interface Data Bus
M[B A]_DM[80] O-IOS DRAM Data Mask Bits
M[B A]_CHECK[70] B-IOS DRAM Interface ECC Check Bits
M[B A]_RAS_L O-IOS DRAM Row Address Select
M[B A]_CAS_L O-IOS DRAM Column Address Select
M[B A]_WE_L O-IOS DRAM Write Enable
M[B A]_ADD[150] O-IOS DRAM ColumnRow Address
M[B A]_BANK[20] O-IOS DRAM Bank Address
M_VREF VREF DRAM Interface Voltage Reference
M_ZP A Compensation Resistor tied to VSS
M_ZN A Compensation Resistor tied to VDDIO
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
22 Date1120419 Dept
By Eddie
Unbuffered 4-DIMM Block Diagram
MB1_CLK_H[20] MB1_CLK_L[20]
MA1_CLK_H[20] MA1_CLK_L[20]
MB0_CLK_H[20] MB0_CLK_L[20]
MA0_CLK_H[20] MA0_CLK_L[20]
MA_ADD[150] MA_BANK[20]
MB_ADD[150] MB_BANK[20]
MA_RAS_LMA_CAS_LMA_WE_L
MB_RAS_LMB_CAS_LMB_WE_L
MA0_CS_L[10]MA_CKE[0]MA0_ODT[0]
MA1_CS_L[10]MA_CKE[1]MA1_ODT[0]
MB1_CS_L[10]MB_CKE[1]MB1_ODT[0]
MB0_CS_L[10]MB_CKE[0]MB0_ODT[0]
MB_DATA[630]MB_CHECK[70]
MA_DATA[630]MA_CHECK[70]
MA_DQS_H[80]MA_DQS_L[80]
MB_DQS_H[80]MB_DQS_L[80]
MB_DM[80]
MA_DM[80]
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
Unb
uffer
ed D
DR2
SDRA
M 2
40 D
IMM
DIMM A0 DIMM A1DIMM B0 DIMM B1
AM2 Socket
Processor
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
23 Date1120419 Dept
By Eddie
Power-Up Signal Sequencing
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
24 Date1120419 Dept
By Eddie
OFS Over Voltage
VID36
C129001U4Y5V50VZ
+12V
XVID1
C1241U8Y5V25VZ
R22606SHTX
VIN12
R2290226
COREFB-634
R996
476
+1
EC25
560uFPD25V886m
R229 06SHTX
R247106X
Close to MOSFET
+1
EC26
560uFPD25V886m
R230 56K4
Q192SK3918TO2521300pF75m
1 32
R229106SHTX
R2311K4
VID26
UG4
R993
476
R246 04X
CPUVDD_EN621
PIN12L3
06uHV40ADLPI129ND
VCORE
PWM135
R227226
PH1
PH3
VID16
XVID4
R24104
Q309
2SK3918TO2521300pF75m
1 32
Q3082SK3918TO2521300pF75m
1 32
VCCP
PIN22
XVID4 R2511 04
L2
06uHV40ADLPI129ND
DRN4 1K8P4R61 23 45 67 8
HIGH(gt124V) ENABLE VRM
+12V
VCORE_PWOK37
R240 06SHTX
R244 51141
R235
10K41
VIN12
R994 82K4
UG3
R245 04X
CPUVDD_EN
C1261U8Y5V25VZ
C133001U4Y5V50VZ
R233 150K41
C1311U8Y5V25VZ
XVID2
+1
EC22
560uFPD25V886m
L21
06uHV40ADLPI129ND
08V~155V52A
PIN19
+1
EC27
3300UD63VAP12m
VIN12
R250226
PH4
R2459 1K4
PIN8
Q22
2SK3918TO2521300pF75m
1 32
+1
EC20
560uFPD25V886mX
C1517
1U8Y5V25VZ
VCC
IO_VID0 42XVID0
XVID2
R234 56K4
C1231U8Y5V25VZX
XVID0
PIN21
R254226
U7HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
C132022U8Y5V25VZ
UG2
For 8mm amp 10mm Co-Layout
VID46
XVID1
PIN25
Q212SK3918TO2521300pF75m
1 32
+1
EC24
560uFPD25V886mX
C15181U8Y5V25VZ
VIN12
RN264 08P4R6
1 23 45 67 8
VCC_SENSE1
VCORE
R232 56K4
2k VID+20mV
Q20
2SK3918TO2521300pF75m
1 32
C1201U8Y5V25VZ
C122022U8Y5V25VZ
R224106X
C15191U8Y5V25VZX
R2286
476
DR39 1K4
VCC3
V12
IO_VID2 42
DRV_CH3
VCC
VCORE
Q232SK3918TO2521300pF75m
1 32
R22316
C130
1U8Y5V25VZ
U5HIP6602BCBSO14
11
5
1
12
13
14
4
3 6
9
8
7
10
2
BOOT1
PVC
C
PWM1
UGATE1
PHASE1
VCC
LGATE1
GN
D
PGN
D
UGATE2
PHASE2
LGATE2
BOOT2
PWM2
XVID0
PIN10
Q24 2SK3918TO2521300pF75m
1 32
R237 04
VIN12
DRN208P4R6
12345678
XVID1
5K VID+50mV
R2458 514X
XVID3
R25706SHTX
IO_VID1 42
FS
COREFB+634
R2481 04
R239226
R2289226
R2460 1K41
Close to MOSFET
Close to MOSFET
LG1
R1054 470K4X
U8
ISL6559CRZS
1826
15
7
14
25
3032
123
6
11
20
2122
19
109
5
27
12
13
29
28
48
1617
2324
31
33
ISEN2FSDIS
VCC
FB
GND
PGOOD
VID4VID3VID2VID1VID0
COMP
VSEN
PWM2
PWM1ISEN1
GND
VDIFFIDROOP
OFS
EN
RGND
GND
OVP
GND
NC
NC
PWM3ISEN3
ISEN4PWM4
NC
GND
PIN18
C1281U8Y5V25VZ
C125001U4Y5V50VZ
LG2
DRN108P4R6
12345678
C1211U6Y5V10VZ
DRN308P4R6
12345678
+12V
FB 34
R225 226
XVID3
Close to MOSFETLG3
IO_VID3 42
PH2
XVID3
PIN24
R22856K4
R995
476
C1520001U4Y5V50VZ
R2285 56K4
R249 7541
L4
06uHV40ADLPI129ND
PIN9
XVID2
LG4
R238 69841X
PIN28
+1
EC28
3300UD63VAP12m
R236 226
COREFB+634
VID06
XVID4
PIN25
PIN11
R24816
PH4
C127 56N4X7R16VK
+1
EC21
560uFPD25V886mX
UG1
PIN23
VSS_SENSE1
IO_VID4 42
CPU VCORE
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
25 Date1120419 Dept
By Eddie
MCP55XE Power
Signal Description
+33V_VBAT 33 V Battery Voltage (20V~345V)This voltage powers the RTC
+33V_DUAL 33 V Sleep Mode PowerThis voltage powers the power management interface to 33 V peripherals
+33V_USB_DUAL 33 V USB Power (connect to 3VDual)This voltage powers the integrated USB controllers Connect this signal directly on the motherboard to the +33 V_DUAL power plane
+33V_PLL_MAC_DUAL 33 V MAC PLL Standby Power (connect to 3VDual)This voltage powers the MAC PLL during power management states
+12V_DUAL 12 V Sleep Mode Core PowerThis voltage powers the internal power management circuitry and devices of MCP55PXE that remain active while in S3-S5
+5V 5 V PowerThis voltage is used as the reference voltage for the 5 V tolerant IO
+33V 33 V PowerThis voltage powers the 33 V interface to 33 V peripherals
+33V_HT 33 V HyperTransport Power (connect to VCC3) This voltage powers the HyperTransport interface circuitry
+33V_PLL_CPU 33 V CPU Interface PLL Power (connect to VCC3)This voltage powers the PLL of the CPU interface
+33V_PLL_HT 33 V HyperTransport PLL Power (connect to VCC3)This voltage powers the PLL of the HyperTransport interface
+33V_PLL_USB 33V USB PLL Power (connect to VCC3)This voltage powers the USB PLL
+33V_PLL_PE_SS 33 V PCI Express Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the PCI Express interface
+33V_PLL_SP_SS 33 V SATA Spread Spectrum PLL Power (connect to VCC3)This voltage powers the spread spectrum PLL of the SATA interface
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
26 Date1120419 Dept
By Eddie
Signal Description
+15V 15 V Core PowerThis voltage powers the core of the NVIDIA MCP55PXE
+15V_PEA 15 V PCI Express Analog Power (connect to VCC15)This voltage powers the analog section of the PCI Express interface
+15V_PLL_CPU_HT 15 V HyperTransport PLL Power (connect to VCC15)This voltage powers the HyperTransport PLL clock drivers
+15V_PLL_PE_SS 15 V PCI Express Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the PCI Express interface
+15V_PLL_PE 15 V PCI Express PLL Power (connect to VCC15)This voltage power the PLL of the PCI Express interface
+15V_PLL_SP_SS 15 V SATA Spread Spectrum PLL Power (connect to VCC15)This voltage powers the spread spectrum PLL of the SATA interface
+15V_PLL_SP_VDD 15 V SATA PLL Power (connect to VCC15)This voltage powers the PLL of the SATA interface
+15V_PLL_USB 15 V USB PLL Power (connect to VCC15)This voltage powers the PLL of the USB interface
+15V_SP_A 15 V SATA Analog Power (connect to VCC15)This voltage powers the analog section of the integrated SATA
+15V_SP_D 15 V SATA Digital Power (connect to VCC15)This voltage powers the digital section of the integrated SATA
+12V 12 V Core Power (connect to VCC15)This voltage powers the core of the NVIDIA MCP55PXE
+12V_HT 12 V HyperTransport PowerThis voltage powers the HyperTransport interface
GND Ground
MCP55XE Power (Cont)
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
27 Date1120419 Dept
By Eddie
VCC12DUAL
+33V
+33V_HT
+33V_PLL_CPU
+33V_PLL_HT
+33V_PLL_USB
+33V_PLL_PE_SS
+33V_PLL_SP_SS
+15V
+15V_PEA
+15V_PLL_CPU_HT
+15V_PLL_PE_SS
+15V_PLL_PE
+15V_PLL_SP_SS
+15V_PLL_SP_VDD
+15V_PLL_USB
+15V_SP_A
+15V_SP_D
+12V
+12V_HT
+33V_VBAT
+33V_DUAL+33V_USB_DUAL+33V_PLL_MAC_DUAL
+12V_DUAL
+5V
VCC12_HTMCP
VCC15V3VDUAL
RTCVDD
VCC3
+5V
R2294
1001210
R2293
1001210
VCC
VCC_MCP1
01U6Y5V25VZBC806
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
28 Date1120419 Dept
By Eddie
Signal Description
+12V_CORE Core Power RailThis voltage powers the core logic of the C51XE It is derived from the mainsilver box ldquoPS_ONrdquo power supply rails
+12V_HT Isolated HyperTransport Power RailSince the +12V_CORE power rail is enabled simultaneously with the +33Vmain power supply rail and before the CPU power is valid the enable of this railmust be delayed to honor the AMD power sequence Most NVIDIA MCP deviceshave timed digital sequencer outputs These can be used to accurately controlthis sequence in accordance with AMD regulations and without using highlyvariable RC timing circuits
+12V_HTMCP HyperTransport to MCP Power RailThis voltage powers the HyperTranport interface between the C51XE and the MCP51
+12V_PEA +12V PCI Express Analog VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the analog circuits of the PCI Express block
+12V_PED +12V PCI Express Digital VoltageThis is a filtered version of the +12V_CORE power supply and is used topower the digital circuits of the PCI Express block
+12V_PLL +12V PLL VoltageThis is a filtered version of the +12V_CORE power supply and is used topower some of the internal PLLs
+12V_PLLCORE +12V Core PLL VoltageThis voltage powers the PLL of the core logic It is a filtered version of the+12V_CORE voltage
+12V_PLLHTCPU +12V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is afiltered version of the +12V_CORE voltage
+12V_PLLHTMCP +12V MCP HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the MCP It is afiltered version of the +12V_CORE voltage
C51XE Power Description
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
29 Date1120419 Dept
By Eddie
Signal Description
+12V_PLLIFP +12V VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+12V_PLLGPU This voltages rails is not used by C51XE It should be pulled down to GNDthrough a 47 kΩ resistor
+25V_CORE 25V Core VoltageThis voltage is used to power the core logic of the C51XE It is derived from themain silver box ldquoPS_ONrdquo power supply rails
+25V_PLLCORE +25V Core PLL VoltageThis voltage powers the core PLL It is a filtered version of the +25V_CORE voltage
+25V_PLLGPU +25V GPU PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_PLLHTCPU +25V CPU HT PLL VoltageThis voltage powers the PLL of the HyperTransport interface to the CPU It is a filtered version of the +25V
_CORE voltage
+25V_PLLIFP +25V IFP PLL VoltageThis voltages rails is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+33V +33V VoltageThis voltage is the +33V rail supplied by the main silver box power supply It isused to power the +33V IOs
+33V_DAC +33V DAC VoltageThis voltage power the video output DAC It is a filtered version of the +33V power supply
+25V_IFPA +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
+25V_IFPB +25V VoltageThis voltage rail is not used by C51XE It should be pulled down to GND through a 47 kΩ resistor
C51XE Power Description (cont)
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
30 Date1120419 Dept
By Eddie
C51XE POWER
1P2VPEA_PWR
2P5V_PLLCORE
VCC12
VCC12_HTMCP
1P2VPLL_PWRFB23
06SHTX
2P5V_PWR
BC76101U6Y5V25VZ
VCC12_HT
FB21 06SHTX
2P5V_PWR
1P2VPLL_PWR
VCC12
VCC12
BC76247U8Y5V10VZ
1P2VPLL_PWR+12V_PLLCORE
VCC3
FB22
06SHTX
+12V_CORE
VCC12
1P2VPEA_PWR
+25V_PLLCORE
SEC 5 OF 6
I101
U1E BGAC51
C51XE-N-A2S
+33V+33V
+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT+12V_HT
+12V_PED+12V_PED+12V_PED+12V_PED
+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP+12V_HTMCP
+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE+12V_CORE
+12V_CORE
+25V_IFPB+25V_IFPA
+25V_CORE+25V_CORE
+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL+12V_PLL
+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA+12V_PEA
C10D18
H17C21U17T16J20
M21R16M16K16
E7D6C5B4
U15U16
W16AA18AB11
Y9U11U13T15
J14J13J12J11
H11G11F11F10E10
E9E8D7C6B5
H15G15
B16C16
J10H10G9G8G7F6E5D4C3C2B2A2
F9F8F7E6D5C4B3A3
+12V_CORE
1P2VPLL_PWR
2P5V_PWR
FB24
06SHTX
+12V_CORE
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
31 Date1120419 Dept
By Eddie
5VSB 5VDUAL
R20611K4
+1
EC1111100UD10V57
5VSB
5VSB+
-
U98B
KA393DSO8
5
67
84
5VDUAL
R20581K4
Q311
AP9435KSOT89507pF50m[10IFC-450603-01R_10IF5-509435-01R]
123
4
R2060 39K41
R205982K4
5VSB
01U6Y5V25VZC1440
SSOP6 Co-Layout SOT89
5VSB
VCC
5VDL_G1
5VSB
Q297
2SK3919TO2522050pF56m
1
32U99
AO6401TSOP6943pF49mX
1234 65
DDGS DD
KA393_3+
-
U98A
KA393DSO8
3
21
84
5VDUAL
Q298
2SK3919TO2522050pF56mX
1
32
PWOK37394249
5VDL_G1
33P4NPO50VJXC1439
+12V
R2062
06SHTX
BC383001U4Y5V50VZX
5VDUAL
BC384001U4Y5V50VZX
+1
EC1112
1000UD63V8C30m
C143801U6Y5V25VZ
VCC5VSB
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
32 Date1120419 Dept
By Eddie
Q75KD1084ADTTO2525A
1
32
BC13301U6Y5V25VZ
3VDUAL
R39616941
5VDUAL
R39310041
BC13401U6Y5V25VZ
EC431000UD63V8C30m
5VDUAL3VDUAL
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
33 Date1120419 Dept
By Eddie
+1
EC1115100UD10V57
VCC12DUAL
Q314AMC1117SKSOT22308A
123
43VDUAL
BC81310U8Y5V10VZ
BC40001U6Y5V25VZR2126
10041
R21272041
VCC12DUAL
15V850mA Max
3VDUALVCC12DUAL
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
34 Date1120419 Dept
By Eddie
DDR18_OV6
10A
DDR18OV2 21
+1
EC1108
1000UD63V8C30m
RN26282K8P4R6
1 23 45 67 8
R2046 106 25V
DDR18_OV5 21
R2314 634K41
DDR18_OV6 21
R204530K4
L20
3uHH10A1PT3726D
SOT23
BAT54ASOT23200mAD77
DDR18OV4
VDDIO_FB_H 6
R2053 12K41X
C14341U8Y5V25VZ
R2485 04
S5_EN
DDR18_OV3
R2408 3K41
R2052 30K41X
SOT23
BAT54ASOT23200mAD78
G
D
S
Q294
2SK3918TO2521300pF75m
1 32
R2051154K41
U97
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATE
R204316
R2488 04C143510P4NPO50VJ
3VDUAL
L19
1uHV10A1PT3726D
+1
EC11091000UD63V8C30m
R204920K41
BC37847U8Y5V10VZ
C1433
01U6Y5V25VZ
C1436001U4Y5V50VZ
DDR18OV4 21
5VDUAL
DDR18_OV5
R2409 3K41X
R20502K41
DDR18V
R2048226
+1
EC11051000UD63V8C30m
SOT23
BAT54ASOT23200mAD76
DDR18_OV3 21
+1
EC11061000UD63V8C30m
5VDUAL
C1437
47n6X7R50VK
R2139 12K41
BC3801U6Y5V10VZ
DDR18_OV1 21
D66SS12SMA1A
G
D
S
Q293
2SK3918TO2521300pF75m
1 32
DDRV18V
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
35 Date1120419 Dept
By Eddie
S5_EN
G S
D Q3412N7002SOT2325pF5
2 13
-SLP_S521 R2057
47K4X
G S
D Q3422N7002SOT2325pF5
2 13
-IO_PSON
394042
R2502
82K4
R2501
82K4
Q295
MMBT2222ASOT23600mA40
13
2
R20541K4
S5_EN
BC38101U6Y5V25VZX
SLP_S3
R205682K4
D791N4148WSOD123300mA
BC8871u8Y5V16VZ
G S
D Q296
2N7002SOT2325pF5
2 13
BC38201U6Y5V25VZX
S5_EN
S5_EN
5VSB
-SLP_S3
21373942
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
36 Date1120419 Dept
By Eddie
DDRVTT
BC37901U6Y5V25VZ
U96
W83310S-R2SO820A
1
2
3
4 5
6
7
8
9
VIN
GND
VREF1
VOUT BOOT_SEL
VCNTL
ENABLE
VREF2
GND
DDR18V
DDRVTT
R204715041
R204415041
3VDUAL
PAD500 X 500mil^2
+1
EC1107
100UD10V57
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
37 Date1120419 Dept
By Eddie
VCC15_OV1 42
L16 28uHV20A3PT5052D
+1
EC1541000UD63V8C30m
U90
ISL6520ACBZSO8
7
5
1
8
3
46
2COMP
VCC BOOT
PHASE
GND
LGATEFB
UGATEVCC15
D65SS12SMA1A
VCC15_OV2 42
EN
BC34347U8Y5V10VZ
R1820226
C1284001U4Y5V50VZ
G
D
S
Q278
2SK3919TO2522050pF56m
1 32
R182288741
VCC VCC
C12821U8Y5V25VZ
SOT23
BAT54ASOT23200mA
D80
C128310P4NPO50VJ
R1930 649K41
R2489 04
+1
EC1531000UD63V8C30m
+1
EC1551000UD63V8C30m
R18231K41
R182120K41
BC3441U6Y5V10VZ
R1819 106
C1285
47n6X7R50VK
C1314
01U6Y5V25VZ
+1
EC1561000UD63V8C30m
R181716
R181830K4
R2318 249K41
8A
G
D
S
Q2772SK3919TO2522050pF56m
1 32
25V
L18
1uHV10A1PT3726D
VCC15
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
38 Date1120419 Dept
By Eddie
+
- U12ALM324MSO14
3
21
411
Q319AOD420TO252710pF25m
1 32
C176001U4Y5V50VZX
R368 1K41
VCC12_OV1 21
Q318
AOD420TO252710pF25mX
1 32
SOT23
BAT54ASOT23200mA
D73
R2313 62K4
+12V
C177
1U6Y5V10VZX
R107336K41
BC128
1U6Y5V10VZX3VDUAL
VCC12
+1
EC1117
1000UD63V8C30m
VCC12_OV2 21
R2312 12K41
VCC15
Z218
C1281001U4Y5V50VZX
C17501U6Y5V25VZ
R3672K41
+1
EC11161000UD63V8C30m
VCC12
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
39 Date1120419 Dept
By Eddie
R19221K4
VCC3
SOT23
Q282MMBT2222ASOT23600mA40
13
2
BC36901U4Y5V16VZ
HT1VDD_EN21
VCC12HT_OV2 42
VCC12_HT
R377 62K4
BC1291U6Y5V10VZ
+
EC381000UD63V8C30m
R3752K41
R37336K41
850mA
HT1_EN
C181001U4Y5V50VZX
3VDUAL
R376 1K41
G S
D Q2832N7002SOT2325pF5
2 13
5VSB
R1923 82K4
VCC12HT_OV1 42
+
- U12BLM324MSO14
5
67
411
Q70AOD420TO252710pF25m
1 32
+12V
R378 12K41
VCC12_HT
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
40 Date1120419 Dept
By Eddie
R2322 12K41
+
- U12CLM324MSO14
10
98
411
R386 1K41
+12V
VCC12_HTMCP
VCC12_CORE_OV2 42
3VDUAL
VCC12_CORE_OV1 42
R38136K41
+
EC11241000UD63V8C30m
R3842K41
R2323 62K4
BC13147U8Y5V10VZ
BC2021U6Y5V10VZ
Q73
AOD420TO252710pF25m
1 32
C182001U4Y5V50VZX
VCC3
C183001U4Y5V50VZX
13V850mA
R1786
1K4X
VCC12_HTMCP
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
41 Date1120419 Dept
By Eddie
BC13001U6Y5V25VZ
R24873K41
BC13601U6Y5V25VZ
R38082K4
G S
DQ340
2N7002SOT2325pF5
2 13
3VDUAL
VDDA25
C184001U4Y5V50VZX
5VSB
C186001U4Y5V50VZ
G S
D Q712N7002SOT2325pF5
2 13
R3951K4X
VDDA25_EN
BC132001U4Y5V50VZ
+
- U12DLM324MSO14
12
1314
411
R3891K41
VCC3
R38547K4X
R1356 82K4
V25_G
EC40100UD10V57
VCC3
DDR18V
+12V
V25_G
G S
D Q72MMBT2222ASOT23600mA40
2 13
G S
DQ74
2N7002SOT2325pF5
2 13
VDDA25
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
42 Date1120419 Dept
By Eddie
BC79101U6Y5V25VZX
R226510041
BC79210U8Y5V10VZX
2P5V_PWR
EC1113
10U8Y5V10VZX
Q304AMC1117SKSOT22308A
123
4
CR17610041
VCC2P5V_PWR
VCC2P5V_PWR
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
43 Date1120419 Dept
By Eddie
R35982K4
SOT23
Q65MMBT2222ASOT23600mA40
13
2
5VSB
R36082K4
R361 82K4
CK8_PWOK 6212841
-SLP_S321383942
VCC15_ENC174
01U6Y5V25VZ
3VDUAL
SOT23
Q63MMBT2222ASOT23600mA40
13
2
SOT23
Q337MMBT2222ASOT23600mA40
13
2
G S
D Q642N7002SOT2325pF5
2 13
3VDUAL
C17301U6Y5V25VZX
R2471 82K4
R363 1K4
VCC15
PWOK38394249
R36204X
CK8_ PWOK
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
44 Date1120419 Dept
By Eddie
HT_VLD
HT1_VLD 21
R346 62K4
3VDUAL
C163033U6Y5V16VZ
5VSB
HT1_VLD
G S
D Q2792N7002SOT2325pF5
2 13
R189382K4
R34382K4
SOT23
Q58MMBT2222ASOT23600mA40
13
2
R2041
82K4
R2042
15K4
5VDUALMEM_VLD 21
SOT23
Q292MMBT2222ASOT23600mA40
13
2
DDR18V
3VDUAL
R204015K4
MEM_VLD
SOT23
Q291
2N7002SOT2325pF5
13
2
CPU_VLD 21
R352 06SHTX
VCORE_PWOK33CPU_VLD
45 Date1120419 Dept
By Eddie
45 Date1120419 Dept
By Eddie
![CEVH CEVH-1P-DECO Mounting instructions · External height Ht [mm] [mm] DECO RPK [mm] DECO RPK 400 450 494 400 450 470 450 500 544 450 500 520 500 550 594 500 550 570 550 600 644](https://img.pdfslide.us/doc/110x75/5f7023cb04a50125214b0344/cevh-cevh-1p-deco-mounting-instructions-external-height-ht-mm-mm-deco-rpk-mm.jpg)
