14
CSD17381F4 30-V N-Channel FemtoFET MOSFET 1 Features Ultra-low on-resistance Ultra-low Q g and Q gd Low threshold voltage Ultra-small footprint (0402 case size) 1.0 mm × 0.6 mm Ultra-low profile 0.36 mm height Integrated ESD protection diode Rated >4 kV HBM Rated >2 kV CDM Lead and halogen free RoHS compliant 2 Applications Optimized for load switch applications Optimized for general purpose switching applications Single-cell battery applications Handheld and mobile applications 3 Description This 90 mΩ, 30 V N-Channel FemtoFET MOSFET technology is designed and optimized to minimize the footprint in many handheld and mobile applications. This technology is capable of replacing standard small signal MOSFETs while providing at least a 60% reduction in footprint size. . 1.00 mm 0.36 mm 0.60 mm Typical Dimensions . . . . Product Summary T A = 25°C TYPICAL VALUE UNIT V DS Drain-to-source voltage 30 V Q g Gate charge total (4.5 V) 1040 pC Q gd Gate charge gate-to-drain 133 pC R DS(on) Drain-to-source on-resistance V GS = 1.8 V 160 mΩ V GS = 2.5 V 110 mΩ V GS = 4.5 V 90 mΩ V GS(th) Threshold voltage 0.85 V . Ordering Information DEVICE (1) QTY MEDIA PACKAGE SHIP CSD17381F4 3000 7-Inch reel Femto (0402) 1.0 mm ×0.6 mm SMD Lead Less Tape and reel CSD17381F4T 250 (1) For all available packages, see the orderable addendum at the end of the data sheet. Absolute Maximum Ratings T A = 25°C unless otherwise stated VALUE UNIT V DS Drain-to-source voltage 30 V V GS Gate-to-source voltage 12 V I D Continuous drain current, T A = 25°C (1) 3.1 A I DM Pulsed Drain Current, T A = 25°C (2) 12 A I G Continuous gate clamp current 35 mA Pulsed gate clamp current (2) 350 P D Power dissipation (1) 500 mW ESD Rating Human body model (HBM) 4 kV Charged device model (CDM) 2 kV T J , T stg Operating junction and storage temperature range –55 to 150 °C E AS Avalanche energy, single pulse I D = 7.4 A, L = 0.1 mH, R G = 25 Ω 2.7 mJ (1) Typical R θJA = 90°C/W on 1 inch 2 (6.45 cm 2 ), 2 oz. (0.071 mm thick) Cu pad on a 0.06 inch (1.52 mm) thick FR4 PCB. (2) Pulse duration ≤ 100 μs, duty cycle ≤ 1%. D S G Top View CSD17381F4 SLPS411G – APRIL 2013 – REVISED JANUARY 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

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CSD17381F4 30-V N-Channel FemtoFET™ MOSFET

1 Features• Ultra-low on-resistance• Ultra-low Qg and Qgd • Low threshold voltage• Ultra-small footprint (0402 case size)

– 1.0 mm × 0.6 mm• Ultra-low profile

– 0.36 mm height• Integrated ESD protection diode

– Rated >4 kV HBM– Rated >2 kV CDM

• Lead and halogen free• RoHS compliant

2 Applications• Optimized for load switch applications• Optimized for general purpose switching

applications• Single-cell battery applications• Handheld and mobile applications

3 DescriptionThis 90 mΩ, 30 V N-Channel FemtoFET™ MOSFET technology is designed and optimized to minimize the footprint in many handheld and mobile applications. This technology is capable of replacing standard small signal MOSFETs while providing at least a 60% reduction in footprint size.

.

1.00 mm

0.36 mm

0.60 mm

Typical Dimensions

.

.

.

.

Product SummaryTA = 25°C TYPICAL VALUE UNIT

VDS Drain-to-source voltage 30 V

Qg Gate charge total (4.5 V) 1040 pC

Qgd Gate charge gate-to-drain 133 pC

RDS(on) Drain-to-source on-resistance

VGS = 1.8 V 160 mΩ

VGS = 2.5 V 110 mΩ

VGS = 4.5 V 90 mΩ

VGS(th) Threshold voltage 0.85 V

.Ordering Information

DEVICE(1) QTY MEDIA PACKAGE SHIP

CSD17381F4 3000 7-Inch reel

Femto (0402) 1.0 mm ×0.6 mm SMD Lead

Less

Tape and reelCSD17381F4T 250

(1) For all available packages, see the orderable addendum at the end of the data sheet.

Absolute Maximum RatingsTA = 25°C unless otherwise stated VALUE UNIT

VDS Drain-to-source voltage 30 V

VGS Gate-to-source voltage 12 V

ID Continuous drain current, TA = 25°C(1) 3.1 A

IDM Pulsed Drain Current, TA = 25°C(2) 12 A

IGContinuous gate clamp current 35

mAPulsed gate clamp current(2) 350

PD Power dissipation(1) 500 mW

ESD Rating

Human body model (HBM) 4 kV

Charged device model (CDM) 2 kV

TJ,Tstg

Operating junction andstorage temperature range –55 to 150 °C

EASAvalanche energy, single pulse ID = 7.4 A,L = 0.1 mH, RG = 25 Ω 2.7 mJ

(1) Typical RθJA = 90°C/W on 1 inch2 (6.45 cm2), 2 oz.(0.071 mm thick) Cu pad on a 0.06 inch (1.52 mm) thick FR4 PCB.

(2) Pulse duration ≤ 100 μs, duty cycle ≤ 1%.

D

SG

Top View

CSD17381F4SLPS411G – APRIL 2013 – REVISED JANUARY 2022

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Table of Contents1 Features............................................................................12 Applications..................................................................... 13 Description.......................................................................14 Revision History.............................................................. 25 Specifications.................................................................. 3

5.1 Electrical Characteristics.............................................35.2 Thermal Information....................................................35.3 Typical MOSFET Characteristics................................ 4

6 Device and Documentation Support..............................7

6.1 Support Resources..................................................... 76.2 Trademarks.................................................................76.3 Electrostatic Discharge Caution..................................76.4 Glossary......................................................................7

7 Mechanical, Packaging, and Orderable Information.... 87.1 Mechanical Dimensions.............................................. 87.2 Recommended Minimum PCB Layout........................97.3 Recommended Stencil Pattern................................... 9

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (October 2021) to Revision G (January 2022) Page• Changed height dimension from "0.35 mm" to "0.36 mm" Features ..................................................................1• Changed height dimension from "0.35 mm" to "0.36 mm" in Typical Dimensions ............................................. 1• Changed height dimension from "0.35 mm" to "0.36 mm" in Mechanical Dimensions ......................................8

Changes from Revision E (December 2017) to Revision F (October 2021) Page• Updated the numbering format for tables, figures, and cross-references throughout the document..................1• Changed footnote to refer to correct support document..................................................................................... 9

Changes from Revision D (August 2014) to Revision E (December 2017) Page• Changed Pulsed Drain Current value From: 10 A To: 12 A in the Absolute Maximum Ratings table. ...............1• Change Note 2 From: Pulse duration ≤300 μs, duty cycle ≤2% To: Pulse duration ≤ 100 μs, duty cycle ≤ 1%. 1• Updated Figure 5-1. ...........................................................................................................................................4• Updated Figure 5-10 with newly measured data. .............................................................................................. 4• Updated all mechanical drawings, increased the size of the pads in Section 7.3 ............................................. 8

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5 Specifications5.1 Electrical Characteristics(TA = 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITSTATIC CHARACTERISTICSBVDSS Drain-to-Source Voltage VGS = 0 V, IDS = 250 μA 30 V

IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 24 V 100 nA

IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 10 V 50 nA

VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = 250 μA 0.65 0.85 1.10 V

RDS(on) Drain-to-Source On-Resistance

VGS = 1.8 V, IDS =0.5 A 160 250 mΩ

VGS = 2.5 V, IDS =0.5 A 110 143 mΩ

VGS = 4.5 V, IDS = 0.5 A 90 117 mΩ

VGS = 8 V, IDS =0.5 A 84 109 mΩ

gfs Transconductance VDS = 15 V, IDS = 0.5 A 4.8 S

DYNAMIC CHARACTERISTICSCiss Input Capacitance

VGS = 0 V, VDS = 15 V,ƒ = 1 MHz

150 195 pF

Coss Output Capacitance 44 57 pF

Crss Reverse Transfer Capacitance 2.2 2.9 pF

RG Series Gate Resistance 23 Ω

Qg Gate Charge Total (4.5 V)

VDS = 15 V, IDS = 0.5 A

1040 1350 pC

Qgd Gate Charge Gate-to-Drain 133 pC

Qgs Gate Charge Gate-to-Source 226 pC

Qg(th) Gate Charge at Vth 150 pC

Qoss Output Charge VDS = 15 V, VGS = 0 V 1110 pC

td(on) Turn On Delay Time

VDS = 15 V, VGS = 4.5 V,IDS = 0.5 A,RG = 2 Ω

3.4 ns

tr Rise Time 1.4 ns

td(off) Turn Off Delay Time 10.8 ns

tf Fall Time 3.6 ns

DIODE CHARACTERISTICSVSD Diode Forward Voltage ISD = 0.5 A, VGS = 0 V 0.73 0.9 V

Qrr Reverse Recovery ChargeVDS= 15 V, IF = 0.5 A, di/dt = 300 A/μs

1500 pC

trr Reverse Recovery Time 5.6 ns

5.2 Thermal Information(TA = 25°C unless otherwise stated)

THERMAL METRIC TYPICAL VALUES UNIT

RθJAJunction-to-Ambient Thermal Resistance(1) 90

°C/WJunction-to-Ambient Thermal Resistance(2) 250

(1) Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.(2) Device mounted on FR4 material with minimum Cu mounting area.

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5.3 Typical MOSFET Characteristics(TA = 25°C unless otherwise stated)

Figure 5-1. Transient Thermal Impedance

0

1

2

3

4

5

6

7

8

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

VDS ­ Drain­to­Source Voltage (V)

I DS ­

Dra

in­t

o­S

ourc

e C

urr

ent (A

)

VGS =8V

VGS =4.5V

VGS =2.5V

VGS =1.8V

G001

Figure 5-2. Saturation Characteristics

0

1

2

3

4

5

0 0.4 0.8 1.2 1.6 2 2.4

VGS ­ Gate­to­Source Voltage (V)

I DS ­

Dra

in­t

o­S

ourc

e C

urr

ent (A

)

TC = 125°C

TC = 25°C

TC = −55°C

VDS = 5V

G001

Figure 5-3. Transfer Characteristics

0

1

2

3

4

5

6

7

8

9

10

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2

Qg ­ Gate Charge (nC)

VG

S ­

Gate

­to­S

ourc

e V

oltage (

V) ID = 0.5A

VDS =15V

G001

Figure 5-4. Gate Charge

1

10

100

1000

0 3 6 9 12 15 18 21 24 27 30

VDS ­ Drain­to­Source Voltage (V)

C −

Capacitance (p

F)

Ciss = Cgd + Cgs

Coss = Cds + Cgd

Crss = Cgd

G001

Figure 5-5. Capacitance

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0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

−75 −25 25 75 125 175

TC ­ Case Temperature (ºC)

VG

S(t

h)

­ T

hre

shold

Voltage (

V)

ID = 250uA

G001

Figure 5-6. Threshold Voltage vs Temperature

60

70

80

90

100

110

120

130

140

150

160

0 2 4 6 8 10 12

VGS ­ Gate­to­ Source Voltage (V)

RD

S(o

n)

­ O

n­S

tate

Resis

tance (

) TC = 25°C Id = 0.5ATC = 125ºC Id = 0.5A

G001

Figure 5-7. On-State Resistance vs Gate-to-Source Voltage

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

−75 −25 25 75 125 175

TC ­ Case Temperature (ºC)

Norm

aliz

ed O

n­S

tate

Resis

tance

VGS = 1.8VVGS = 8V

ID =0.5A

G001

Figure 5-8. Normalized On-State Resistance vs Temperature

0.0001

0.001

0.01

0.1

1

10

0 0.2 0.4 0.6 0.8 1

VSD − Source­to­Drain Voltage (V)

I SD −

Sourc

e­t

o­D

rain

Curr

ent (A

)

TC = 25°C

TC = 125°C

G001

Figure 5-9. Typical Diode Forward Voltage

VDS - Drain-To-Source Voltage (V)

I DS -

Dra

in-T

o-S

ourc

e C

urr

ent (A

)

0.1 1 10 500.01

0.1

1

10

100

D010

100 ms10 ms

1 ms100 µs

10 µs

Single Pulse Typical RθJA =250°C/W (min Cu)

Figure 5-10. Maximum Safe Operating Area

0.1

1

10

100

0.001 0.01 0.1 1

TAV ­ Time in Avalanche (mS)

I AV ­

Peak A

vala

nche C

urr

ent (A

)

TC = 25ºC

TC = 125ºC

G001

Figure 5-11. Single Pulse Unclamped Inductive Switching

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0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

−50 −25 0 25 50 75 100 125 150 175

TA ­ AmbientTemperature (ºC)

I DS ­

Dra

in­

to­

Sourc

e C

urr

ent (A

)

Typical RthetaJA =90ºC/W(max Cu)

G001

Figure 5-12. Maximum Drain Current vs Temperature

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6 Device and Documentation Support6.1 Support ResourcesTI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

6.2 TrademarksFemtoFET™ are trademarks of Texas Instruments.TI E2E™ is a trademark of Texas Instruments.All trademarks are the property of their respective owners.6.3 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

6.4 GlossaryTI Glossary This glossary lists and explains terms, acronyms, and definitions.

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7 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

7.1 Mechanical Dimensions

C

0.35

2X0.16

0.14

2X0.26

0.24

0.36 MAX

0.325

0.26

0.24

0.51

0.49

0.175

0.65

A1.04

0.96B

0.64

0.56

PIN 1 INDEX AREA

SEATING PLANE

1

2

0.015 C B A

0.015 C A B

3

A. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

B. This drawing is subject to change without notice.C. This package is a Pb-free bump design. Bump finish may vary. To determine the exact finish, refer to the device data sheet or contact a

local TI representative.

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7.2 Recommended Minimum PCB Layout

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EXAMPLE BOARD LAYOUT

2X (0.25)

2X (0.15)0.05 MINALL AROUND

(0.65)

(0.35)

(0.25)

(0.5)

(R ) TYP0.05

4220651/B 08/2015

PicoStar - 0.35 mm max heightYJC0003APicoStar

PKG

1

2

SYMM

LAND PATTERN EXAMPLESOLDER MASK DEFINED

SCALE:50X

3

SOLDER MASKOPENING

METAL UNDERSOLDER MASK

NOTES: (continued)

4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

TM

TM

A. All dimensions are in millimeters.B. For more information, see FemtoFET Surface Mount Guide (SLRA003D).

7.3 Recommended Stencil Pattern

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EXAMPLE STENCIL DESIGN

2X (0.15)

2X (0.25)

2X (0.2)

(0.65)

(0.25)

(0.5)(0.4)

(R ) TYP0.05

4220651/B 08/2015

PicoStar - 0.35 mm max heightYJC0003APicoStar

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

TM

TM

SOLDER PASTE EXAMPLEBASED ON 0.075 - 0.1 mm THICK STENCIL

SCALE:50X

PKG

1

2

SYMM

3

2X SOLDER MASK EDGE

A. All dimensions are in millimeters.B. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design

recommendations.

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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

CSD17381F4 ACTIVE PICOSTAR YJC 3 3000 RoHS & Green NIAU Level-1-260C-UNLIM -55 to 150 CQ

CSD17381F4T ACTIVE PICOSTAR YJC 3 250 RoHS & Green NIAU Level-1-260C-UNLIM -55 to 150 CQ

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

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Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

CSD17381F4 PICOST AR

YJC 3 3000 180.0 8.4 0.7 1.1 0.46 4.0 8.0 Q2

CSD17381F4 PICOST AR

YJC 3 3000 178.0 8.4 0.7 1.1 0.46 4.0 8.0 Q2

CSD17381F4T PICOST AR

YJC 3 250 180.0 8.4 0.7 1.1 0.46 4.0 8.0 Q2

CSD17381F4T PICOST AR

YJC 3 250 178.0 8.4 0.7 1.1 0.46 4.0 8.0 Q2

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CSD17381F4 PICOSTAR YJC 3 3000 182.0 182.0 20.0

CSD17381F4 PICOSTAR YJC 3 3000 220.0 220.0 35.0

CSD17381F4T PICOSTAR YJC 3 250 182.0 182.0 20.0

CSD17381F4T PICOSTAR YJC 3 250 220.0 220.0 35.0

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 2

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