Future Fab International Volume 44

ISSUE 44 – January 2013 – www.future-fab.comIn Association with:

Special Focus: International Technology Roadmap for Semiconductors

Accelerating the next technology revolution.

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FUTURE FAB International | ITRS Issue 44

WELCOME …

Welcome to this, our fourth collaboration with the International Technology Roadmap for Semiconductors (ITRS). The world has changed immeasurably in the past four years: Facebook has gone from being a plaything to having a membership of one-seventh of the world’s population; there are now more Internet-connected devices in the world than there are people; and the semiconductor indus-try has embarked upon its long-discussed journey toward a larger wafer size amid a raft of technical challenges, any one of which could derail the quest to stick to Gordon Moore’s famous observation. Seemingly, then, our work with our partners is more important than ever, given that one of the main tools in overcoming the challenges we face is communica-tion. However, that too is facing its own challenge—one that we’re tackling head on in the new year, and one we’d like you to participate in.

Until then, here’s to a prosperous 2013!

The Future Fab team

SPECIAL INTRODUCTION | FUTURE FAB International | Issue 44

2 | FUTURE FAB International | ITRS Issue 44 3www.future-fab.com | 3www.future-fab.com |

Paolo A. GarginiChairman of the International Technology Roadmap for Semiconductors (ITRS)

The organization of the ITRS is very simple

and yet it very efficiently covers an incredible

amount of information that is readily avail-

able to anybody with access to the Internet

(www.itrs.net). The International Roadmap

Committee (IRC) oversees and organizes all

the activities of the ITRS, and now 17 ITWGs

produce the technical chapters. These organi-

zations meet three times a year for face-to-

face meetings intermixed by multiple phone

and e-mail communications. The spring meet-

ing is held in Europe, the summer meeting

in the United States, and the winter meeting

rotates among Japan, Korea and Taiwan (the

latter being the location of the 2012 meeting).

It is absolutely remarkable how the working

groups—with representatives from Europe,

Japan, Korea, Taiwan and the United States—

have been able to work together so coopera-

tively and efficiently.

A Solid FoundationThe NTRS was founded on Moore’s Law and

Dennard’s Scaling Law, which still represent the

pillars of the semiconductor industry.

Intel’s Gordon Moore anticipated the explo-

sive growth of integrated circuits in 1965, when

he predicted the doubling of transistors every

year under the propulsion of the twin engines

of design innovation and process-driven min-

iaturization. He revised his prediction in 1975,

asserting that transistor count would double

only every two years from then on. In 1972,

IBM’s Robert H. Dennard established a simple

set of rules by which a MOS device could be

scaled from one generation to the next.

These two laws solidly laid out all the nec-

essary foundations of the semiconductor indus-

try. Indeed, a multitude of companies ventured

into the semiconductor business attracted by

the promise of smaller, faster and cheaper tran-

sistors being easily realizable.

Which other industry can double the num-

ber of components per unit area every two

years with a minimal increase in cost?

For these reasons, the early versions of the

ITRS concentrated on scaling of DRAM, Flash

and microprocessor products. The magic com-

bination of silicon wafers, silicon dioxide as gate

insulator and polysilicon as gate conductor with

the addition of aluminum interconnections con-

stituted the perfect recipe to make any IC.

But everything eventually reaches a final

limit, and potential limitations of the MOS

technology were already apparent in the late

’90s and clearly predicted by the ITRS. In the

first historical meeting of the ITRS in July 1998,

it was clearly outlined that a new approach to

scaling—dubbed “equivalent scaling”—needed

to be introduced to continue moving the

semiconductor industry forward at the speed

of Moore’s Law. The ITRS quickly formed a

working group on Emerging Research Devices

(ERD) that subsequently turned into a full-

fledged ITWG. This was soon followed by the

Emerging Research Materials (ERM) ITWG.

The first limitation was overcome at the end

of the previous century with copper to replace

aluminum for interconnects. In addition, the

thickness of the SiO2 had reached the 1 nm

range by the end of the ‘90s, meaning that only

4-5 atoms were separating the polysilicon from

the silicon substrate. It was apparent that as the

thickness of the oxide continued to decrease, by

the middle of the next decade its value would

reach one atom and then “nothing more.”

The introduction of strained silicon in 2003

bought the industry some time to continue

improving transistor performance without

further decreasing the thickness of the SiO2

insulator. This creative invention was followed

by the great success of replacing the silicon

gate insulator with a material of a higher

dielectric constant (a hafnium-based material).

This was done in 2007 in conjunction with the

use of new metal gate materials for P and N

channels. Finally, in 2011, multi-gated MOSFETs

(MuGFETs) were introduced into manufactur-

ing. This approach reduces transistor leakage

induced by short channel effects.

You will also find that the scope of the

Radio Frequency (RF) and Analog/Mixed-

Signal (A/MS) chapter has been extended to

include the challenges of keeping wireless

communications on the leading edge of tech-

nology in the globally interconnected world.

In addition, a new chapter on Micro-Electro-

Mechanical Systems (MEMS) has been officially

added to the 2012 ITRS. This chapter, along with

other sections in various ITRS chapters, extends

the influence and guidance into this rapidly

growing segment of the total solution. It is a

subset of an arena of devices that has become

known as “More than Moore,” which also

includes A/MS, passives, high-voltage power,

sensors/actuators (key for MEMS), and biochips.

Happy reading!

• link to ITRS 2012 Overview

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Welcome to this issue of Future Fab

International featuring the updated 2012

International Technology Roadmap for

Semiconductors (ITRS). This year we celebrate

the 20th anniversary of technology roadmap-

ping!

You will discover that the number of

International Technology Working Groups

(ITWGs) continues to grow; from the initial 11,

we have now reached 17 as the ITRS continues

to expand in order to represent the evolving

semiconductor industry.

The first version was published in 1992

as the National Technology Roadmap for

Semiconductors (NTRS). At that time, multiple

versions of a long-term technology roadmap

existed in the United States and elsewhere, since

industry, academia and national laboratories

used to produce their own specific versions of

what the future of technology was going to be.

This multitude of technology roadmaps

created a great level of ambiguity and confu-

sion for the readers, especially among those

that were responsible for allocation of research

funds. Therefore, in a historical workshop

held in 1991, it was decided to create a unified

vision, which led to the first NTRS.

Two additional versions of the NTRS

were generated in 1994 and 1997. However,

in the 1990s the semiconductor industry had

become truly international, so in 1998, as newly

appointed chairman of the NTRS, I proposed

the internationalization of the roadmap to cre-

ate the ITRS. The proposal was accepted by

the World Semiconductor Council (WSC) and

was ratified in 2000.

http://www.future-fab.com/?d5023


5www.future-fab.com |

CONTENTS | FUTURE FAB International | Issue 44

2 Special Introduction Paolo Gargini – Stanford University

FUTURE VISIONS & CURRENT CONCERNS

13 Introduction Gilbert Declerck – imec

14 Environment, Safety, & Health Leo T. Kenny,1 Steve Moffatt,2

Hsi-An Kwong3 – 1Intel Corp. 2Applied Materials 1ISMI

19 RF and A/MS Technologies Herbert S. Bennett,1 John J. Pekarik,2

– 1National Institute of Standards and Technology, 2IBM Corp.

NEW TECHNOLOGIES & DEVICE STRUCTURES

27 Introduction Daniel J.C. Herr – University of North

Carolina at Greensboro

28 Chapter Article Sponsor

Brewer Science

29 Emerging Research Materials C. Michael Garner1 Hiro Akinaga2 Paul

Zimmerman3 Daniel Herr4 – 1Garner Nanotechnology Solutions 2National Institute of Advanced Industrial Science and Technology 3Intel Corp. 4University of North Carolina at Greensboro

34 MEMS Michael Gaitan,1 Robert Tsai,2 Philippe

Robert3 – 1Institute of Standards and Technology 2TSMC 3CEA-Leti

40 Emerging Research Devices An Chen,1 Victor V. Zhirnov,2

James A. Hutchby,2 C. Michael Garner3 – 1GLOBALFOUNDRIES 2Semiconductor Research Corp. 3Garner Nanotechnology Solutions

DESIGN IMPLEMENTATION & PROCESS INTEGRATION

51 Introduction Liam Madden – Xilinx

52 Design and System Drivers Juan-Antonio Carballo,1 Andrew

B. Kahng2 – 1Broadcom 2University of California at San Diego

57 Modeling & Simulation Jürgen Lorenz – Fraunhofer IISB

MANUFACTURING: FABS, SYSTEMS & SOFTWARE

62 Introduction Alan Weber – Alan Weber & Associates


Total Facility Solutions

64 Factory Integration James Moyne – Applied Materials

70 Process Integration, Devices, & Structures

Kwok Ng,1 Charles Cheung2 – 1Semiconductor Research Corporation 2National Institute of Standards & Technology

Next generation lithography techniques continue to evolve, but IC makers need

solutions today that will keep them on their aggressive technology roadmaps.

Nikon understands that extension of ArF lithography is vital to maintaining

production timelines, and continues to evolve the Streamlign platform to meet this

challenge. Nikon immersion and dry ArF scanners based on this proven technology

satisfy the increasingly demanding

and ultra-high productivity are

Nikon. Evolution in Action. www.nikonprecision.com


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6 | FUTURE FAB International | ITRS Issue 44

CONTENTS | FUTURE FAB International | Issue 44

FRONT END OF LINE

73 Introduction John Schmitz – NXP Semiconductors


Nikon

75 Lithography Mark Neisser – SEMATECH


Hitachi

81 Front End Processes Mike Walden,1 Joel Barnett,2

Raj Jammy,3 Chris Hobbs3 – 1MEMC 2Tokyo Electron America 3SEMATECH

BACK END OF LINE

87 Introduction Dan Edelstein – IBM


Tokyo Electron

89 Interconnect Azad Naeemi,1 David J. Maloney,2

Michele Stucchi3 – 1Georgia Institute of Technology 2Intermolecular Inc. 3imec

METROLOGY, INSPECTION & FAILURE ANALYSIS

95 Introduction David G. Seiler – NIST

96 Metrology Alain C. Diebold,1 Christina Hacker2

– 1College of Nanoscale Science and Engineering, University at Albany 2National Institute of Standards and Technology

101 Yield Enhancement Lothar Pfitzner, Sabrina Anger –

Fraunhofer Institute for Integrated Systems and Device Technology (IISB)

ASSEMBLY, TEST & PACKAGING TECHNOLOGIES

105 Introduction William Chen – ASE (U.S.) Inc.


Rudolph Technologies

107 Assembly & Packaging W.R. Bottoms – Third Millennium Test

Solutions


Advantest

117 Test & Test Equipment Roger Barth – Micron Technology

123 Related Chapters

124 Advertisers Index

EDITORIAL PANEL | FUTURE FAB International | Issue 44

Paolo A. GarginiIEEE Fellow and IEC Fellow

Paolo Gargini recently joined forces with the electrical engineering staff of Stanford University after 34 years working at Intel Corp. During his tenure at Intel, he was director of technology strat-egy in Santa Clara, Calif., and was responsible for worldwide research activities conducted by uni-versities and consortia for the Technology and Manufacturing Group. Gargini received doctorates in electrical engineering and physics from the Università di Bologna, Italy.

Michel BrillouëtSenior Adviser, CEA-Leti

Michel Brillouët is a senior adviser with CEA-Leti. He joined CEA-Leti in 1999, where he man-aged the silicon R&D. Prior to joining CEA-Leti, he worked for 23 years in the Centre National des Télécommunications (France Telecom R&D Center), where he held different positions in micro-electronics research. He graduated from École Polytechnique.

Alain E. KaloyerosSenior Vice President, CEO and Professor, College of Nanoscale Science and Engineering; University at Albany

Alain E. Kaloyeros is professor, SVP and CEO of CNSE at the University at Albany-SUNY. He has authored and co-authored over 150 articles and contributed to eight books on nanosci-ence, holds 13 U.S. patents, and has won numerous academic awards. He received his Ph.D. in experimental condensed matter physics from the University of Illinois, Urbana-Champaign, in 1987.

Biographies of Future Fab’s Panel MembersFor the full versions of the following biographies, please click here.

Gilbert J. DeclerckExecutive Officer, imec; Member of the Board of Directors, imec International

Gilbert J. Declerck received his Ph.D. in electrical engineering from the University of Leuven in 1972. He has authored/co-authored over 200 papers and conference contributions. In 1993, he was elected fellow of the IEEE. Since July 1, 2009, Dr. Declerck has been executive officer imec and a member of the board of directors of imec International.

Didier LouisDeputy Director, Materials & Advanced Modules Laboratory & Public Relations Manager, Nanoelectronic Division; CEA-Leti

After working for three years at Thomson Electronic Tubes division, where the research empha-sis was on improvement and characterization of medical electronic tubes, Louis joined CEA-Leti (France) in 1985, where he received a Ph.D. in metallurgy/electrochemistry from the University of Grenoble. He has written more than 30 papers related to etching and stripping processing and has co-authored more than 60 scientific papers and eight patents.

http://www.future-fab.com/editorial.asp

8 | FUTURE FAB International | ITRS Issue 44 9www.future-fab.com |


Shishpal RawatChair, Accellera Director, Business-Enabling Programs; Intel Corp.

Shishpal Rawat is chair of Accellera, an EDA industry standards organization, and director of Business-Enabling Programs with the Design Technology Solutions group at Intel. He holds M.S. and Ph.D. degrees in computer science from Pennsylvania State University, University Park, and a B. Tech. degree in electrical engineering from the Indian Institute of Technology, Kanpur, India.

Jon CandelariaDirector, Interconnect and Packaging Sciences; SRC

Jon Candelaria is the director of the Interconnect and Packaging Sciences area for SRC. He has over 34 years’ experience in the electronics industry in a wide variety of engineering and manage-rial roles. He received his BSEE and MSEE from the University of New Mexico.

Yannick Le TiecTechnical Expert, CEA-Leti, MINATEC Campus

Yannick Le Tiec is a technical expert at CEA-Leti. He joined CEA-Leti in 1995 and received his Ph.D. in materials science and engineering from the Polytechnic Institute, Grenoble, France, and his M.S. in chemistry from the National School of Chemistry, Montpellier, France. He is a CEA-Leti assignee at IBM, Albany (NY) to develop the advanced 22 nm CMOS node and the FDSOI technology.

Alain C. DieboldEmpire Innovation Professor of Nanoscale Science; Executive Director, Center for Nanoscale Metrology, CNSE, University at Albany

Alain’s research focuses on the impact of nanoscale dimensions on the physical properties of materials. He also works in the area of nanoelectronics metrology. Alain is an AVS Fellow and a senior member of IEEE.

Thomas SondermanVice President, Manufacturing Systems Technology; GLOBALFOUNDRIES

Thomas Sonderman is the VP of Manufacturing Systems Technology for GLOBALFOUNDRIES. He obtained a B.S. in chemical engineering from the Missouri University of Science and Technology in 1986 and an M.S. in electrical engineering from National Technological University in 1991. He is the author of 43 patents and has published numerous articles in the area of automated control and manufacturing technology.

Rohan AkolkarSenior Process Engineer, Components Research; Intel Corporation

Dr. Akolkar is a senior process engineer in Components Research at Intel Corporation, Hillsboro, Ore. He received the Norman Hackerman Prize of the Electrochemical Society in 2004, and numer-ous Intel Logic Technology Development awards. He has authored more than 40 technical papers, invited talks, and U.S. patents in the area of electrodeposition.

Christo BojkovSenior Package Development Engineer, TriQuint Semiconductor

Dr. Christo Bojkov is a senior package development engineer with TriQuint Semiconductor. Christo has published over 30 publications and holds 15 patents. Since receiving his doctorate in chemical engineering, he has worked and taught in academia for over 10 years in physical chemistry and surface science.

Steve GreathouseGlobal Process Owner for Microelectronics, Plexus Corp.; Idaho

Steve Greathouse is the Global Microelectronics Process Technology manager at Plexus Corp. in Nampa, Idaho. He has published many articles on technical topics related to semiconductor pack-aging, failure analysis and lead-free packaging. Steve has a B.S. in electronic physics from Weber State University with advanced studies in material science and computer science.

Daniel J.C. HerrDirector of Nanomanufacturing Science Research, SRC

Dr. Herr is a pioneer in collaborative nanotechnology research. He is professor and chair of the Nanoscience Department at the new Joint School for Nanoscience and Nanoengineering in Greensboro, North Carolina. Until recently, Dr. Herr served as the director of Semiconductor Research Corporation’s Nanomanufacturing Sciences area. He received his B.A. with honors in chemistry from Wesleyan University in 1976 and his Ph.D. from the University of California at Santa Barbara in 1984.

William T. ChenSenior Technical Advisor, ASE (U.S.) Inc.

Bill Chen is senior technical advisor at ASE (U.S.) Inc. He is the co-chair of the ITRS Assembly and Packaging International Technical Working Group. Bill was elected a Fellow of IEEE and a Fellow of ASME. Bill received his B.Sc. at University of London, MSc at Brown University and Ph.D. at Cornell University.

Liam MaddenCorporate VP, FPGA Development & Silicon Technology; Xilinx, Inc.

Liam Madden is vice president of silicon technology in the programmable platforms development (PPD) group at Xilinx, with responsibility for foundry technology, computer aided design and advanced package design. He earned a BE from the University College Dublin and an MEng from Cornell University. Madden holds five patents in the area of technology and circuit design.

Alan WeberPresident, Alan Weber & Associates

Alan’s consulting company specializes in semiconductor advanced process control, e-diagnostics and other related manufacturing systems technologies. He was previously the VP/GM of the KLA-Tencor Control Solutions division, acquired from ObjectSpace in March 2000. Alan has a bach-elor’s and a master’s degree in electrical engineering from Rice University.

Yayi WeiSenior Member, Technical Staff; GLOBALFOUNDRIES

Dr. Wei is a senior member of the technical staff at GLOBALFOUNDRIES, investigating advanced lithography processes and materials. He has over 16 years of lithography experience, including DUV, 193 nm, 157 nm, 193 nm immersion, EUV and E-beam lithography. Dr. Wei has numerous publications and holds several patents in the field of lithography.

David G. SeilerChief, Semiconductor and Dimensional Metrology Division, NIST

David G. Seiler is chief of the Semiconductor and Dimensional Metrology division in the Physical Measurement Laboratory at the National Institute of Standards and Technology. He received his Ph.D. and M.S. degrees in physics from Purdue University and his B.S. in physics from Case Western University.




Giuseppe FazioAdvanced Process & Equipment Control Sr. Engineer; Micron Semiconductors Italy

With a laurea degree in applied physics from Milan University, Giuseppe has working experience in several sectors, from research to industry, and vast experience in industrial and scientific instru-mentation. He has authored/co-authored many articles, is an avid contributor at conferences and holds several patents in the semiconductor field.

Peter RabkinDirector of Device & Process Technology, SanDisk Corp.

Dr. Peter Rabkin is director of Device and Process Technology at SanDisk Corp., focusing on development of novel 3D memory technologies and products. He holds a master’s degree in physics from Tartu University and a Ph.D. in physics of semiconductors from the St. Petersburg Institute of Physics and Technology.

Sitaram R. ArkalgudDirector of Interconnect, SEMATECH

Dr. Sitaram R. Arkalgud is director of SEMATECH’s Interconnect Division. He has over 20 years of R&D and manufacturing experience within the chip industry. Arkalgud has a Ph.D. and a master’s degree in materials engineering from Rensselaer Polytechnic Institute, and a B.S. in metallurgical engineering from Karnataka Regional Engineering College, Surathkal, India.

Daniel C. EdelsteinIBM Fellow; Manager, BEOL Technology Strategy, IBM T.J. Watson Research Center

Dr. Edelstein is an IBM Fellow, and Manager of BEOL Technology Strategy at IBM’s T.J. Watson Research Center. He played a leadership role in IBM’s industry-first “Cu Chip” technology in 1997, in the introduction to manufacturing of Cu/Low-k insulation in 2004. Dr. Edelstein received his B.S., M.S., and Ph.D. degrees in applied physics from Cornell University.

Christian BoitHead, Semiconductor Devices at Berlin University of Technology, Germany

The Berlin University of Technology is an institution for research and development in the areas of device simulation, technology, characterization and reliability. Christian Boit received a diploma in physics and a Ph.D. in electrical engineering on power devices, then joined Siemens AG’s Research Laboratories for Semiconductor Electronics in Munich and has been a pioneer on photoemission.

Pushkar P. AptePresident, Pravishyati Inc.

Dr. Pushkar P. Apte is president of Pravishyati Inc., a strategy consulting firm focused on the high-tech industry. He received his master’s and Ph.D. from Stanford University in materials science and electrical engineering, and his bachelor’s degree in ceramic engineering from the Institute of Technology, Varanasi, India.

Dr. Jiang YanProfessor, IMECAS

Dr. Jiang Yan is a professor at the Institute of Microelectronics Chinese Academy of Sciences. He has authored and co-authored over 30 papers, holds 17 U.S. patents and five China patents. He received his Ph.D. in electrical engineering from the University of Texas at Austin in 1999.

Klaus-Dieter RinnenDirector/Chief Analyst, Dataquest

Klaus-Dieter Rinnen is director for Dataquest’s semiconductor and electronics manufacturing group. He received a diploma degree in physics with minors in physical chemistry and mechanical engineering in Germany, and a Ph.D. in applied physics from Stanford University.

John SchmitzVP & General Manager, Intellectual Property and Licensing; NXP

John Schmitz is VP and general manager of Intellectual Property and Licensing for NXP Semiconductors. He holds a master’s degree in chemistry from Radboud University of Nijmegen, Netherlands, and a doctorate in physical chemistry from Radboud University Nijmegen. Schmitz has authored more than 45 papers in various scientific journals and has written books on IC tech-nology and on thermodynamics.

Lode Lauwers Director Strategic Program Partnerships for Silicon Process & Device Technology, imec

Lode Lauwers has an M.S. in Electronics Engineering and a Ph.D. in Applied Sciences. He joined imec in 1985 as a researcher. Lode is currently Director Strategic Program Partnerships for Silicon Process and Device Technology at imec, managing imec’s core partner research program on sub-32nm CMOS technologies.

Ehrenfried Zschech Division Director for Nanoanalysis & Testing, Fraunhofer Institute for Nondestructive Testing; Dresden, Germany

Ehrenfried Zschech is the division director of Nanoanalysis & Testing at Fraunhofer INT in Dresden. He received his diploma degree in solid-state physics and his Dr. rer. nat. degree from Dresden University of Technology. Dr. Zschech has published three books and over 100 papers in scientific journals on solid-state physics and materials science.

Janice M. GoldaDirector, Lithography Capital Equipment Development; Intel Corp.

Janice Golda manages an organization responsible for creating strategies and working with Intel’s lithography, mask and metrology suppliers and subsuppliers to deliver equipment meeting Intel’s roadmap technology, capacity and cost requirements. She is a member of the Berkeley CXRO Advisory committee, is Chairman of the Board for the EUV LLC and holds one U.S. patent.

Luigi ColomboTI Fellow

Dr. Luigi Colombo is a TI Fellow working on the Nanoelectronic Research Initiative (NRI). He is author and co-author of over 130 publications, three book chapters, and holds over 60 U.S. patents. Dr. Colombo received his Ph.D. in materials science from the University of Rochester.

Warren SavageChief Executive Officer, IPextreme

Warren Savage has spent his entire career in Silicon Valley, working with leading companies includ-ing Fairchild Semiconductor, Tandem Computers and Synopsys, where he focused on the prob-lem of building a global scalable semiconductor IP business. In 2004, he founded, and still leads IPextreme in the mission of unlocking and monetizing captive intellectual property held within semiconductor companies and making it available to customers all over the world. He holds a B.S. in computer engineering from Santa Clara University and an MBA from Pepperdine University.



FUTURE VISIONS & CURRENT CONCERNSClick here to return to Table of Contents

Radio frequency (RF), high-frequency (HF) and analog/mixed-signal (A/MS) technologies have now become critical for the success of many semiconductor manufacturers, according to Herbert S. Bennett (NIST) and John J. Pekarik (IBM). This is mainly because fourth-generation cellphones and tablets have a much higher semiconductor content than the wireless devices of just a few years ago. Different technologies are capable of meeting the technical requirements, with time-to-market and system cost being the decisive factors in the technology selec-tion.

To reflect that changing reality, the scope of the ITRS section on wireless tech-nologies was broadened, such as increasing the coverage of analog technologies. The authors also look forward to future road-map updates, where they expect to include,

Gilbert Declerck Executive Officer, imec Member of the Board of Directors, imec international

for example, more of the technologies that support mesh networks using mobile mil-limeter-wave communications.

Also, Leo T. Kenny (Intel), Steve Moffatt (Applied Materials) and Hsi-An Kwong (ISMI) acknowledge that the 2012 update of the ITRS is in essence transitional, as the various working groups prepare for the major rewrite of the roadmap in 2013.

These authors of the Environment, Safety & Health (ESH) section describe how they prepare for a growing need to include issues of environmentally sustain-able fabrication. They have expanded the membership of the ESH Working Group to include all key stakeholders in the road-mapping process. Their aim is that this will help formulate ESH improvements that contribute to (or at least don’t conflict with) improved cost, performance and product timing.

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Peter RammHead of Silicon Technology and Vertical System Integration Department, Fraunhofer EMFT; Munich

Peter Ramm is head of the Silicon Technology and Vertical System Integration department of Fraunhofer EMFT (formerly IZM-M) in Munich. He received his physics and Dr. rer. nat. degrees from the University of Regensburg. Dr. Ramm has authored or co-authored over 100 publications, including three book chapters and 23 patents.

Davide Lodi Baseline Defectivity & Metrology Engineering Manager; Micron Semiconductors Italy

Davide Lodi is the baseline defectivity and metrol-ogy engineering manager at Micron F14, in Agrate, Italy. After graduating in physics from the University of Milan, he started working in 1997 for STMicroelec-tronics as a process engineer. After becoming the manager of Wet Processes and Metrology Engineer-ing at the NVM R&D Agrate site, he moved to Numonyx, which was acquired by Micron in 2010.

Stephen J. Buffat Staff Research Scientist, Lockheed Martin NanoSystems

Stephen Buffat is a staff research scientist and operations manager of the Jordan Valley Innovation Center for Lockheed Martin in Springfield, Mo. He is responsible for the startup and operation of Lockheed Martin’s nanotechnology facility and operation in Springfield, Mo. He has authored or co-authored numerous articles on photolithography, etch and 300 mm surface preparation process tech-nologies.

Steven E. SchulzPresident and CEO, Silicon Integration Initiative, Inc.

Since 2002, Steve Schulz has served as president and CEO of Si2, the leading worldwide consortium of semiconductor and software companies chartered to develop EDA standards. He has a B.S. in electri-cal engineering from the University of Maryland at College Park, and an MBA from the University of Texas at Dallas.


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Future Fab Special ITRS FocusFuture Fab Special ITRS Focus

The 2012 Environment, Safety & Health (ESH) section of the International Technology Roadmap for Semiconductors (ITRS) reflects the major changes that were begun in the 2011 roadmap, where many of the tactical short-term require-ment elements previously present were de-emphasized, with a renewed focus on the overall long-range strategic direc-tion for the semiconductor industry. Recognizing the significant directional change that 2011 represented and also being a minor edit year, the current road-map bears a close resemblance to its pre-decessor, and is essentially transitional as we prepare for the major rewrite of the roadmap in 2013.

Looking forward, then, we will be emphasizing the critical importance of leveraging the roadmap to drive proac-tive, integrative and technical solutions to address many future ESH challenges. Nevertheless, the core principles of suc-cessful ESH program execution remain largely independent of the specific tech-nology thrust advances to which they are applied. This also means that many of the ESH roadmap elements, such as the Difficult Challenges and the Technology

Requirements, are very similar to those in previous roadmap editions. Therefore, the fundamental ESH roadmap strategies we have historically employed to guide our approach in developing our long-range vision have not changed:• Understand (characterize) processes

and materials during the development phase.

• Use materials that are less hazardous or whose byproducts are less hazardous.

• Design products and systems (equip-ment and facilities) that consume less raw material and resources.

• Continue to ensure that factories are safe for employees and the surrounding communities.

In 2011, to better address our key chal-lenges of defining research needs, to determine technology requirements and to mitigate future regulatory and compliance restrictions, we added a new strategic ele-ment to our core strategies listed above. This new strategy included integration of the principles of “green chemistry” into the overall ITRS. The objective of this approach was to create a framework and process for the industry, aligning with a concept that

ITRS CHAPTER: Environment, Safety & Health

Leo T. Kenny,1 Steve Moffatt,2 Hsi-An Kwong3 1Intel Corp. 2Applied Materials 3ISMI

Table 1. ESH Requirements by Domain and Category

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17www.future-fab.com |16 | FUTURE FAB International | ITRS Issue 44

has been gaining acceptance in govern-ment, academia and other industries (such as pharmaceutical and chemical).

In fact, adoption of green/sustainable chemistry concepts naturally builds on the well-established business processes for ESH developed in the semiconductor industry over many decades, enabling us to drive consistency and alignment and to proactively address the growing complex-ity of regulations, restrictions and global compliance requirements.

For the roadmap, this means that EHS materials issues are addressed at the outset of the technology lifecycle (in the chemical and process design phase). By

applying and building on these strate-gies as essential elements to success, the industry continues to be an ESH as well as a technology leader. For many years, the semiconductor industry has adopted a business approach, where key ESH princi-ples are integrated into R&D, manufactur-ing technologies, products and services.

However, the unique challenge that we have faced since the early days of the roadmap in the ESH section—namely, how to comprehend and address various policy and regulatory issues—has not changed. As previously stated, any failure to do so could jeopardize the implementation of success-fully developed technologies. Our first step toward addressing this was in the 2009 ITRS, by the introduction of ESH Domains & Categories. This concept was extended

in 2011 by the introduction of two new sub-categories (“requirements have data” and “no data available”) to reflect the availabil-ity of roadmap quality goals and metrics to address the ESH goals presented.

Now moving forward, we are using the concept of the aforementioned green/sus-tainable chemistry to establish a consist-ent framework to address ESH issues. This does not diminish our foundational activity of comprehending the state of the global regulatory environment, but going for-ward, this characterization of the current landscape serves as a basis for projecting out key trends, as we identify future ESH challenges for the roadmap.

The ESH roadmap will continue to iden-tify challenges when new wafer processing and assembly technologies move through R&D phases and toward manufacturing insertion. Following the presentation of ESH Domains & Categories (including the sub-categories) in Table ESH2, ESH technology requirements are listed in Tables ESH3–7. Potential technology and management solutions to meet these challenges are pro-posed in Figures ESH1–3, and are essentially unchanged from 2011. As we have stated previously, effective resolution of these future challenges will be fully realized only when ESH concerns are integral to the technology design process, where we have the most impact and lower cost to effect change; hence our focus on green/sustain-able chemistry (and engineering).

That said, we have expanded our ESH Working Group membership to include all key stakeholders (process, equipment and facilities engineers; chemical/material and tool suppliers; and academic and consortia researchers) in the roadmapping process. This will enable ESH improvements to contribute to (or at least not conflict with) enhanced cost, technical performance and product timing. Roadmap requirements must inherently minimize risk, public and employee health and safety effects, and environmental impact. Successful global ESH initiatives must be timely, yet far-reaching, to ensure long-term success over the roadmap’s life, improving efficient use of industry resources and ensuring effec-tive decision making.

The ESH roadmap Domains remain essentially the same as they were in 2011 (shown in the table), which serve to unify ESH elements for the full require-ment set. However, the tables themselves remain in their simplified state, relative to previous years, due to the radical changes made in 2011. Even as we move toward a major rewrite of the tables in 2013, we will continue employing these Domain categories:• Restricted Chemicals: By nature, this

Domain highlights chemicals that fall into the Critical Category.

• New Chemicals: There are a variety of emerging chemicals and materials, the exact specifications and ESH properties of which are not always fully estab-lished when they enter into new pro-cess consideration.

• Nanotechnology: While formally only a subset of New Chemicals, there can be unique ESH considerations for nanome-ter-scale chemicals and materials, which merit their separation into their own Domain.

• Utilization/Waste Reduction: The fun-damental ESH strategies noted in the opening paragraph all have a prominent role in this Domain.

• Energy: Given the increasing attention to greenhouse gas control, carbon foot-print and related energy-control metrics, this area stands out as one deserving deeper attention at the Domain level.

• Green Fab: This is a broad—and at pre-sent not well-defined or universally agreed-upon—term meant to represent fab operations conducted with minimal ESH impact (and the process and eco-nomic benefits that may derive from such practices). This Domain includes sustain-ability issues, as well as the full lifecycle considerations for chemicals/materials, tools and processes, the full fab infra-structure, and the products derived from them. The lessons we learn from devel-oping integrated solutions at the fab level will be crucial to proactively addressing ESH challenges, which may or may not be soluble at the operational level.

We will continue to emphasize the criti-cal importance of defining research needs that ensure alignment of public/govern-ment policy expectations with future technology needs, where critical materials are needed or new materials required to assure future technology.

Emphasizing the distinction between green and sustainable chemistries will be a key role for the roadmap. So while the long-term ideal goal will be to strive for completely “green” materials, we will none-theless address ESH issues at the earliest possible time, to develop sustainable mate-rials and highlight the technical advantages that these new materials provide.

Determining how to specify technol-ogy requirements for non-quantifiable or

ITRS CHAPTER: Environment, Safety & Health Future Fab Special ITRS Focus

The ESH roadmap will continue to identify challenges when new wafer processing and assembly technologies move through R&D phases and toward

manufacturing insertion.



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non-data supported requirements (i.e., where no meaningful information exists), which are not representative of the over-all industry, or where there is insufficient data for defining a technical objective, is nonetheless important for ESH to at least provide a path toward obtaining data. This is where our role of defining the key char-acteristics of alternative assessment tools will be critical in developing predictive tools for materials selections.

Looking ahead to 2013 and beyond, the ESH TWG recognizes that the roadmap will undergo significant changes as we strive to focus on a more strategic, long-term agen-da that emphasizes the critical importance of employing novel technology solutions to ESH challenges to support and enable the advancement of future industry technology developments. This certainly applies to the 450 mm wafer transition, which represents a clear opportunity for driving ESH technol-ogy improvements. However, because this transition will touch many parts of the over-all roadmap, we did not deem it appropri-ate to create a separate Domain for it.

AcknowledgmentsThe authors would like to acknowledge

the efforts of the ITRS Environment, Safety & Health Working Group in making this article possible. A full list of members of the Environment, Safety & Health Working Group can be found here.

About the Authors

Leo T. Kenny Leo T. Kenny is chair of the ITRS ESH

International Technology Work Group (and U.S. ESH TWG). He is a senior materials development engineer for Intel’s Corporate

ITRS CHAPTER: Environment, Safety & Health

Future Fab Special ITRS Focus

Radio frequency (RF), high-frequency (HF) and analog/mixed-signal (A/MS) tech-nologies serve the rapidly growing com-munications and More than Moore (MtM) markets and represent essential and critical technologies for the success of many semi-conductor manufacturers. Communications products and emerging products with func-tionalities enabled by MtM, RF, HF and A/MS technologies are becoming key drivers for volume manufacturing.

Consumer products account for more than half of the demand for semicon-ductors. Fourth-generation (4G) cellular phones and tablets now have much higher semiconductor content and account for a very large fraction of the mobile market compared with only 5% of the market a few years ago. The iPad, for example, has more than 19 RF and A/MS front-end com-ponents.[1] The consumer portions of the RF and A/MS markets are very sensitive to cost. With different technologies capable of meeting technical requirements, time to market and overall system cost will govern technology selection.

The RF, HF and A/MS technologies pre-sented herein depend on many materials systems, some of which are compatible with complementary metal oxide semicon-ductor (CMOS) processing, such as SiGe; others have not traditionally been compat-ible with CMOS processing, such as those compound semiconductors composed of elements from groups III and V on the periodic table, and from other elements in group IV, such as carbon. Compound and carbon-based semiconductors become more significant as today’s emerging research devices, especially those devic-es based on the MtM technologies, are deployed in the marketplace.

2012 Update ScopeCompared with the scope of the RF and

A/MS International Technology Working Group (ITWG) for the 2011 ITRS, the scope for the 2012 Update includes both wireless and tethered RF, HF and A/MS technologies. The requirements for transceiver ICs are technology drivers that contribute substan-tially to the recent ITRS-defined MtM thrust.

ITRS CHAPTER: RF and A/MS Technologies

Herbert S. Bennett,1 John J. Pekarik2 1National Institute of Standards and Technology (NIST) 2IBM Corp.

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Materials Environmental, Safety & Health Group, where he focuses on enabling new materials development and green chemis-try. He holds a Ph.D. in physical inorganic chemistry, and formerly managed one of Intel’s Environmental Process Engineering Development groups.

Steve Moffatt Steve Moffatt is the ESH TWG co-chair,

and is CTO for front-end products at Applied Materials. With a Ph.D. in physics from St. Andrews University in Scotland, he is a veteran of Silicon Valley after 30 years with Applied Materials, working in every aspect of the semiconductor equipment business. Moffatt has led teams for two Queens Awards in the UK for Technology and Export, and holds a Dan Maydan Award for Excellence and three Applied Materials President’s Awards for Engineering, Manufacturing and Quality.

Hsi-An Kwong Hsi-An Kwong, P.E., is the ESH pro-

gram manager at the SEMATECH/ISMI ESH Technology Center. Kwong has been working in the semiconductor and elec-tronics industries in areas of environmental compliance, engineering, process develop-ment and operations. He has M.S. degrees in chemical engineering and environmental sciences.

• Link to 2011 ITRS ESH Chapter

• Link to 2012 ITRS Update






http://www.itrs.net/Links/2011ITRS/2011Chapters/2011ESH.pdf


Similar to the 2011 chapter, this 2012 ITRS RF, HF and A/MS Update covers the device technologies that support four analog-carrier frequency bands: low fre-quency (LF), 0.0–0.4 GHz; RF, 0.4–30 GHz; millimeter-wave (mm-wave), 30–300 GHz; and terahertz (THz), >300 GHz. Figure 1 lists a few examples of applica-tions for each of these bands.

Strictly speaking, RF covers the 0.4–30 GHz frequency range. However, consider-ing the mm-wave and THz applications, we should change the generic designation from the present RF to HF to reflect the much wider spectrum. The members of the

ITWG will develop a consensus for this ter-minology in the 2013 ITRS chapter, and in the meantime we welcome comments sent to [email protected] on the ter-minology for future editions prepared by members of this ITRS Working Group.

We present roadmaps for device tech-nologies, and not for applications or fre-quency bands. The device technologies are high-performance Si CMOS; high-voltage CMOS; high-performance group IV bipolar; III-V compound semiconductors, which include high-electron mobility transistors (HEMTs) and heterojunction bipolar tran-sistors (HBTs); and on-chip passives.

Analog - Carrier Frequency Bands

LF Analog

(0.0–0.4 GHz)

RF

(0.4–30 GHz)

Millimeter-Wave

(30–300 GHz)THz (>300 GHz)

Example Applications

Automotive

ControlsCellular 60 GHz Point-to-Point No Products Yet

On-Chip

RegulatorsWLAN Imaging

Power

Management

SerDes Automotive Radar

ADC, DAC Wireless Backhaul High-Bandwidth Converters

Figure 1. RF and A/MS scope in terms of the analog-carrier frequency bands, and examples of applications considered in formulating the RF and A/MS roadmap.

ITRS CHAPTER: RF and A/MS Technologies Future Fab Special ITRS Focus

Some portions of the roadmap for RF, HF and A/MS device technologies pertain more to prototype device technologies rather than the usual high-volume CMOS device technologies presented in most of the other ITRS chapters. The device technologies for emerging mm-wave con-nectivity and imaging that are part of the scope for the RF and A/MS ITWG currently lag technology and processing capabilities for reliable manufacturing.

Figures of merit (FoMs) for device tech-nologies that relate to those circuit-level FoMs needed to support the performance requirements of systems are what drive the RF, HF and A/MS roadmap. The FoMs included in the RF and A/MS roadmap are those FoMs for low-noise amplifiers (LNA), voltage-controlled oscillators (VCO), power amplifiers (PA), analog-to-digital converters (ADC), and serializer-deserializ-ers (SerDes).

10

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2010 2015 2020 2025 2030LN

A Fo

M [G

Hz]

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MG

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SiGe NPN

Figure 2. Low-noise amplifier performance comparing CMOS, SiGe and InP transistor roadmaps.



What’s New in This Update?This year, the RF and A/MS ITWG

accepted a challenge from the Semi-con duc tor Industry Association (SIA) to increase its treatment of analog technolo-gies. In response, its roadmap now includes applications spanning frequencies of 0–300 GHz, which are described in Figure 1.

All ITRS RF and A/MS roadmaps since 2003 included sections on RF MEMS. In April 2011, the International Roadmap Committee (IRC) created a new ITRS

Working Group on MEMS that includes RF MEMS. As a result, the RF MEMS roadmap now appears within the MEMS roadmaps. We refer readers to the Future Fab article for the 2011 RF MEMS roadmap.

CMOS Technologies – The 2012 updated technology requirements tables reflect the RF and analog performance metrics needed to support the technology roadmap developed by the ITRS Process Integration, Devices and Structures (PIDS) Working


0

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SiGe NPN

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ar P

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M [G

Hz2-

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m]

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Power Amplifier Performance

Figure 3. Power amplifier performance comparing CMOS with InP and GaN HEMT transistor roadmaps.

Group. These performance metrics include maximum transit or cutoff frequency (fT), unity power gain maximum frequency (fMAX), minimum noise figure (NFMIN), analog gain, flicker noise and threshold volt-age matching. Compared with the 2009 roadmap, fT increased faster in the 2011 roadmap and in the present 2012 Update roadmap.

The 2012 updated RF, HF and A/MS technology requirement tables have para-sitic resistances and capacitances needed to support the ITRS Interconnect and Front End Processing (FEP) roadmaps. The 2013 roadmap will give the perfor-mance FoMs obtained from TCAD-based modeling and visualization methods that are similar to those used in the PIDS road-map. Also, the 2013 RF, HF and A/MS roadmap will include more details obtained from TCAD models for realistic layout and the resulting parasitic impedances.

It is instructive to consider two circuit-level FoMs, the values of which we can estimate using transistor-level FoMs. First, the upper limit of low-noise ampli-fier (LNA) FoMs allows us to compare the performance potential of CMOS, SiGe high-speed (HS) NPN, and the InP HEMT (Figure 2). The sources for the data in Figures 2 and 3 are contained in the 2011 RF and A/MS roadmap tables for each technology. Figure 2 shows that CMOS is roughly equally suited for implementing a 60 GHz LNA when compared to the SiGe and III-V transistors.

Comparing Figures 2 and 3 shows that the results for power amplifiers (PAs) are different than those for LNAs. The FoM for power amplifiers can be estimated from device FoMs as described in the System Drivers Chapter. The technol-ogy comparison in Figure 3 now shows a clear advantage of InP and especially GaN

HEMTs over CMOS. Furthermore, SiGe NPNs are shown to perform equally well as GaN HEMTs.

These FoMs do not provide the whole picture, however. For example, they ignore the fact that the load resistance needed to achieve the assumed output power will be extremely low for silicon devices and essentially illustrate an unrealistic design point.

CMOS technology performance for the PA application is projected to roll off dramatically with technology scaling. This highlights the fact that, though bandwidth might be high, the transistor gain is limited by its low frequency value. The suitability of CMOS relative to other device technolo-gies to implement a given application will depend on performance, and on other factors such as cost and integration level. Other changes include a more rigorous attempt to predict the effects of parasitic resistances and capacitances, and the observations that fT increases faster com-pared with the 2009 roadmap and that fMAX is lower in the near term because of parasitic effects.

High-Voltage MOS Technologies – The HVMOS section that was new in 2011 includes both HVNMOS and HVPMOS devices for power management and display-driver applications. The FoMs pre-sented in this section are BVDSS, RON x area with the framework of the integrated CMOS node. The 2012 Update HVMOS roadmap is essentially the same as the 2011 roadmap. We expect that the 2013 HVMOS roadmap will include higher volt-ages and automotive and industrial appli-cations. Because of these additions, the devices and FoMs in the revised HVMOS roadmap for 2013 will have an impact on the passive devices roadmap.



Group IV Bipolar Technologies – Only minor changes occurred in the 2012 technology requirement tables. For high-speed NPN transistors, changes included a one-year delay for the increase in fT, and updating parameters related to fT such as WE, BVCEO, BVCBO, JC at peak fT, NFMIN and SLi. For high-speed PNP transistors, we updated the linearity effi-ciency fLE. The contributors to the road-map expect major changes for high-speed NPN and PNP bipolar transistors, including moving to a roadmap based on TCAD and compact modeling simulations; moving to performance plateaus every three to four years that are linked to applications and the foregoing system drivers; and evaluating the effects of back-end-of–line (BEOL) parasitics on RF FoMs, as is done for CMOS.

III-V Compound Semiconductor Technologies – We have assumed “pro-duction” implies that at least one company offers products with data sheets or that the technology is available for custom designs from one or more companies as a foundry service. Even though the III-V technology tables involve analog, micro-wave and mm-wave applications, the emphasis is on mm-wave applications for this update. The production dates for scaled InP HEMT and GaN HEMT shift by one year later, primarily driven by the pull for these technologies.

The III-V roadmap truncates at the fol-lowing expected ends of scaling: GaAs pseudomorphic HEMT (PHEMT) in 2015, GaAs power metamorphic HEMT (MHEMT) in 2019, and InP power HEMT in 2013. This is primarily due to the projected replace-ment of GaAs PHEMT, power MHMET and InP power HEMT by GaN for power appli-cations and replacement of GaAs PHEMT

by InP HEMT and MHEMT and even GaN for low-noise applications. We expect that low-noise GaAs MHEMT and InP HEMT, InP HBT and GaN HEMT will continue with physical scaling.

For HEMTs, the 2012 Update, as in the past, has only D-mode FETs. The FoMs depend on technology, and include fT, fMAX, gm, IMAX and VBD; power, gain and efficiency at 10, 24, 60, 94, 140 and 220 GHz; NFMIN and GA at 10, 24, 60 and 94 GHz; and LNA NF and GA at 140 and 220 GHz. We plan to add E-mode devices in the 2013 roadmap. On-Chip Passive Device Technologies—This technology area has had no major revisions since 2011. The updated 2012 technology requirement tables emphasize on-chip passive devices and refresh the values for FoMs as functions of technol-ogy nodes (time). We will synchronize the 2013 roadmap for passive devices with the application-based framework of the RF, HF and A/MS chapter by capturing the unique requirements of the applica-tions and by reflecting the silicon, III-V and HVMOS performance metrics needed to support those applications.

2012 RF, HF and A/MS TrendsIn coming years, the members of the

RF and A/MS ITWG expect to expand their interactions with both the Metrology and the Modeling and Simulation TWGs. The meas-urements of device parameters at frequen-cies in the mm-wave bands are becoming necessary both to understand the physical mechanisms limiting device performance and to accurately simulate this performance. Commercial equipment capable of per-forming these measurements has recently become available for frequencies up to 750 GHz. However, such equipment has not


been in use long enough to establish stand-ardized methodologies for de-embedding device parameters from the parasitics.

There is a need for building a consen-sus and establishing standardized meth-odologies. Even below 50 GHz, a con-sensus is limited at best, and a standard methodology does not exist. Production measurements above 50 GHz are practi-cally non-existent. International standards will play an even more significant role for addressing these challenges. International standards and their associated measure-ment methods are key enablers for suc-cess at all stages of RF and A/MS innova-tion—from research, development, initial deployment, high-volume commercializa-tion and end of initial useful life, to recy-cling and disposal. Standards can ensure interoperability and reduce the number of times different designs are implemented, thereby freeing RF, HF and A/MS engi-neering resources to innovate where it will be a true differentiator.

Those working on RF, HF and mm-wave characterization have requested improve-ments in measurement equipment and associated standards to accurately assess performance FoMs. Requests include:• Improved dynamic ranges in small-

signal measurements, equipment and methodology.

• Improved measurements and instru-mentation in the mm-wave range for noise performance characterization. Noise sources above 200 GHz are not readily available.

• Development of large-signal network analysis for mm-wave frequencies. This would let designers see the voltages and currents inside nonlinear devices under operating conditions and develop large-signal models to optimize effi-ciency and linearity at the same time.

• Improved signal measurement tools to allow standardization of modulation formats.

Mesh networks using mobile mm-wave communications are very promising solu-tions for addressing the spectrum crunch. Because of this, there is a lot of explora-tory work being done on mobile devices at millimeter wavelengths. We expect to include more of the technologies that sup-port mesh networks in future RF and A/MS roadmaps. Though we are still a long way from this goal, there are several innova-tions that will assist in attaining this goal:• Integrating SiGe HBTs into CMOS to get

the best of both worlds.• Silicon digital processing power to

enable inherently nonlinear but efficient transmitters to behave linearly.

• Multiple-input multiple-output (MIMO) systems to get the connectivity in chan-nels that are characterized by high multipath and fading, and to make the most of the silicon processing power and small antenna size.

The Emerging Research Devices (ERD) and Emerging Research Materials (ERM) groups use the concept of the future RF transceiver as the context in which to con-sider selected new devices and materials for RF applications that are within the MtM domain in the ITRS. The following emerg-ing technologies are future candidates for RF transceiver functions of transistors, mixers, local oscillators and resonators:• Sub-100 nm carbon-based FET tech-

nology might be able to address HF applications such as LNAs, mixers and PAs if their superior intrinsic material properties vs. silicon properties can be accessed through suitable processing steps.



NEW TECHNOLOGIES & DEVICE STRUCTURESClick here to return to Table of Contents

This year marks the 20th anniversary of the first meeting of the National Technology Roadmap for Semiconductors (NTRS) and the 15th anniversary of the International Technology Roadmap for Semiconductors (ITRS). Perhaps more importantly, it also marks the Emerging Research Device (ERD) and Emerging Research Materials (ERM) teams’ 12th and sixth year, respectively, as ITRS Working Groups and, coincidentally, the sixth year since the ITRS announced the expansion of its scope to include More-than-Moore (MtM) technologies. In December 2006, the ITRS public presentation included a schematic of its scope similar to the one shown in Figure 1, which was presented at the ITRS 2012 rollout meeting recently in Hsinchu, Taiwan.

Although scaling likely will continue for the current ITRS time horizon, we also might be entering a new era of integrated systems. From this year’s rollout meeting, there was a growing consensus on the need for combining system-on-a-chip (SoC) and system-in-a-package (SiP) technologies to yield higher-value systems. The coordina-tion of ERD, ERM and MtM roadmap activi-ties with work underway in relevant external sectors (e.g., in healthcare, energy, transpor-tation, etc.) will help the ITRS community move toward achieving this goal.

For example, several years ago, Semiconductor Research Corp. and the National Institute of Standards

Daniel Herr Professor, UNCG/Joint School of Nanoscience and Nanoengineering

and Technology (NIST) organized two Bioelectronics Round Table (BERT) events, which brought together colleagues from the nanoelectronics and biotechnology communities to prioritize research needs at the interface between these convergent technology sectors. This effort identified three specific win-win research opportuni-ties that would address high-impact needs in the healthcare community (e.g., personal-ized medical diagnostics and monitoring, prosthetics and implantable devices, and multi-scale medical imaging) by leveraging the semiconductor industry’s high-volume nanomanufacturing infrastructure. The ITRS community has an opportunity to lead this effort by reaching out to colleagues in adja-cent sectors and co-developing a series of system roadmaps for technology inte-gration (SRTI) that identify specific needs and application horizons at the interfaces between convergent sectors, with high impact potential.

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Combining SoC and SiP: Higher-value systems

Non-digital contentSystem-in-package

(SiP)

Digital contentSystem-on-chip

(SoC)

Interacting with people and environment130 nm

---V

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90 nm

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logi

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Informationprocessing

BiochipsSensors

Actuators[e.g. MEMS]

HVPowerPassivesAnalog/RF

More than Moore: Diversification

• Nanometer-sized spin-torque oscilla-tors (STOs) are likely to have low phase noise and be tuned from 0.1 GHz to >40 GHz by external magnetic fields, spin-torque currents, and magnetic materials and structures.

• Resonators made from NEMS devices (nano-resonators) will be used for RF filters that we expect will have high Q values and will ultimately be tunable. Materials of interest for this application include silicon nanowires, III-V com-pound semiconductor nanowires, car-bon nanotubes and graphene.

AcknowledgmentsThe authors would like to acknowl-

edge the efforts of the ITRS RF and A/MS Working Group in making this article pos-sible. A full list of members of the RF and A/MS Working Group can be found here.

References1. “Global and China GaAs-Based Device

Industry Report, 2011-2012,” The Business Journals, May 28, 2012.

2. P.H. Singer, “Dramatic Gains in Performance on the Horizon,” Semiconductor International, Vol. 29, No. 8, July 2006, p. 15.

About the Authors

Herbert S. BennettHerbert S. Bennett, A.B. and Ph.D.

from Harvard University, and M.S. from the University of Maryland, is a NIST Fellow and executive advisor in the Semiconductor and Dimensional Metrology Division of the Physical Measurement Laboratory at the National Institute of Standards and Technology. He is a Life

Fellow of the Institute of Electrical and Electronics Engineers and a Fellow of the American Physical Society and the Materials Research Society. Bennett’s cur-rent interests include More than Moore applications of nanoelectronics, medi-cal imaging, international standards for nanoelectrotechnologies, and technology roadmaps for semiconductors, energy and healthcare.

John J. (Jack) PekarikJack Pekarik joined IBM in 1985 and

received his Ph.D. in electrical engineering from UC Santa Barbara in 1993 while on leave. He has worked on technology for bipolar, DRAM and CMOS in bulk and SOI, compact modeling and manufacturing, and now works on SiGe BiCMOS in Burlington, Vt. Pekarik is chairman of the ITRS TWG on RF and A/MS Technologies for Wireless Communications.

• Link to 2011 ITRS RF and A/MS Chapter



ITRS CHAPTER: RF and A/MS Technologies

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http://www.itrs.net/Links/2012ITRS/2012Tables/RFAMS_2012Tables.xlsx



http://www.itrs.net/Links/2011ITRS/2011Chapters/2011RFAMS.pdf


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EMERGING RESEARCH MATERIALS


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Publication of this special Future Fab ITRS article is sponsored by Brewer Science

The Emerging Research Materials (ERM) Technology Working Group (TWG) does not plan to make any updates or changes to the 2011 ERM chapter, but is focused instead on collecting input on changes in materials and technology status for the 2013 ITRS rewrite. The ERM group has participated with the Emerging Research Devices (ERD) group in several work-shops, and we are holding e-workshops on materials for Lithography, Front End Process, Interconnects, and Assembly and Packaging. The goal is that these work-shops will enhance the chapter with the latest industry materials and trends.

Emerging Research Device Materials

In 2012, we participated with the ERD TWG in workshops on memory select devices, storage class memories, and logic devices, and will be identifying material requirements for the devices covered. ERM is planning workshops and updates on materials for alternate channel materi-als for extending CMOS, charge-based beyond CMOS, and non-charge-based

beyond CMOS. For memory devices, we’re planning e-workshops on spin materials for out-of-plane spin-transfer torque (STT), complex metal oxides for resistive RAM (RRAM), and novel materials for memory select devices. For alternate channel mate-rials, ERM is planning updates on carbon-based device (graphene and carbon nano-tube) materials, semiconductor nanowires, p-channel III-V materials, nanoscale con-tacts, and modeling of ultra-high-k dielec-trics. For beyond CMOS, ERM is planning updates on properties of spin materials, strongly correlated electron materials, semiconductor spin properties, and inter-face coupling between materials.

Lithography MaterialsThe ERM and Lithography TWGs have

agreed that ERM will continue to assess new resist and lithography materials for 193 nm and extreme ultraviolet (EUV) lithography technologies. The 2013 ERM chapter will include photolithography materials (resists and hard masks) for 193 nm and EUV, and materials for directed self-assembly (DSA).

ITRS CHAPTER: Emerging Research Materials

C. Michael Garner1 Hiro Akinaga2 Paul Zimmerman3 Daniel Herr4

1Garner Nanotechnology Solutions 2National Institute of Advanced Industrial Science and Technology 3Intel Corp. 4University of North Carolina at Greensboro

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193 nm Extension and EUV Lithography Materials

The ERM TWG is holding several tel-econferences in 2012 and early 2013 to update the status of photoresist and hard mask materials for 193 nm and EUV lithog-raphy. We completed one e-workshop on nanocomposite resists and inorganic-organic hybrid resists. The status of more conventional resist materials will be updated after the 2013 SPIE Advanced Lithography conference in late February.

Nanocomposite resists with ~2 nm par-ticles of HfO2 or ZrO2 have demonstrated improved sensitivity and resolution through the use of new ligands with these nanoparti-cles. These resists can be used with 193 nm, EUV and e-beam lithography as positive- or negative-tone resists. Applications using negative or positive resists require the use of different development techniques and development chemistries. These nanocom-posite resists also have an increased plasma etch resistance, which might improve their utility in advanced lithography.

Inorganic-organic hybrid (HfO2-based) resists are also demonstrating improved resolution and sensitivity; however, resolu-tion and sensitivity are trade-offs just as they are with conventional resists. These materials also can have dramatically higher etch resistance than SiO2, and it is pos-sible to use them as hard masks with pat-terned photoresists.

DSA Materials for Lithography Extension

Since the ERM chapter was written in 2011, DSA with block-copolymers and pol-ymer blends continues to make progress. An important milestone in 2011 was the demonstration that defect densities can be reduced to <25 cm-2 by eliminating parti-cle-related defects. However, it still must

be demonstrated that defect levels can be reduced to ITRS levels in a cleanroom with track dispense. Multiple teams are work-ing to determine whether low defect levels can be demonstrated with clean processes in cleanroom environments.

Additionally, with the growing interest in the use of DSA for contacts and vias, more cross-sectional data is needed to prove that patterns are formed through the entire depth of the structure. Top-down SEMs are of little use for evaluating contact formation.

Since interest in DSA is increasing rap-idly, ERM has surveyed groups that have internal projects to assess DSA and also to identify pre-competitive issues vs. com-petitive technology capabilities.

The first survey was to discover whether companies had specific plans to evalu-ate contact or via rectification, line edge roughness (LER) improvement or pattern density multiplication in their organization. Contact or via rectification is the patterning of “large” contact structures with photoli-thography, using DSA to form small contact structures with a tight distribution of sizes (determined by the polymer molecular weight). LER improvement patterns lines with photolithography, and then uses DSA to assemble polymers with reduced line edge and width roughness. Pattern density multiplication is used to lithographically gen-erate a sparse pattern with large features on a wafer and have DSA create smaller struc-tures with higher density than is possible with the lithography technique.

As shown in Figure 1, survey respond-ents had the most interest in contact or via rectification and pattern density multi-plication. There was some interest in LER/LWR improvement, however.

A second poll identified pre-competi-tive areas that consortia should work on.

ITRS CHAPTER: Emerging Research Materials Brewer Science: Where Innovation Takes Flight!SM

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Though industry did identify several areas that they considered to be competitive and thus proprietary, the following areas were considered pre-competitive: defects, material specifications, simulation, metrol-ogy (2D and 3D), design tools, high (phase segregation energy) block co-polymers, and prediction and modification of sur-face energy to control morphology. Other areas, including design rules, photomask design tools, rework processes, and hard mask layers, were viewed as competitive. Clearly, metrology tool manufacturers would view defect metrology as a com-petitive area, so many of the “pre-compet-itive” areas would be competitive in other business segments.

ERM will have further meetings to review progress on this technology.

Front End Process MaterialsThe ability to produce conformal

dopant deposition on 3D structures is important as multi-gate structures are introduced and scaled to high densities.

The ERM TWG continues to monitor pro-gress on monolayer doping and deter-ministic doping (the ability to precisely control dopant locations in devices). In addition to wet processing to achieve monolayer doping, vapor phase deposi-tion, atomic layer deposition (ALD) and other techniques are being investigated. Similarly, ERM is evaluating combining directed self-assembly with monolayer doping to place dopants in precise loca-tions in MOSFET channels and source/drain regions. We are planning a work-shop on this in February 2013 in the San Francisco Bay area.

In addition, ERM is planning an e-work-shop on modeling high-k dielectrics to identify potential materials for second-generation gate applications.

As devices scale to sub-10 nm dimen-sions, contact resistivity could limit the performance of devices, so the ERM group is planning a workshop on contact resistiv-ity in spring 2013 to identify concepts that could solve this potential issue.

0

2

4

6

8

10

12

14

No Maybe Yes No Maybe Yes No Maybe Yes

Contact or Via Rectification LER/LWR Improvement Pattern Density Multiplication

Plans to Evaluate Directed Self-Assembly

Industry Total

Figure 1. IC industry and consortia members were polled to determine whether they had specific plans to evaluate DSA for 1) contact or via rectification, 2) line edge roughness (LER) improvement, or 3) pattern density multiplication. This was a non-scientific poll that could have input from more than one person at a company or institution.




Interconnect MaterialsThe ERM group is evaluating materials

to extend copper interconnects and inter-level dielectrics, and also possibly native materials to interconnect future novel devices. In 2012, the ERM held e-work-shops on novel low-k dielectrics and also ultra-thin copper diffusion barrier layers.

Graphene and carbon nanotubes are being evaluated for potential application as device interconnects. However, sig-nificant challenges must be overcome for them to be viable. We had an e-workshop on this in November to assess progress on improving material performance and to evaluate concepts for overcoming quan-tum resistance issues.

Assembly and PackagingA critical challenge for the Assembly

and Packaging TWG is to identify “zero residue” adhesives that could be used in a number of applications. The ERM and Assembly and Packaging TWGs held a joint review of polymer research to iden-tify concepts that could be applied to pro-viding these adhesives.

Concepts for stimulus-activated adhe-sive release included thermally or photon-activated mechanisms. Though these polymer adhesives might not have the complete set of properties, the strategies could be applied to other polymers that might better meet thermal and residue requirements. Since achieving “zero” resi-due after release might be impractical, the viable options could include use of a light O2 plasma or rinse with an ESH-benign solvent or clean.

The Assembly and Packaging group also needs materials for low-assembly-temperature electrical interconnects and package polymers (<200°C) that can be applied and cured at these temperatures.

It is critical that electrical interconnect materials have low electrical resistance and contact resistance, high electromi-gration resistance, and high resistance to fatigue. Other materials needed include electrically insulating materials with a high lateral thermal conductivity, and a mold-ing compound that is resistant to moisture absorption and mobile ions.

Metrology and Modeling New metrology is needed to charac-

terize the properties and performance of materials and interfaces at the nanometer scale. Modeling and simulation are needed to assess the properties and performance of materials as a function of composition, size, structure and interface.

Environment, Safety and Health (ESH)

The ERM TWG is preparing to update the emerging materials’ earliest potential intercept table to help the ESH TWG iden-tify when to assess potential issues and trade-offs in their implementation, and to include sustainable and green chemistry principles in the ITRS.

AcknowledgementsThe authors would like to acknowledge

the efforts of the ITRS Emerging Research Materials Working Group in making this article possible. A full list of members of the Emerging Research materials Working Group can be found here.

About the Authors

C. Michael GarnerMichael Garner is a visiting scholar at

Stanford University, and a consultant for Garner Nanotechnology Solutions. He is also

ITRS CHAPTER: Emerging Research Materials Brewer Science: Where Innovation Takes Flight!SM

| www.brewerscience.com

co-chair of the ITRS Emerging Research Materials (ERM) Technology Working Group. He previously worked for Intel, most recent-ly as program manager of External Materials Research. Garner received his Ph.D. in mate-rials science and engineering from Stanford University in 1978.

Hiro AkinagaHiro Akinaga is director for the

Innovation Center for Advanced Nanodevices at AIST, and is co-chair of the ITRS Emerging Research Materials (ERM) Technology Working Group. He has B.E., M.E. and Ph.D. degrees from the University of Tsukuba in Japan, and has been appointed to professorships at the University of Tokyo (2001), Tokyo Institute of Technology (2002-2004) and Osaka University (2008, 2010).

Paul ZimmermanPaul Zimmerman has worked for

Intel since 1994, starting in the Portland Technology Development group. During his time at Intel, he has worked to devel-op materials, tools and processes for FEOL, BEOL, metrology and lithography. Zimmerman received his B.S., M.S. and Ph.D. in chemistry from the University of Pittsburgh. He also completed an MBA in 2000 at Arizona State University.

Daniel J.C. HerrDaniel Herr recently joined the

University of North Carolina’s new Joint School of Nanoscience and Engineering (JSNN), where he serves as professor and founding Nanoscience department chair. In this role, he is building a highly collaborative and interdisciplinary team that explores and addresses emerging, high-impact More-than-Moore applica-tion opportunities. He also continues to

serve as an adjunct associate professor in the Materials Science and Engineering department at North Carolina State University, where he co-teaches classes on smart materials and nanoelectronics. Prior to joining the JSNN, Herr served as Semiconductor Research Corp.’s director of Nanomanufacturing Sciences area.

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MEMS are fabricated using techniques similar to those used for ICs to create micrometer-sized mechanical structures (suspended bridges, cantilevers, mem-branes, fluid channels, etc.) that are often integrated with analog and digital cir-cuitry. MEMS can act as sensors, receiving information from their environment; or as actuators, responding to a decision from a control system to change the environment.

The ITRS has organized a MEMS Technology Working Group (TWG), which has developed a new chapter on MEMS for its 2011 report. The report focuses on MEMS technologies associated with mobile Internet devices, such as smartphones and tablet computers. These applica-tions represent the fastest growing seg-ment in MEMS manufacturing, according to 2011 market forecasts by iSuppli, Yole Développement and SEMI.

The report focuses on the leading MEMS devices used in mobile Internet applica-tions: accelerometers and gyroscopes, microphones, and RF MEMS, including reso-nators, varactors and switches. The report

also reviews emerging MEMS applications, including optical filters, picoprojectors, the electronic nose, microspeakers and ultra-sound devices.

Difficult ChallengesThe ITRS MEMS roadmap considered

both the evolution of discrete MEMS devices and integrated MEMS technolo-gies. Here, the term “discrete” MEMS is used to refer to devices that perform one function. For the purposes of this discus-sion, a three-axis accelerometer with an integrated ASIC is referred to as a discrete MEMS device. “Integrated” MEMS refers to the integration of multiple types of sensing functions, such as accelerometer and gyro-scope, in the same package.

Discrete MEMS accelerometers, gyro-scopes and microphones are expected to see continuous incremental improvement in performance. MEMS three-axis accel-erometers are expected to see improve-ment in resolution, bias and drift, with resolutions improving by a factor of 2 from 1,000 μg to 500 μg by 2017. MEMS three-

ITRS CHAPTER:MEMS

axis gyroscopes are expected to see a continuous increase in resolution from 100 μ°/s/√Hz to 50 μ°/s/√Hz. MEMS micro-phones are expected to see an improve-ment in sensitivity from -42 dB (V/Pa) to -38 dB (V/Pa) at 1 kHz.

The greatest challenge faced by manu-facturers of discrete MEMS devices comes from the required cost and size reduc-tions. The cost of MEMS accelerometers and gyroscopes is predicted to lower from 60 to 20 cents and $2.70 to $1.20 per die, respectively, by 2017, with no known solu-tions at the present time.

RF MEMS resonators, varactors and switches are also expected to see a continuous incremental improvement in performance. The greatest challenge that these devices face in order to pen-etrate into the mobile Internet market is increasing their reliability, driving the need for reliability simulation tools and methods for accelerated lifetime test-ing. RF MEMS also specifically call out requirements for inductors with Q>50 integrated at the package level and methods for minimizing package inter-connect length and loading.

The greatest challenges by manufactur-ers of integrated MEMS technologies were in relation to their integration path toward the inertial measurement unit (IMU), a device that incorporates a three-axis accel-erometer, three-axis gyroscope, three-axis magnetometer (compass) and a pressure sensor (altimeter). The IMU is also referred to as a 10 degree of freedom (DOF) multi-mode sensor. Multimode sensor technolo-gies face challenges in assembly and pack-aging, but have known interim solutions over the near term. The greatest cause for concern for multimode sensor technologies relates to testing. The cost of testing has been continuously increasing, yet the price of the devices continues to fall—a trend that cannot be sustained. The challenges of testing are further compounded by the increasing complexity of the tests, which require testing the multiple functionalities (acceleration, angular rate, direction and elevation) of the IMU.

The trends of increasing device perfor-mance, reducing cost and size, and advanc-ing integration path in turn drive the require-ments for advances in design and simula-tion, packaging and integration, and testing.

Michael Gaitan,1 Robert Tsai,2 Philippe Robert3

1Institute of Standards and Technology 2TSMC 3CEA-Leti

Challenge Need

Assembly and Packaging can be

being

Table MEMS1. Summary of MEMS Difficult Challenges

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Design and SimulationContinuous improvement of simulation

tools: MEMS devices are expected to see a continuous incremental improvement in performance metrics. The simulation tools must also continuously improve in their capacity to predict those performance improvements. This will require improved links between device and system simula-tion; more specifically, the integration of finite element modeling with electronic computer aided design (ECAD) tools. Fabrication process modeling should also advance so that material properties and process-induced surface characteristics and stress fields can be more accurately predicted from a process flow.

Design for testability: A critical chal-lenge for MEMS devices is the cost of test-ing, which is already about one-third of the manufacturing cost and is continuing to rise, while the price of devices is expected to continue to drop. Furthermore, inte-grated 10 DOF multimode MEMS have no known solutions for testing. There has been a mantra in the MEMS community

that designing a new device requires consideration of the package at the start of the process. Now, this mantra should expand to include the need for designing for test at the start. There are no formal algorithms to design MEMS for test, espe-cially for integrated multimode MEMS sen-sors. The consensus opinion of the com-mittee is that as much testing as possible should be moved upstream in the process.

Design tools are needed to support this. There is also a call for “design for no test,” where research could further enable tech-niques to design systems that are self-test-ing and self-calibrating.

Simulation tools for predicting pack-aged device performance from wafer-level testing: Manufacturers typically test their devices after they are fully assembled and packaged—referred to as device-level test-ing. An important piece of addressing test-ing challenges is moving as much of the testing as possible to the wafer level, sim-plifying and reducing the burden of testing at the end. This will require validated simu-lation tools and methodologies to predict the effects of assembly and packaging from wafer-level test data.

Reliability simulation: Accurate predic-tive models using information from the design and fabrication process are needed in order to predict and optimize the reli-ability of MEMS. These models may also prove useful in developing accelerated reliability test methods. Addressing this need requires research and the advance-

ment of knowledge of the physics of fail-ure, so that the models can be developed.

Cost modeling for packaging and inte-gration: Cost analysis is an important methodology for ensuring that future predictions of the price of a MEMS com-ponent are consistent with the resources and technology needed to deliver it to the marketplace. Currently, the method-ology can be usefully employed to cost/

price discrete MEMS devices and predict the production developments needed for the immediate future. Advancing predic-tive models of integration paths for MEMS could be useful for technology roadmap-ping over the long term.

Packaging and IntegrationCost reduction: MEMS devices are

expected to see a continuous incremental improvement in performance while simul-

taneously requiring a reduction in package size and cost. The greatest challenges for discrete MEMS devices, with no known solu-tions, are in the latter: reduction in package size and cost. Advancement of assembly and packaging technologies and materials is required to meet these challenges.

Package standardization: MEMS tech-nologies require some sort of packaging standardization so that costs can be low-ered and the trend of a custom package for each MEMS device can be reversed. One suggestion, among many to consider, is a line of cavity-type packages starting at 3 x 3 mm and with 1 mm increments to 7 x 7 mm. Packages should include a data sheet with all parameters needed to accu-rately simulate the stress on the MEMS and predict the packaged device performance using wafer-level tests.

Package standardization of signal lines: As MEMS continue to advance in integra-tion and functionalities of the ASIC, stand-ardization of the signal lines and power handling will become increasingly desired.

The pull for this is likely to come from the integrated multimode sensors and the advancement of the ASIC toward micro-controllers. RF MEMS also see a unique need for inductors integrated in the pack-age with Q>50 and methods for minimiz-ing interconnect length and loading.

Advancement of 3D packaging tech-nologies (TSV): MEMS have 3D packaging requirements that surpass those for cur-rent ASICs and memories, especially with

the regard to package-induced mechanical stress on device performance.

TestingCost of test: The cost of testing con-

tinues to rise, yet the price of devices is expected to fall; this is not a sustainable situation. MEMS devices require not only electrical tests, but also need to be stimu-lated mechanically (i.e., shaken, rattled and rolled). These added requirements result in expensive handlers, which are the pieces of the automatic test equipment that provide stimulus and monitor responses of the devices. These handlers tend to be customized for each manufacturer. Standardizing the handlers and the test methods could lower costs considerably. The cost of testing is also influenced by the requirements for tests by the custom-er, which add expense but might not add any value. Standardizing tests on product performance, reliability and device data sheets can also significantly reduce the cost of testing.

ITRS CHAPTER: MEMS Future Fab Special ITRS Focus

A critical challenge for MEMS devices is the cost of testing, which is already about one-third of the manufacturing cost and is continuing to rise, while

the price of devices is expected to continue to drop.

The cost of testing continues to rise, yet the price of devices is expected to fall; this is not

a sustainable situation.



Wafer-level testing: Testing of inte-grated 10 DOF multimode MEMS sensors has no known solutions, and it is not clear that solutions can be developed using the standard approach, which is to conduct the testing at the end of the manufacturing process (device-level testing). A possible solution could be to move as much of the testing as pos-sible to the wafer level. This will require knowledge and predictive models of and/or the elimination of effects from assembly and packaging so that informa-tion from wafer-level testing can predict the final packaged device performance. The goal would be to make the final tests of the finished device a simple veri-fication of the expected performance. Wafer-level testing should also be used to feed data forward in earlier stages in the process, including to the designer, to improve designs and product yields.

Design for test: This is also referred to as self-test/self-calibration. This topic is covered in the section on possible solu-tions for design and simulation. There is

presently a lack of know-how for designing for testability and methods for self-test/self-calibration that can reduce the burden of test at the back end of manufacturing. Since design for test is very application-dependent, methodologies will need to be developed for each device technology.

Accelerated reliability test methods: There is a continuing need to extend knowledge of the physics of failure of

MEMS devices. This is especially relevant for RF MEMS devices, where their adoption in many applications has been hindered due to reliability requirements. Extending knowledge of the physics of failure will enable methods to improve device reliabil-ity and to develop accelerated reliability test methods. Specific knowledge of reli-ability metrics and test methods resides in companies, but this information is not typi-cally shared because it can be a commer-cial advantage to the company to keep it secret. Otherwise, the possible solution is to share the information that exists, evalu-ate gaps, and support R&D on developing knowledge for those areas that require it. Then this knowledge can be applied to the development of standardized accelerated reliability test methods.

Update for 2012The MEMS Technology Working Group

focused this year on a complete rewrite of the iNEMI MEMS Chapter, which includes a new discussion on MEMS for consumer medical applications and proposes the

idea of integration nodes as a path for MEMS sensor fusion modeled after the evolution of the IMU. The 2012 update to the MEMS technology roadmap leveraged this effort to update device performance metrics and a reorganization of the tech-nology requirements tables.

Predicted cost metrics for devices have been dropped from the tables because of a variety of concerns from the manufac-

turers; instead, cost targets for testing are listed. The integration path for MEMS IMUs has been removed from the accelerometer and gyroscope tables and put into a new table. The integration path for IMUs has been accelerated by one year; the 9 DOF device integrated at the package level as well as the 6 DOF device integrated at the chip level were moved from 2013 to 2012. Finally, the RF MEMS tables have been combined into a single table.

ConclusionThe back end of MEMS manufacturing

(packaging and testing) consumes two-thirds of the total manufacturing cost, yet virtually all R&D investment has been in the front end of manufacturing (device and process development). This unbalance can be attributed to a lack of articulation of the important problems at the back end.

The roadmapping efforts described in this report are the first steps in the long journey of communicating the industrial needs for MEMS technology to advance along its projected technology timeline. The development of a consensus opin-ion that documents the issues facing the industry, which is the primary output from technology roadmapping, can be used as a tool to optimize R&D investment that meets critical manufacturing needs in a timely manner.

About the Authors

Michael GaitanMichael Gaitan leads the Semiconductor

and Dimensional Metrology Division’s Microelectronics Device Integration Group at the National Institute of Standards and Technology (NIST). His group advances measurement science and standardization

of test methods for MEMS device technol-ogies. He chairs the iNEMI and ITRS MEMS Technology Working Groups.

Robert TsaiRobert Tsai is the director of the MEMS

program at TSMC, where he is spearhead-ing the growth of the MEMS foundry busi-ness. Prior to joining TSMC, Tsai was a senior vice president and CTO of AOPC, a maskmaker for large TFT-LCD manufactur-ers in Taiwan. He has 30 years of experi-ence in laser scanning, laser-related semi-conductor processing and other cross-field electro-optical and MEMS technologies. He is Asian co-chair of the ITRS MEMS Technology Working Group.

Philippe RobertHaving worked in various positions in

industry, Philippe Robert, Ph.D., is now manager of the MEMS Sensors group at CEA-Leti. He has authored or co-authored about 40 journal papers and conference contributions, and holds more than 40 patents dealing with MEMS and NEMS. He was member of the IEEE MEMS Technical Committee in 2007 and 2008. He is European co-chair of the ITRS MEMS Technology Working Group.

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Extending knowledge of the physics of failure will enable methods to improve device reliability and to

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In response to strong interest from the memory community, the ITRS Emerging Research Devices (ERD) and Emerging Research Materials (ERM) Technology Working Groups (TWGs) organized two workshops in 2012 to address two new topics in the ERD Emerging Memory sec-tion: Memory Select Devices and Storage-Class Memory (SCM). The workshops brought together experts in the fields to identify device options and assess technol-ogy feasibility in these two areas.

The study on memory select devices focused on scalable diode- or switch-type devices capable of driving and select-ing resistance-based emerging memories in crossbar arrays. The study on SCM focused on the suitability of conventional and emerging memories for SCM applica-tions and architectural issues of SCM. Both workshops broadened the scope of ERD coverage on these two new topics and provided in-depth assessment. Important research directions for these two topics were also recommended.

Emerging Research DevicesThe ERD chapter of the ITRS surveys,

assesses and catalogs viable new memory and information processing devices and

system architectures for their long-term potential and technological maturity, and identifies the scientific/technological chal-lenges gating their acceptance by the semiconductor industry. Since 2011, ERD has added memory select devices and SCM to the Emerging Memory section of the chapter.

Emerging memories have made promising progress in the past 10 years and offered potential solutions for the replacement of conventional CMOS-based memories. A functional memory includes a memory/switch element and a selec-tion element. Both elements impact the memory scaling limits. In Flash memory, these two elements are built in one: the transistor for device selection and the floating gate for memory/switch. As shown in the memory taxonomy in Figure 1, many emerging memories have a simple two-terminal structure that is compat-ible with crossbar array architectures and could achieve 4F2 footprint for high device density. However, these two-ter-minal emerging memories often have only the memory/switch function and lack the device selection capabilities. Select devic-es need to be built with these emerging memories in memory arrays. For several

ITRS CHAPTER:Emerging Research Devices

advanced concepts of resistance-based memories, the memory/switch element could in principle be scaled below 10 nm, and the memory density would be lim-ited by the much larger select devices. Therefore, the select devices represent a serious bottleneck for emerging memories scaling to 10 nm and beyond.

SCM describes a relatively new device category that combines the benefits of solid-state memory, such as high perfor-mance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. Such a device requires a non-volatile memory technology that can be manufactured at a very low cost per bit. The potential of prototypical and emerging research memory devices for SCM applications is assessed in the

context of existing commercialized stor-age technologies, namely the magnetic hard disk drives (HDD) and non-volatile semiconductor Flash memory. As the scalability of Flash memory approaches its limit, emerging technologies for non-volatile memories need to be investigated for a potential replacement for Flash to continue the scaling roadmap.

Memory Select DevicesMemory select devices can be cat-

egorized into three-terminal devices (i.e., transistors) and two-terminal devices (i.e., diodes, volatile switches, and nonlinear devices), as shown in Figure 2.

Although transistors have the best “device selection” functions in terms of on/off ratio and drive current, the large

An Chen,1 Victor V. Zhirnov,2 James A. Hutchby,2 C. Michael Garner31GLOBALFOUNDRIES 2Semiconductor Research Corp. 3Garner Nanotechnology Solutions

Memory

Volatile

Non-refreshable

SRAM

Refreshable

DRAM

Floating-body

Non-volatile

Mature

Flash

NOR

NAND

Prototypical

Discrete trap

FeRAM

PCM

MRAM

STT-RAM

Exploratory

Nanomechanical

RRAM

Redox

Nano PMC

Electronic

Polymer

Molecular

Two-terminalstructures

4F2 footprint

Figure 1. This memory taxonomy highlights memories with two-terminal structures suitable for crossbar memory arrays with a 4F2 device footprint.

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footprint and high processing temperature are their main disadvantages. Two-terminal select devices are more scalable; however, it is still a challenge to find these devices with sufficiently high rectification ratio and drive current. Another disadvantage of two-terminal select devices is the lack of current-control capabilities. Transistors can limit current during switching by Vg; how-ever, diodes and volatile switches do not provide this function.

Since memory elements can be unipo-lar (switch on and off in the same polar-ity) or bipolar (switch on and off in the opposite polarities), the operation polarity of select devices needs to be compatible with that of the memory element. Most diodes only work for unipolar devices (e.g., pn-junction, Schottky diodes, heterojunc-tion diodes, etc.). Some volatile switches

provide bipolar select devices (e.g., Mott-transition devices, threshold switches, etc.). Many of these volatile switches are built on unconventional materials (e.g., oxides, chalcogenides, super-ionic mate-rials, etc.). Figure 3 maps two-terminal select devices based on their polarity and materials.

Functional select devices need to have large enough resistance difference in the conductive state and the blocking state, a parameter known as on/off ratio (e.g., for switch-based select devices) or recti-fication ratio (e.g., for diode-based select devices). Another important requirement is that select devices need to provide suf-ficiently high voltage and current for the operation of the memory elements. It is also desirable that the select devices have better or similar scalability as the memory

element; otherwise, the scaling advantage of emerging memories and crossbar arrays could be compromised by select devices. Table 1 defines a set of parameters for select devices. In addition to the on/off ratio, maximum on current and scalability, other parameters such as speed, endur-ance and manufacturability also impact the feasibility of select devices.

It is important to take applications into consideration when select devices are compared. For embedded applica-tions where device size is less a concern, transistor select devices provide random-access capability and 1-transistor-1-resistor (1T1R) is the preferred configuration. For standalone applications, 3D architec-tures might be necessary for emerging memories to be competitive with bit-cost scalable 3D NAND, which impose strong

requirements on the scalability of select devices. Memory elements with self-select-ing capabilities might be required.

An important requirement in the 1T1R configuration is that the channel resistance of the select transistor needs to be sig-nificantly lower than that of the memory element; otherwise, the effective memory window of 1T1R will not be dominated by the memory element. Transistor resistance increases steadily while half-pitch scales down. It could reach 100 k at 20 nm half-pitch, which requires the memory element to have the resistance over 1 M at low-resistance state (LRS).

Polysilicon-based p-i-n diodes are able to achieve on-current density of 107 A/cm2 and off-current density of 10-1 A/cm2. They have been demonstrated as functional select devices for PCM.[1,2] It is believed

ITRS CHAPTER: Emerging Research Devices Future Fab Special ITRS Focus

Select Devices

Transistor

Planar

Vertical

Diodes

Si diodes

Oxide/oxideheterojunctions

Reverse-conductiondiodes

Zener diode

BARITT diode

Volatile switch

Threshold switch

Mott switch

MIEC

Nonlinear devices

Metal/oxideSchottky junctions

Figure 2. Categories of memory select devices.Figure 3. Types of two-terminal select devices in terms of polarity and materials. (Courtesy of Dirk Wouters, IMEC)



that they can be scaled down to 20 nm or even 10 nm. The major challenge of silicon diodes is the high processing temperature required to crystallize silicon to reduce contact resistance and off-current. Metal-oxide-based diodes can be fabricated at lower temperatures; however, these diodes are not yet able to provide the same level of switching current and on/off ratio as silicon diodes.[3-6] Another issue with diodes as select devices is the variability caused by random distribution of dopants. At least one side of a junction needs to be low or intermediate doping to maintain a certain breakdown voltage. In highly scaled devices, doping fluctuation could be severe, e.g., 1018 cm-3 doping concentration in a 10x10x10 nm volume means a single-atom dopant.

Volatile switching devices based on metal-insulator transition (or Mott transi-tion) phenomenon may also be used for

select devices. In principle, these devices can achieve high speed and long endur-ance. VOx is one of the most important Mott materials under investigation; however the low transition temperature is a severe limitation for VOx-based switches.[7,8]

Complementary resistive switch (CRS) was proposed as a self-selecting struc-ture by connecting two resistive switch-ing memories anti-serially.[9,10] The “0” and “1” states of CRS both have high resistance, which helps to reduce leakage through sneak paths in crossbar arrays. A main challenge of CRS is the destructive reading and some non-destructive readout methods are being investigated.[11] CRS also has limited tolerance on the variation of memory switching voltages.

A so-called mixed ionic electronic con-duction (MIEC) device is also developed as a select device for PCM and other emerging resistive memories.[12-14] The

copper-containing MIEC materials exhibit exponential I-V characteristics and a large fraction of mobile Cu+ enables high cur-rent density required for memory switch-ing. MIEC devices have been integrated in a standard CMOS process and demon-strate promising properties, such as long endurance, high current, large on/off ratio, strong thermal stability, etc.

The memory select device work-shop raised some important issues to be addressed by the memory R&D commu-nity. Contact resistance is a common limi-tation for all types of select devices, and its impact increases with device scaling.

Many resistive switching memories require a forming process before stable switch-ing can be achieved. The high voltage and current for forming imposes extra perfor-mance requirements on select devices. The resistance difference between select devices and the memory element is an important factor in compatibility. Select device resistance usually increases with scaling, which requires the memory ele-ment to operate in a much higher resist-ance range. Speed of select devices should not be slower than the memory element, and the steepness of select device I-V (dI/dV) also affects the memory window.


(in ns)1

10

100

103

104

105

106

107

108

109

1010

On-chipmemoryDecreasing

cost

Memory/storage gap

Off-linestorage

On-linestorage

Off-chipmemory

Read or write to disk (5 ms)

Get data from tape (40 s)

Write to Flash, random (1 ms)

Read a Flash device (20 μs)

Get data from DRAM/SCM (60 ns)Get data from L2 cache (<5 ns)

Access time…

Tape

Disk

RAMCPU

Tape

Disk

RAMCPU

1980 Today

FlashSSD

CPU operations (1 ns)

Figure 4. Storage Class Memory.[16]

Parameter Explanations

On/off ratio Defined as the ratio between on- and off-state current or resistance. On/off ratio varies with measurement voltage, so a reasonable on/off ratio needs to be defined at appropriate forward and reverse voltages.

Maximum on current (density) Determines the capability of select devices to deliver sufficient current to switch memory elements. There may be intrinsic limits on maximum current, and external contact resistance also affects this parameter.

Scalability How small can the select device be made? How do select device parameters change with scaling?

Threshold voltage Affects the effective voltage passed to the memory elements.

Operation polarity Bipolar or unipolar operations.

Switching speed Select devices need to turn on and off fast enough to avoid slowing down memory operation.

Endurance Select devices are turned on and off during both writing and reading of memory element, which imposes strong endurance requirements.

Manufacturability Processing temperature, materials compatibility, integration issues, etc.

Variability Parameters of the select device need to be tightly controlled so that NVM resistance distributions are not excessively broadened.

Margin There must be safety zones around the operating voltages so that the “selected for write,” “unselected during write,” “selected for read” and “unselected during read” operations all remain sufficiently distinct.

Table 1. Parameters of Select Devices



Storage-Class MemoryMemory technology and memory archi-

tectures are going through a period of rapid change. Emerging non-volatile memo-ries complement and potentially replace the traditional triad of SRAM, DRAM and Flash. At the same time, the nature of memory use is changing fast as well. SCM (Figure 4) is an emerging memory category that seeks to combine the benefits of solid-state memory, such as high performance and robustness, with the data retention capabil-ities and the low cost of conventional hard-disk magnetic storage.[15] An SCM device requires a non-volatile memory technology that could be manufactured at a very low cost per bit. In principle, such new SCM

technology could engender two entirely new and distinct levels within the memory and storage hierarchy, M-SCM and S-SCM, located below off-chip DRAM and above mechanical storage, which are differentiat-ed from each other by access time. Table 2 compares the specifications of M-SCM and S-SCM with these of benchmarks.

The goal of SCM development is to cre-ate compact, robust storage (and memory) systems with greatly improved cost/per-formance ratios relative to other technolo-gies. To be successful, SCM should offer a combination of reliability, fast access, and endurance of a solid-state memory, togeth-er with the low-cost data retention capabili-ties and vast capacity of a magnetic hard

disk drive. Thus, the defining requirements for all SCM technologies are non-volatility (ranging from one week to 10 years), very low read and write latencies (ranging from hundreds of nanoseconds up to tens of microseconds), physical durability during practical use and, most importantly, ultra-low cost per bit.

Necessary attributes of a memory device for the SCM applications are scal-ability, multi-level cell (MLC), 3D integra-tion, fabrication costs, endurance and retention. Table 3 shows the potential of different prototypical and current emerg-ing research memory entries for SCM applications based on the above param-eters. A likely introduction of these new memory devices to the market is by the hybrid solid-state discs, where the new memory technology complements the tra-

ditional Flash memory to boost the SSD performance. Experimental implementa-tions of FeRAM/Flash and PCRAM/Flash have recently been explored. It was shown that the PCRAM/Flash hybrid improves SSD operations by decreasing the energy consumption and increasing the lifetime of Flash memory.[17]

Since SCM is a system-level approach to fill the memory gap, not only the memory technologies but also dedicated interface and architecture for each tech-nology need to be examined, in order to utilize the potential of the memories and to address their weaknesses. For exam-ple, performance of Flash SSD is strongly limited by their interface performance. The standard Serial Advanced Technology Attachment (SATA) interface commonly used for SSD has originally been designed


Prototypical memories

Emerging memories

Parameter FeRAM STT-MRAM PCRAM Emerging

ferroelectric memory

Nanomechanical memory

Redox memory

Mott memory

Macromolecular memory

Molecular memory

Scalability

MLC

3D integration

Fabrication cost

Endurance

!

! !

!

!

! !

!

Table 3. Potential of Current Prototypical and Emerging Research Memory Candidates for SCM Applications

HDD [B] NAND Flash [C] DRAMMemory-type

SCM

Storage-type

SCM

~100 μs(block erase ~1 ms)

Endurance (cycles) Unlimited 104-105 Unlimited >109 >106

Retention >10 years ~10 years 64 ms >5 days ~10 years

ON power (W/GB) ~0.04 ~0.01-0.04 0.4 <0.4 <0.04

Standby power ~20% on power <10% on power ~25% on power <1% on power <1% on power

Areal density ~ 1011 bit/cm2 ~ 1010 bit/cm2 ~ 109 bit/cm2 >1010 bit/cm2 >1010 bit/cm2

Cost

[A] The benchmark numbers are representative values, which may have significant variations in specific products

[B] Enterprise class

[C] Single-level cell (SLC)

($/GB) 0.1 2 10 <10 <3-4

Parameter

Target

Read/write latency 3-5 ms <100 ns <100 ns 1-10 μs

Benchmark [A]

Table 2. Target Device and System Specifications for SCM



for HDD and is not optimized for Flash SSD.[18] There are several approaches to employ a novel interface or architecture to take advantage of the Flash SSD perfor-mance.[18-20] For new SCM candidates, novel memory interface solutions have to be explored at the system level.

In addition to storage applications, suc-cessful implementation of SCM could also affect developments in new chip architec-tures. For example, advances in SCM could drive the emerging data-centric chip archi-tectures (e.g., the Nanostores),[21] which could be an important direction for the future of information processing.

SummaryMemory select devices and SCM rep-

resent two promising emerging memory research directions. Select devices are considered technology enablers for emerging memories. Essentially nonlinear-ity and asymmetry in device characteris-tics can be used for memory selection. A broad range of diodes and volatile switch-es have been experimented with for this application.

SCM introduces a new application space for emerging memories, which imposes unique performance requirements and provides market drivers for technol-ogy development. Based on the informa-tion and expert opinions from the two workshops, ERD will continue document-ing progress and evaluating technology maturity on these two topics.


the efforts of the ITRS Emerging Research Devices Working Group in making this article possible. A full list of members of the Emerging Research Devices Working Group can be found here.

Switches for Passive Nanocrossbar Memories,” Nature Materials, 9, 403 (2010).

10. Y. Chai, et al., “Nanoscale Bipolar and Complementary Resistive Switching Memory Based on Amorphous Carbon,” IEEE Transactions on Electronic Devices, 58, 3933 (2011).

11. S. Tappertzhofen, et al., “Capacity Based Nondestructive Readout for Complementary Resistive Switches,” Nanotechnology, 22, 395203 (2011).

12. K. Gopalakrishnan, et al., “Highly Scalable Novel Access Device Based on Mixed Ionic Electronic Conduction (MIEC) Materials for High Density Phase Change Memory (PCM) Arrays,” Symposium on VLSI Technology, 19.4 (2010).

13. R.S. Shenoy, et al., “Endurance and Scaling Trends of Novel Access-Devices for Multi-Layer Crosspoint Memory Based on Mixed Ionic Electronic Conduction (MIEC) Materials,” Symposium on VLSI Technology, T5B-1 (2011).

14. G.W. Burr, et al., “Large-Scale (512kbit) Integration of Multilayer-Ready Access-Devices Based on Mixed-Ionic-Electronic-Conduction (MIEC) at 100% Yield,” Symposium on VLSI Technology, T5.4 (2012).

15. G.W. Burr, et al., “Overview of Candidate Device Technologies for Storage-Class Memory,” IBM J. Res. & Dev., 52, No. 4/5, 449–464 (2008).

16. G.W. Burr, “Storage Class Memory: Towards a Disruptively Low-Cost Solid-State Non-Volatile Memory,” ITRS Workshop on Emerging Architectures for Storage Class Memory, Monterey, Calif., July 8, 2012.

17. H.G. Lee, “High-Performance NAND and PRAM Hybrid Storage Design for

References1. Y. Sasago, et al., “Phase-Change

Memory Driven by Poly-Si MOS Transistor With Low Cost and High-Programming Gigabyte-per-Second Throughput,” Symposium on VLSI Technology, 24 (2009).

2. M. Kinoshita, et al., “Scalable 3-D Vertical Chain-Cell-Type Phase-Change Memory With 4F2 Poly-Si Diodes,” Symposium on VLSI Technology, 5.1 (2012).

3. M.J. Lee, et al., “2-stack 1D-1R Cross-Point Structure With Oxide Diodes as Switch Elements for High Density Resistance RAM Applications,” IEDM Technical Digest, 771-774 (2007).

4. S. Narushima, et al., “A P-Type Amorphous Oxide Semiconductor and Room Temperature Fabrication of Amorphous Oxide P-N Heterojunction Diodes,” Advanced Materials, 15, 1409-1413 (2003).

5. W.Y. Park, et al., “A Pt/TiO2/Ti Schottky-Type Selection Diode for Alleviating the Sneak Current in Resistance Switching Memory Arrays,” Nanotechnology, 21, 195201 (2010).

6. Y.C. Shin, et al., “(In,Sn)2O3/TiO2/Pt Schottky-Type Diode Switch for the TiO2 Resistive Switching Memory Array,” Applied Physics Letters, 92, 162904 (2008).

7. M. Son, et al., “Excellent Selector Characteristics of Nanoscale VO2 for High-Density Bipolar ReRAM Applications,” IEEE Electron Device Letter, 32, 1579 (2011).

8. M.J. Lee, et al., “Two Series Oxide Resistors Applicable to High Speed and High Density Nonvolatile Memory,” Advanced Materials, 19, 3919 (2007).

9. E. Linn, R. Rosezin, C. Kuegeler and R. Waser, “Complementary Resistive

Consumer Electronics,” IEEE Trans. Consum. Electron., 56, 112-118 (2010).

18. D. Kim, K. Bang, S.H. Ha, S. Yoon and E.Y. Chung, “Architecture Exploration of High-Performance PCs With a Solid-State Disk,” IEEE Trans. Comp., 59, 879-890 (2010).

19. Fusion-io, www.fusionio.com.20. NVM Express Explained, download.

intel.com/standards/nvmhci/NVM_Express_Explained.pdf.

21. P. Ranganathan, “From Microprocessors to Nanostores: Rethinking Data-Centric Systems,” Computer, 44, 39-48 (2011).

About the Authors

An ChenAn Chen is co-chair of the Emerging

Research Device Working Group for the ITRS. He is a senior member of techni-cal staff at GLOBALFOUNDRIES, working on emerging logic devices. He is also the memory technology lead responsible for the collaboration with industry consor-tia on emerging memories. He is a senior member of the IEEE.

Victor ZhirnovVictor Zhirnov is director of special pro-

jects at the Semiconductor Research Corp. He is the chair of the Emerging Research Device Working Group for the ITRS. He also holds an adjunct faculty position at North Carolina State University, and has served as an advisor to a number of gov-ernment, industrial and academic institu-tions. Zhirnov received an M.S. in applied physics from the Ural Polytechnic Institute, and a Ph.D. in solid-state electronics and microelectronics from the Institute of Physics and Technology, Moscow.




Being a “futurist” in the semiconduc-tor industry has never been more dif-ficult. Hard as it may be to believe, the iPad made its appearance less than three years ago, yet at least one Fortune 500 CEO was rumored to have lost his job because he lacked a “tablet strategy.”

Given the pace of change, it is reas-suring to see that the ITRS continues to boldly predict the future up to 15 years out. In the following articles, we see two sides of what is essentially the same coin. In the first, the authors look at how changes in the application space impact ITRS Design and System Driver trends. The emergence of mobile and (a new term for me) microserver SoC devices is leading to different tradeoffs in terms of frequency and core count when com-pared with traditional server-class pro-cessors. Because of the power limitations in both applications, designers need to be even more creative in extracting MIPS from an ever-decreasing milliwatt budget.

Liam MaddenCorporate VP, FPGA Development & Silicon Technology, Xilinx

The second article looks at similar shifts in Modeling and Simulation predic-tions. With the introduction of finFETs this year, the prevalence of double pat-terning at 20 nm, and the (hopefully) imminent deployment of extreme ultra-violet (EUV) lithography equipment, the modeling community can be expected to be busy for many years to come. In addi-tion, overworked designers are being asked to reach beyond Moore’s Law and leverage More than Moore technologies such as 3D chip stacking. Simulations must now reach from the nanometer regime all the way to exotic “sandwich-es” made up of silicon and organic pack-ages.

If there is any good news to be extracted here, it is that our technolo-gists have been exceptionally success-ful at maintaining the momentum of our more than $300 billion/year business. The ITRS predictions might not be com-pletely accurate, but they give scale to the mountains that must be climbed.

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DESIGN IMPLEMENTATION & PROCESS INTEGRATION

Click here to return to Table of ContentsJames A. HutchbyJames A. Hutchby, currently a con-

sultant, was formerly senior scientist and director of device sciences with the Semiconductor Research Corp. (SRC). He founded and chaired the Emerging Research Device Working Group for the ITRS. Prior to joining SRC, he was director of the Research Triangle Institute’s Center for Semiconductor Research. He is a Life Fellow of the IEEE and a recipient of the IEEE Third Millennium Medal.

C. Michael GarnerMichael Garner is a visiting scholar

at Stanford University, and a consultant for Garner Nanotechnology Solutions. He is also co-chair of the ITRS Emerging Research Materials (ERM) Technology Working Group. He previously worked for Intel, most recently as program manager of External Materials Research. Garner received his Ph.D. in materials science and engineering from Stanford University in 1978.

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The Design and System Drivers chap-ters of the ITRS provide a view into critical design technology challenges and required solutions across various market domains and abstraction levels. The solutions are fundamental to improved tools and meth-odologies that will enable the development of future electronic products. The Design Technology Roadmap encompasses every pre-manufacturing aspect of developing a semiconductor product, and sets out a 15-year path of improvements needed to sustain the industry’s amazing pace.

For many years, the scaling of elec-tronic product value has been only partly due to improvements in manufacturing technology. Particularly in the past dec-ade, design technology has become a

key enabler of the overall semiconductor roadmap, and is increasingly aligned and

mutually dependent with the manufac-turing and device aspects of the ITRS. In 2012, we are witnessing the transition to a new phase of the industry’s evolution, whereby application domains increasingly drive the development of technology to scale electronic products. Though a sin-gle implicit domain (microprocessors, or MPUs) drove improvements for decades, new applications that have severe power constraints yet very competitive perfor-mance requirements are becoming the new industry drivers.

In this article, we explore a couple of these key emerging applications, along with how they relate to the ITRS System Drivers chapter and modeling efforts. We conclude that the System Drivers chapter

will need to progressively adapt to a new reality of power-performance drivers that

ITRS CHAPTERS: Design and System Drivers

increasingly cut across traditional domain boundaries and product classifications.

SoC and Mobile as the New Leading Edge

Application domains and architectures start to drive innovation based on market traction. Systems-on-chip (SoCs), and in

particular mobile SoCs (with mobile pro-cessors showing particularly strong focus and market uptake), have been catching up with high-end MPUs for the past 10 years and may now be the new driving force behind semiconductor technology.

Market forces in the mobile arena have put a huge emphasis on efficient Juan-Antonio Carballo,1 Andrew B. Kahng2

1Broadcom 2University of California at San Diego

Figure 1. A frequency trend shows multicore SoCs catching up to high-end MPUs in the recent 10-year cycle.

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Figure 2. The overall SoC industry trend vs. the mobile SoC model in the ITRS System Drivers chapter.

For many years, the scaling of electronic product value has been only partly due to improvements

in manufacturing technology.




power consumption. Since SoC designs have already extensively leveraged het-erogeneous multicore architectures and accelerators, the industry must continu-ally seek new design, architecture and circuit innovations to keep performance growing despite the strict power con-straints that will remain in place. Figure 1 illustrates this trend, focused on clock

frequency (one of the parameters that has been driving processor performance for decades).

The figure lines up a sampling of actual clock frequencies for industry products in the SoC category, against frequency data from the ITRS MPU driver model. As the figure shows, SoC frequencies have outpaced those of MPUs over the past

10 years. We expect that SoCs will soon experience a similar flattening of frequen-cies because of the same type of power constraints that MPUs have faced. As noted earlier, multicore and other power-reducing design techniques from the MPU world have already been applied to SoCs; hence, even deeper innovation will be needed this time around, especially since power constraints are more severe in the types of applications where SoCs are most used.

The Number of SoC Cores Mirroring the industry experience with

standard MPUs, the number of cores in SoCs is rapidly growing. Is the ITRS model keeping up with this trend? We have recently studied how well the current ITRS mobile SoC model compares with a survey of industry data points, many of which correspond to mobile SoCs. Figure 2 compares SoC product data with the ITRS Consumer Portable model.

We see from the figure that both the ITRS Consumer Portable (mobile SoC)

model and the industry survey show a rap-idly growing number of cores—with the growth rate being significantly more rapid than in the “conventional” high-perfor-mance MPU model. This provides support to the notion that SoCs are the new driver in terms of number of cores. A secondary observation is that industry is surpassing the current ITRS SoC model with respect to the number of general-purpose cores inside an SoC.

At the same time, it should be noted that the industry SoC data includes not just mobile, but also some networking SoCs, whose number of cores grows (at least, historically) even faster. Figure 3 is restricted to only mobile SoCs, and the trend reverses: The current ITRS model appears to be too aggressive in terms of how quickly the number of cores should grow. Indeed, one can see from industry newsletters that the state of the art in mobile application processors is no higher than four cores in 2012-2013.

SoC Mobile Drives MicroserversPower constraints are not exclusive to

mobile applications. They are also very vis-ible in new domains and non-mobile appli-cations, such as very large data centers with huge numbers of storage, server and networking hardware systems.

Microservers are a new class of servers composed of numerous microprocessors, each of which is not very powerful and consumes extremely low power—pre-sumably via a simplified architecture. A

microserver can have hundreds of proces-sors in a very small volume, each proces-sor consuming from 20 W down to as low as 5 W—in contrast to a typical server pro-cessor, which may easily consume several times that amount (Figure 4).

Updates and ConclusionsThe 2012 update and the planned 2013

revision of the ITRS Design and System Drivers chapters will bring several key new

ITRS CHAPTERS: Design and System Drivers Future Fab Special ITRS Focus

Figure 4. Microserver product applications drive step-function improvements in power-per-unit performance.

Figure 3. The mobile SoC industry trend vs. the mobile SoC model in the ITRS System Drivers chapter.

Mirroring the industry experience with standard MPUs, the number of cores in SoCs is rapidly growing. Is the ITRS model keeping up with this trend?



messages and updates to these facets of the semiconductor roadmap. Highlights include the following:• Design chapter: refreshed data and text

in several sections, as well as refreshed Cost and Power charts.

• System Drivers chapter: updated data and accompanying text, particularly for the SoC product class.

The takeaway for 2012: Power is an increasingly dominant consideration in the roadmap and will continue to be a major force and driver over the next decade. Amid this context, the nature of drivers and applications is also changing quickly. Indeed, the key design trends that drive design and device technologies—such as number of cores and frequency—are increasingly going to be resolved in domains such as mobile processors and microserver processors (which in turn borrow mobile design techniques to save power).

Acknowledgments The authors would like to acknowledge

the efforts of the ITRS Design and System Drivers Working Groups in making this article possible. A full list of members of the Design and System Drivers Working Groups can be found here. We thank Jonas Chan, Jiajia Li and Siddhartha Nath at UC San Diego for their survey of indus-try products, results of which have been used in this article.

About the Authors

Juan-Antonio CarballoJuan-Antonio Carballo has been an

ITRS Design group co-chair for more than 10 years. Currently at Broadcom, he has pursued research, development, strat-egy, marketing, sales and venture capital roles at various other companies, includ-ing NetLogic, IBM, LSI Logic and DEC. He has more than 30 patents, numerous publications, and wrote a book on chip design. He has a Ph.D. from the University of Michigan and an MBA from the Collège des Ingénieurs in Paris.

Andrew B. KahngAndrew B. Kahng is professor of com-

puter science and engineering and elec-trical and computer engineering at UC San Diego, and has been chair/co-chair of the ITRS Design ITWG since 2000. His research focuses on physical design, per-formance analysis, and design for manu-facturability of ICs. He is the author of more than 400 papers, three books and 22 issued U.S. patents. He received his Ph.D. in computer science from the University of California at San Diego in 1989.

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Technology modeling and simulation is the virtual counterpart of semiconductor device and chip fabrication and charac-terization: Computer programs are used to predict the geometries, strain and chemi-cal composition (dopants, SiGe, etc.) of devices, their electrical performance and reliability, and finally the behavior of circuit and system. The overall aim of modeling and simulation is to support the develop-ment of real-world technologies, devices, circuits and systems by providing informa-tion that is difficult, costly, less efficient or too time-consuming to obtain from experi-ments, and in this way to reduce develop-ment times and costs.

To enable this, modeling and simulation tools must contain appropriate physical models, including appropriate parameter settings, and also meet various require-ments in terms of generality of application, speed of simulation, complexity of the applications that can be addressed, and user interfaces and interactions. In turn, dedicated R&D activities on modeling and simulation capabilities are needed.

The ITRS Modeling and Simulation chapter addresses 11 areas, grouped into equipment-related, feature-scale, IC-scale

simulation, and four cross-cutting areas as shown in the chapter and outlined in Issue 36 of Future Fab International. Besides texts on these areas and on the cross-cuts with the other chapters of the ITRS, the Modeling and Simulation chapter contains four tables that are in agreement with the general ITRS procedure revised in the 2012 ITRS Update: Difficult Challenges, Technology Requirements: Capabilities (both near-term and long-term versions), and Technology Requirements: Accuracy.

2012 Table UpdateConsiderable changes were made to

the tables already in 2010, especially to the Difficult Challenges and the Technology Requirements: Capabilities—Near-Term tables. This was because of the ITRS’s two-year shift of the projection for the develop-ment of prioritized technological options, new materials and device architectures being addressed, and generally the devel-opment of state-of-the-art devices.

Another effect that influences the Modeling and Simulation chapter is the ongoing transfer of selected device archi-tectures and materials from the Emerging Research Devices (ERD) and Emerging

ITRS CHAPTER: Modeling & SimulationJürgen LorenzFraunhofer IISB

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Research Materials (ERM) chapters into the Process Integration, Devices and Structures (PIDS) and Front End Processes (FEP) chapters of the ITRS. In parallel with this, the simulation of such devices and materials also enters the scope of the Modeling and Simulation chapter.

Because the projection horizon does not change in an update year like 2012, the changes of the Modeling and Simulation tables have in 2012 been considerably smaller than in 2011. In the following, the main content of the tables and of their

2012 changes is summarized. Also in 2012, the Difficult Challenges table (MS1) defines six near-term challenges:1. Lithography simulation including EUV2. Front-end process modeling for nanom-

eter structures3. Integrated modeling of equipment,

materials, feature scale processes and influences on device and circuit perfor-mance and reliability, including random and systematic variability

4. Nanoscale/advanced More than Moore (MtM) device simulation capability:

Difficult Challenges ≥ 14 nm Summary of Issues Complementary lithography

2011 Simulation of defect inspection and characterization, influences/defect printing. Mask optimization including defect repair or compensation

2012 Simulation of defect inspection and characterization, influences/defect printing. Mask optimization including defect repair or compensation based on defect signature available from characterization. Multilayer defect propagation.

Simulation of resolution enhancement techniques including combined mask/source optimization (OPC, PSM) and including EMF and resist effects, and extensions for inverse lithography

2011 Models that bridge requirements of OPC (speed) and process development (predictive) including EMF effects

2012 Models that bridge requirements of OPC (speed) and process development (predictive) including EMF effects, including high NA effects for EUV

Predictive and separable resist models (e.g., mesoscale models) including line-edge roughness, accurate profiles, topcoat and substrate (underlayer) interactions, etch resistance, adhesion, mechanical stability, leaching, swelling or slimming, and time-dependent effects in in single and multiple exposure

Resist model parameter calibration methodology (including kinetic transport and stochastic parameters)

Fast, predictive simulation of ebeam mask making (single-beam and multibeam) including short and long range proximity corrections

2011 Simulation of directed self-assembly of sublithography patterns

2012 Simulation of directed self-assembly of sublithography patterns, esp. guiding pattern optimization and defect formation.

Modeling lifetime effects of equipment and masks, including lens and mirror heating effects

Predictive coupled deposition-lithography-etch simulation (incl. double patterning, self-aligned patterning)

Modeling metrology equipment and data extraction for enhancing model calibration accuracy

Lithography simulation including EUV

Modeling of pellicle effects and pellicle defects simulation (incl. double patterning, self-aligned patterning)

Table 1. One of the 10 challenges from table MS1, Modeling and Simulation Difficult Challenges

methods, models and algorithms5. Electrical-thermal-mechanical modeling

for interconnect and packaging6. Circuit element and system modeling

for high-frequency (up to 300 GHz) applications

These titles are similar to 2011 except for the extension of the fourth challenge to also include advanced MtM devices. Several changes were made to the detailed content of these challenges. In particular, in the first challenge on lithography simulation, defect propagation/repair and directed self-assembly was extended, and the request for high numerical aperture (NA) added for EUV lithography. The application of con-formal doping for finFETs was specifically added to the second challenge on front-end process simulation. For the fourth challenge on nanoscale/advanced MtM device simulation, wide bandgap and high-voltage device were added, as well as the request for orientation-dependent mobility for non-standard directions. For the fifth

challenge on electro-thermal-mechanical modeling, combined electromagnetic and drift diffusion simulation to include inductance effects in substrate caused by interconnects and bond wires was added. Minor modifications were made in the sixth challenge on circuit element and system modeling.

For the long-term challenges, the need to simulate the stability of physical parameters (e.g. keff) was added to the challenge on the modeling of chemical, thermomechanical and electrical proper-ties of new materials. The other three long-term challenges—nanoscale modeling for Emerging Research Devices and inter-connects including Emerging Research Materials, optoelectronics modeling, and NGL simulation—were kept unchanged.

As an example, Table 1 shows the lithog-raphy simulation part of the near-term chal-lenges, comparing differences between the 2011 ITRS and the 2012 ITRS Update.

A key change made in all three Technology Requirements tables is that

Figure 2. As an example of the impact of process variations on SRAM performance, these charts show read and write delay in the presence of six different process variations. For details on the simulations carried out, see Ref. 1.

ITRS CHAPTER: Modeling & Simulation Future Fab Special ITRS Focus



the feature size definitions—such as half-pitch and gate length—have been skipped in the table headers. The reason for this is that modeling and simulation tools should be available before the technology to be supported by these tools goes into production. Therefore, the time specified does not refer to the manufacturing of a device with certain feature sizes but to the requested availability of simulation.

The table Modeling and Simulation Technology Requirements: Capabilities—Near-Term Years again summarizes the needs in the areas of process, device, cir-cuit and package simulation, and also pre-mier general requirements on tools. The most important changes are as follows: For EUV lithography, high-NA optics have

come into play. We have also highlighted the need for databases for all relevant processes and equipment. Various details of the requirements have been changed, including an update of the timelines, the sequences, and the state-of-the-art of sev-eral requirements. At this level of detail, also some aspects have been dropped because they were identified as solved.

The long-term version of the table is far less detailed because long-term technol-ogy options are so far only partly defined or prioritized in the other parts of the ITRS. Generally, the majority of the items in the long-term requirements table are colored red because there are no known solutions yet. This is partly because the technological options are not yet known or prioritized, so therefore simulation

approaches cannot yet be developed or selected. Another problem is of course the inherent difficulty to develop models and tools to meet the ambitious requirements. In turn, the success of the development work required from M&S cannot be pre-dicted 10 or more years in advance. In the 2012 Update, the long-term requirements for circuit component modeling have been extended to include new memory devices.

The table on Modeling and Simulation Technology Requirements: Accuracy—Near-Term Years is quite similar to the other requirement tables grouped into lithography modeling, front-end process modeling, topography modeling, numeri-cal device modeling, circuit element mod-eling/ECAD, and package modeling. Here,

the estimate of about one-third—given for the cost and time reduction from using TCAD in best practice cases reported by industry—is based on an industrial survey already discussed in the 2008 ITRS.

In this table, accuracy refers to models and tools calibrated to a certain tech-nology (at a company), not to a certain experiment. Most accuracy specifications are given as a percent of the respective nominal value or of some top-level param-eter of the respective technology node (e.g. the physical gate length). A key issue in the preparation of this table has been how to define the accuracy of simulation compared with the experiments, which themselves have significant inaccuracy or uncertainty. As such, definitions listed in the footnotes of the table include notes

ITRS CHAPTER: Modeling & Simulation Future Fab Special ITRS Focus

such as “compared with median value of statistically meaningful samples.”

Furthermore, the table does not only specify the required accuracy in the simu-lation of nominal values like a junction depth, but also the accuracy of the sensi-tivity of such values with respect to chang-es in process conditions. This is important for tracing the impact of process variations through a simulation sequence, as request-ed in the M&S subchapter “Modeling for Design Robustness, Manufacturing and Yield” of the 2011 ITRS. In the 2012 Update, the specifications for the simulation of leakage currents have been consolidated, and some timelines have been updated.

SummaryGenerally speaking, the growing diver-

sity of materials, processes and device architectures to be simulated continues to increase the need for focused work on the development of physical models and simu-lation tools. In particular, the successive transfer of non-standard architectures and materials that are being explored in the ERD and ERM parts of the ITRS strongly calls for extended interdisciplinary coop-eration with research groups that have traditionally been less active in the area of microelectronics.

The requirements for multi-physical simulation covering electrical, electromag-netic, thermal and mechanical effects; for multi-scale simulation from atomistic to package, system or equipment level; the interrelationship between nominal process results/device properties, process vari-ability and reliability issues generate large challenges, but also offer huge prospects if appropriate simulation tools could be made available.

Figure 2 shows an example of the impact of various process variations on

circuit behavior as it can be studied with current simulation tools.[1]

AcknowledgementsThe author would like to acknowl-

edge the efforts of the ITRS Modeling & Simulation Working Group. A full list of members of the Modeling & Simulation Working Group can be found here.

Reference1. A. Burenkov, E. Baer, J. Lorenz and C.

Kampen, “Correlation-Aware Analysis of the Impact of Process Variations on Circuit Behavior,” Proc. SISPAD 2012, 260-263.

About the Author

Jürgen LorenzJürgen Lorenz heads the Technology

Simulation Department of the Fraunhofer Institute for Integrated Systems and Device Technology (IISB). He has been contributing since 2000 as an expert in the preparation of the ITRS, and has been chairman of its Modeling and Simulation Chapter since 2002. He has authored or co-authored more than 120 papers, and has repeatedly been or is a member of the technical committees of the ESSDERC, SISPAD and IEDM conferences. n

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FACTORY INTEGRATION


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Designing and producing even one family of modern semiconductor products is a collaborative effort involving hundreds of integrated technologies, thousands of people, and billions of dollars. Keeping this global economic engine on track is a com-plex, monumental task, and for the past 15+ years, the International Technology Roadmap for Semiconductors (ITRS) has served a vital role in establishing the requirements and suggesting potential solutions for an amazingly broad range of technologies across the entire value chain.

Despite the economic difficulties in the second half of 2012, the drive to innovate never wanes, and the energy that will be devoted to the 2013 version of the ITRS will be significant. Since 2013 is an odd year, the roadmap is due for a major update, which is summarized in this section of Future Fab for two of the technology areas: Factory Integration (FI) and Process Integration, Devices, and Structures (PIDS). Both are well-written and very approachable for those wanting a quick view of the industry’s direction in these areas.

Alan WeberPresident, Alan Weber & Associates

The FI summary is provided by James Moyne (Applied Global Services and the University of Michigan), a long-time participant in the roadmap development process and soon-to-be co-chair of this particular working group. Moyne not only explains the cur-rent structure and likely 2013 priorities for the FI section, he also makes a very compelling case for its significant struc-tural revision. This is driven by both the changing nature of the requirements and challenges, and the available solu-tion technologies in the manufacturing systems and information technology domains.

The PIDS summary is given by Kwok Ng and Charles Cheung of the Semiconductor Research Corp. (SRC) and the National Institute of Standards and Technology (NIST), respectively. This area will not see the same kind of structural change as in FI, but the authors do highlight which areas will see the greatest medium- and long-term challenges and the likely activity to address them.

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The Factory Integration (FI) chapter of the International Technology Roadmap for Semiconductors (ITRS) seeks to define a roadmap for factories and enterprise systems that are designed and integrated for efficient and effective development and manufacturing. The FI Technology Working Group (TWG), made up of semiconductor FI experts from around the world, evaluates the challenges and determines the near-term and longer-term technology requirements and potential solutions to meet these requirements. The FI TWG is divided into five thrust teams: Factory Operations (FO), Production Equipment (PE), Automated Material Handling Systems (AMHS), Factory Information & Control Systems (FICS), and Facilities.

The entire ITRS is updated every odd year, so major revisions occurred dur-ing 2011 that were published in 2012, and major revisions will occur again in 2013. The 2011 Future Fab publication on the ITRS summarized the events of the 2011 major revision year.[1,2] Since only minor revisions occurred this year, this article will focus on summarizing the 2011-12 chapter structure and providing a glimpse into plans for the 2013 major revision year.[3]

FI Activity Focus for 2011-12ITRS chapters are structured to identify

requirements in various areas, define the challenges in meeting those requirements, and identify and provide a roadmap for potential solutions to address these requirements. The FI requirement drivers are summarized in Figure 1.

The FI difficult challenges are broken into shorter-term (through 2019) and longer-term (beyond 2019) challenges in the FI chapter, and can be summarized as follows:[2]

Difficult Challenges Through 20191. Responding to rapidly changing, com-

plex business requirements2. Managing ever increasing factory com-

plexity3. Achieving growth targets while margins

decline4. Meeting factory and equipment reliabil-

ity, capability and productivity require-ments per the roadmap

5. Emerging factory paradigm and next wafer size change

Difficult Challenges Beyond 20191. Meeting the flexibility, extendibility and

scalability needs of a cost-effective, leading-edge factory

ITRS CHAPTER: Factory Integration

2. Managing ever increasing factory com-plexity

3. Increasing global restrictions on envi-ronmental issues

4. Post-conventional CMOS manufacturing uncertainty

These challenges are explained through a delineation of issues that relate to these challenges. As an example, Figure 2 shows this delineation for the first two shorter-term challenges, with callouts highlighting items that were added or moved in the 2011-12 version of the roadmap.

The FI potential solutions to address these challenges are presented through narrative and tables that define the tech-nologies that can address the challenges,

as well as a timetable for the migration of these technologies from research through development, qualification/pre-production, through continuous improvement. Figure 3 is an excerpt from the Potential Solutions table in the Production Equipment sub-chapter, with callouts highlighting poten-tial solutions that were discussed at length during the 2011-12 FI TWG meetings.

As can be seen from a comparison of Figures 2–4, the 2011-12 FI TWG efforts are punctuated by a focus on topics such as the movement from reactive to predic-tive, integration (e.g., of fab with facilities), and mechanisms for improved control and repeatability. Download and read the 2012 ITRS (www.itrs.net) to get a complete presentation of the challenges, issues and

James MoyneApplied Materials

Multiple lots per carrier and/or fewer wafers per carrier. Get new products to customer much faster.

Cycle Time Reduction and Operational Flexibility

Output per tool must increase:Find breakthrough solutions that result in significant increases in good wafer out and increased OEE (e.g. APC, e-Diag)

More Good Wafers Out per Tool

The 300 mm factory is much more automated and must be designed to transport hot-lots and hand-carries.

Highly Automated Factory

What are stretch goals for cycle timefrom ground-breaking to first full loop wafer out. How to achieve quicker shrink?

Reduce Time to Money

Increased floor space effectiveness: Don’t want each new generation to drive big increase in cleanroom size, esp. since fab is segregated Cu/non-Cu and new metal layers added at each node.

Factory Size Is Becoming an Issue

Figure 1. This chart summarizes requirement drivers for factory integration.

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potential solution roadmap for FI in semi-conductor manufacturing.

Looking Ahead to 2013As we move into the 2013 major revi-

sion year, we are considering a number of changes to the FI chapter and even the FI TWG itself.

One example is the elimination of the “silo” approach to specifications. As noted above, the FI chapter is broken into sub-chapters (Figure 4), each with its own set of roadmap specifications. Though this approach was appropriate for the 1990s and 2000s, the information age has forced a reevaluation. For 2013, it is

proposed that these “silos” be eliminated, and information technology be presented as common to all areas. This will highlight the commonality of technologies across the fab, facilities, and even up and down the supply chain. It will also promote a stronger level of integration of and stand-ardization across technologies. Further, it will allow for the consistent incorporation of non-nanomanufacturing FI technologies into the roadmap. The net result of this fundamental change to the FI chapter is that sub-chapters will likely be reorganized or eliminated. The reorganization would likely be along data-driven (rather than physical partitioning) boundaries.

2013 updates will likely focus on con-tinued emphasis on some of the 2011-12 concepts, but also the introduction of new challenges and ideas. The following are examples of some of these ideas.

FI solutions for 300 and 450 mm – It is postulated that, at the FI level, require-ments and solutions for 300 and 450 mm wafers should be fundamentally the same. This will allow for leveraging of technolo-gies across these domains, and will pro-mote a smooth migration of FI from 300 mm to 450 mm technologies.

Look outside the semiconductor indus-try – Considering the acceleration of infor-mation technology in recent years, FI, more

than any other ITRS chapter, must leverage solutions from other industries. Challenges such as the movement from reactive to predictive, “big data” (see below) and sup-ply chain integration are pervasive across all of manufacturing. The semiconductor industry must accelerate the leveraging of general manufacturing solutions.

Align with a data-driven approach – The advent of concepts such as cloud computing and autonomous agents is part of a general movement toward data-driven solutions. The FI chapter could be reor-ganized to promote commonality of data-driven solutions across all elements of the FI space.

ITRS CHAPTER: Factory Integration Your Single Source for Critical Process Infrastructure | www.tfs-us.com

Production Equipment Potential Solutions (Excerpt)

First Year of IC Production 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020-2026

Productivity and Quality Improvement

Process quality improvement through APC (including R2R control, FDC, SPC and Fault Prediction) as a design-in requirement; designed-in APC inside or outside tool, communicating with fab-wide APC system

Equipment functional verification through techniques including fingerprinting and equipment health monitoring

….Enhancement of equipment systems (sensors, models, etc.) and reporting to support the move from reactive to predictive capability…including predictive scheduling, fault prediction, health prediction, predictive maintenance, virtual metrology, and yield prediction

Prognostics Health Management (PHM) capability to provide a common health indication capability across tools, and to provide input to a predictive tool health model

Predicitive tool health models to schedule maintenanceon need but before tool failure or yield impact

Standardized equipment data model …..

Build chambers to be matched and provide necessary data to support confirmation of this matching; migration of Chamber Variance Reporting to Chamber Variance Correction Systems; reporting of data necessary to support chamber matching

450mm

mmuiremen

Designed-in APC inside or outside tool,

communicating with fab-wide system

Fingerprinting and equipment health

monitoring

Enhancement of equipment systems to

support move from reactive to predictive

Prognostics Health Management (PHM)

common health indication capability

across tools

Predictive tool health models for

predictive maintenance

Standardized equipment data model

Built-in chamber matching; movement

from chamber variance reporting to

chamber variance correction

Figure 3. Excerpt from Potential Solutions tables: Callouts highlight potential solutions that were discussed at length during the 2011-12 Factory Integration TWG meetings.

FI Difficult Challenges: Noteworthy Additions and Modifications Table FAC1 Factory Integration Difficult Challenges

Difficult Challenges Through 2019 Summary of Issues

1. Responding to rapidly changing, complex business requirements

2. Managing ever-increasing factory complexity　 Addressing need to minimize energy resource usage and waste; e.g., need to

integrate fab management and control with facilities management and control

Comprehending increased purity requirements for process and materials

Supporting adoption and migration of equipment communication protocol standards

to meet ITRS challenges and be in sync with emerging technologies in systems

communication and management such as XML and cloud computing.

Meeting equipment design challenges in maintaining yield and improving maintenance

practices resulting from movement to new process materials that may be corrosive, caustic,

environmentally impacting, molecularly incompatible, etc.

Addressing factory integration challenges to assess and integrate EUV systems into the

Addressing AMC challenges through possibly changing factory

operation approach (e.g., maintaining vacuum in specific areas), as well as providing

necessary interfaces, information and technologies (e.g., virtual metrology and APC).

Maintaining equipment availability and productivity while managing increase in

sensors and systems within and outside the equipment, coordinated to support

new paradigms (e.g., management of energy expended by the equipment and the

fab in general, movement from reactive to fully predictive).

Linking yield and throughput prediction into factory operation optimization.

Real-time simulation in lock-step with production for operations prediction.

Items Added and Moved Up

Integration of fab and facility management

and control

Increased emphasis on communication

standards

Maintain availability and productivity …

move to predictive

Moved from “after 2017” to “before

2019”

Figure 2. Taking a closer look at the first two shorter-term challenges, callouts delineate items that have been added or moved up for the 2011-12 FI chapter.




Increased focus on the movement from reactive to predictive – This concept has been accelerated in the FI chapter over the past few years and will continue to grow in importance. Concepts such as predictive maintenance, predictive sched-uling and metrology prediction (“virtual metrology”) will be expanded to support yield prediction and fab component simu-lation in lock-step with reality. This predic-tion roadmap will draw heavily from other industries and will focus not only on the prediction technologies, but also on the migration of existing systems to predic-tion-ready systems.

Re-think/define key performance indi-cators (KPIs) for FI – The KPIs for FI (see Figure 1 for examples) must be revisited to make sure they are capturing the goals of today’s fabs. A good example here is defining the Wait Time Waste metrics for equipment productivity, which is currently a SEMI standardization effort.

Address the “big data” problem – The information age has seen an explosion in the depth and breadth of data. This explo-sion delivers benefits, but also creates challenges in dealing with data sizes and rates that are not unique to this industry. A roadmap for dealing with the “big data” problem must be devised that addresses semiconductor manufacturing challenges while moving to align this industry with other manufacturing arenas.

Consider new control paradigms – The concept of centralized control is being questioned in other industries and should be addressed in the FI roadmap. The pos-sibility of autonomous control (e.g. “auton-omous agents”) should be considered. Predictive control should be explored as part of the movement from reactive to predictive. Control performance should be quantified. Time-based (time-synchro-nized) control should be considered in some instances.

Stronger focus on technology ramps and cost – As technology cycles get short-er and shorter, the importance of technol-ogy ramp speed and cost grows. Specific challenges, solutions and metrics for tech-nology ramp should be considered. For example, the integration of process control and design for manufacturability (DFM) should be considered to reduce the num-ber of redesign cycles in a new technology ramp-up.

Consider that some FI technologies might be limiters to achieving ITRS mile-stones – The importance of FI technolo-gies continues to grow in the fab to the point that, in some cases, these technolo-gies might be the barriers to achieving the next technology node. As an example, process control (e.g., run-to-run control), which was once an add-on technology, is now a required technology in most 300 mm processing and indeed is a require-

ment to achieving necessary yields in some emerging technologies. These critical FI technologies must be identified, and a roadmap devised that will keep pace with the overall ITRS requirements.

SummaryThe Factory Integration chapter of the

ITRS focuses on the integration of factory components in order to efficiently produce the required products in the right volumes on schedule while meeting cost targets. Over the past two years, this chapter has been updated to focus on technologies, such as prediction and facilities integra-tion, that will be required components of the fab of the future.

As we move forward into 2013, we are considering major revisions to the FI chap-ter. These revisions will allow the chapter to better address the challenges of factory integration in the information age in such a way as to provide a consistent and robust solution across the factory integration space.

AcknowledgmentsThe author would like to acknowledge

the efforts of the ITRS Factory Integration Working Group in making this article pos-sible, especially Gopal Rao for supporting the work and contributing to the chap-ter content. A full list of members of the Factory Integration Working Group can be found here.

References1. R. Oechsner, “ITRS Chapter: Factory

Integration,” Future Fab International, Issue 40, January 2012.

2. International Technology Roadmap for Semiconductors, www.itrs.net.

3. J. Moyne, “International Technology Roadmap for Semiconductors (ITRS)

Factory Integration Chapter Update: 2013 Major Revision Plans,” invited, APC Conference XXIV, Ann Arbor, Mich., September 2012.

About the Author

James MoyneJames Moyne is the standards and

technology specialist for Applied Global Services at Applied Materials. He received his B.S.E.E., B.S.E.–Mathematics, M.S.E.E. and Ph.D. from the University of Michigan, where he is currently an associate research scientist in the Department of Mechanical Engineering. Moyne has experience in advanced process control, database tech-nology and sensor bus technology. He also holds patents on software control and manufacturing prediction technologies. He serves as the chair of semiconductor standards efforts and is co-author of a number of SEMI standards in process con-trol, sensor/actuator networks and data quality. He has been a member of the ITRS Factory Integration TWG for four years.

• Link to 2011 ITRS Factory Integration Chapter



ITRS CHAPTER: Factory Integration

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Factory Operations

Production Equipment

AMHS Factory Information & Control Systems

Facilities

UI

Figure 4. The current FI chapter is divided into five sub-chapters, as shown above. For 2013, those ‘silos’ could be eliminated.





http://www.itrs.net/Links/2011ITRS/2011Chapters/2011Factory.pdf



The Process Integration, Devices, and Structures (PIDS) chapter of the ITRS deals with the main IC devices and struc-tures, their performance, and reliability. The chapter emphasizes physical and electrical requirements and characteristics, considering physical dimensions and key electrical device parameters such as per-formance, leakage and reliability.

The main goals of the ITRS include identifying key technical requirements and challenges critical to sustain the historical scaling of CMOS technology per Moore’s Law, and to stimulate the needed R&D to meet the key challenges. The PIDS chapter is divided into the following major sections: Logic, DRAM, Non-Volatile Memory, and Reliability.

Difficult ChallengesProcessing modules, tools, material

properties, etc., are presenting difficult challenges to continue scaling. We have identified these difficult challenges and summarized them in Table PIDS1 of the 2011 Edition. These challenges remain simi-lar and have the following categories:

Short-Term (2012-2018)1. Scaling Si CMOS with thin-body channel

2. Implementation of high-mobility CMOS channel materials

3. Scaling of DRAM and SRAM4. Scaling high-density non-volatile mem-

ories5. Reliability due to material, process and

structural changes, and novel applica-tions

Long-Term (2019-2026)1. Implementation of advanced multi-gate

structures2. Identification and implementation of

new memory structures3. Reliability of novel devices, structures

and materials4. Power scaling5. Integration for functional diversification

We refer readers to the table of the 2011 publication for more details.

Sub-Section Status and UpdateLogic: There are no changes to the

logic section for the 2012 update. For logic technologies, there is a tradeoff between speed performance and power. Four technology options are currently identi-fied: high performance (HP); low operat-ing (dynamic) power (LOP); low standby

ITRS CHAPTER: Process Integration, Devices, and Structures

power (LSTP); and III-V/Ge, which com-bines high performance with low power using alternate channel materials.

The first three logic technologies are based on conventional silicon technolo-gies, while the last is based on alternate channel materials. In this case, it is expect-ed that III-V will be used for the n-channel and germanium for the p-channel. It is forecast to be in production in 2018.

DRAM: DRAM is expected to remain as a 1T-1C cell structure for the foreseeable future. The capacitor scaling is getting increasingly difficult. For cell size, 4F2 is the limit for the next 15 years.

The only updates to this section are on the DRAM cell FET structure transition to vertical-channel transistor, and the transi-tion of cell size factor from 6F2 to 4F2. Both are delayed by one year from 2013 to 2014 (Table PIDS4).

Non-Volatile Memory: Non-volatile memories include three-terminal charge-storage FETs and two-terminal non-charge-based structures. The three-terminal charge-storage FETs are floating-gate (NOR and NAND) and charge-trapping (NOR and NAND); the two-terminal non-charge-based are ferroelectric RAM (FeRAM), phase-change memory (PCRAM), magnetoresistive RAM (MRAM) and spin-transfer-torque MRAM (STT-MRAM).

Among the many types, floating-gate FETs still dominate NAND. It is expected that 3D structures will be used, and they mostly will use charge-trapping FETs. Two-terminal (non-charge-based) cells are for more diverse applications, and an effi-cient selection device needs to be devel-oped and integrated.

The only changes in this update are for FeRAM (Table PIDS5b). The more signifi-cant changes:

• New nodes are introduced 1-2 years sooner.

• Cell size is increased.• Capacitor effective area and footprint

are increased. Capacitor structure tran-sition from stacked to 3D is delayed from 2017 to 2021.

• Capacitor voltage is increased.• Minimum switching charge is

decreased.

Reliability: This section addresses reliability issues associated with scaling and new materials. It quantifies reliability requirements for early failures, both on the chip level and transistor level. There is no change in this update.

Forward for 2013In the 2013 revision, more major

changes will occur mainly in the logic section. To forecast transistor perfor-mance, TCAD modeling will likely be used, in addition to MASTAR, which is a compact model-based tool.

With the clock frequency of circuits slowing down, transistor speed (I/CV) will also be relaxed from the 13% increase per year. One of the low-power technolo-gies, LOP, will be eliminated, so LSTP will become the only low-power technology and will be renamed to LP—covering both low dynamic power and low stand-by power.


the efforts of the ITRS Process Integration, Devices, and Structures Working Group in making this article possible. A full list of members of the Process Integration, Devices, and Structures Working Group can be found here.

Kwok Ng,1 Charles Cheung2 1Semiconductor Research Corp. 2National Institute of Standards & Technology

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FRONT END OF LINEClick here to return to Table of Contents


Undoubtedly, the front end of line (FEOL) part of the ITRS contains the two biggest “problem” areas of the roadmap, and I am happy that we have articles on both lithography and front-end process-es in this section.

What we all want is what is some-times called in the patent-drafting pro-fession “free beer.” This refers to a claim in a patent that is so broad that no mat-ter what you invent you will infringe the claim: Everybody wants free beer, but no one knows how to make it. In ongo-ing CMOS scaling, the free beer is to have a CMOS process that enables high performance (HP), low operating power (LOP), and low standby power (LSTP)—of course all at the same time. That’s not even mentioning things like cost, reliabil-ity, resilience, etc.

To achieve all of this, the arsenal of tricks that our engineers need to apply is impressive. In lithography, we need—at least temporarily—to look into tricks such as 193 nm double patterning (DP) or even multiple patterning (MP) because extreme

John SchmitzSVP and General Manager, Intellectual Property and Licensing, NXP Semiconductors

ultraviolet (EUV) and directed self-assem-bly (DSA) approaches are not yet ready. With EUV, for example, there are still issues with the source as well as mask and resist challenges to overcome. Other can-didates are maskless e-beam lithography and nanoimprint lithography (NIL) tools.

The front-end part of the equation also demonstrates many inventive steps: fully depleted SOI (FDSOI), high-k mate-rials, strain engineering, high-mobility channels, finFET architectures and more. But even the use of high-k materials has not kept us from running into a barrier in the equivalent gate oxide (EOT) thick-ness of about 0.6 nm.

There are also other big ticket devel-opments underway such as 450 mm wafers, alternative non-volatile memories that can scale such as phase-change memories (PCM), and 3D architectures that need through-silicon vias (TSVs).

Enough food for thought, I would say. And without an ITRS and the associated focus and joint work, all the above would likely form unsurpassable barriers.

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About the Authors

Kwok Ng Kwok Ng received his Ph.D. from

Columbia University in 1979 and his B.S. from Rutgers University in 1975, both in electrical engineering. He joined Bell Laboratories of AT&T in Murray Hill, N.J., in 1980, and continued on with its spin-offs Lucent Technologies and Agere Systems. Since 2007, he has been with Semiconductor Research Corp. in Research Triangle Park, N.C., serving as senior direc-tor of device sciences.

Charles CheungCharles Cheung received his B.A. and

Ph.D. from New York University in 1977 and 1983, respectively, both in chemistry. He joined Bell Laboratories of AT&T at Murray Hill, N.J., in 1983, and continued on with its spin-offs Lucent Technologies and Agere Systems. In 2001, Cheung became an associate professor in the Electrical and Computer Engineering Department at Rutgers University. Since 2007, he has been with the National Institute of Standards and Technology in Gaithersburg, Md., serving as the leader of the CMOS Devices & Reliability Project in the Semiconductor Electronics Division.

• Link to 2011 ITRS Process Integration, Devices

and Structures Chapter



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http://www.itrs.net/Links/2012ITRS/2012Tables/PIDS_2012Tables.xlsx



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Nikon Corporation has been one of the world’s leading optical companies for more than 90 years. Nikon devel-oped the world’s first production-worthy step-and-repeat photolithography tool in 1980. Since then, over half of all ICs printed have been manufactured on Nikon steppers and scanners.

With a long-established precedent of leading the industry through innova-tion and the continuous evolution of our proven lithography solutions, Nikon pro-vides photolithography systems span-ning the range of resolutions required by today’s IC manufacturers. From high-throughput i-line steppers to advanced immersion ArF scanners for 20 nm technology and beyond, Nikon deliv-ers exceptional performance with the lowest cost of ownership, and the most comprehensive customer support of any manufacturer.

In 2007, Nikon shipped the industry’s first 1.30 NA immersion scanner, the NSR-S610C, for 45 nm half-pitch produc-tion. Later that year, Nikon also intro-duced the NSR-S310F and NSR-S210D non-immersion scanners. These systems were evolutions of the S610C immer-

sion platform that incorporated Tandem Stage technology to provide optimal performance and cost of ownership for dry lithography applications.

Then, in 2009, to meet the stringent requirements for 32 nm double pattern-ing and provide extendibility to next-generation applications, Nikon introduced the NSR-S620D immersion scanner, which is based on the innovative Streamlign platform. This was followed in 2011 by the NSR-S320F, an evolutionary Streamlign platform-based system designed to deliver exceptional performance and productivity for the most critical dry ArF applications. The latest evolution of the Streamlign platform, the NSR-S621D immersion scanner satisfies the aggressive overlay and throughput requirements of high-volume immersion double patterning for 20 nm technology and beyond.

Next-generation lithography tech-niques continue to evolve, but IC makers need solutions today that will keep them on their aggressive technology road-maps. With a history of innovation and evolutionary lithography solutions, Nikon will be there to ensure you maintain your production timelines.

Proven Solutions Through Evolution

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LITHOGRAPHYClick here to return to Table of Contents

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Extending lithography to smaller dimen-sions has always been difficult, and this year is no exception. The semiconductor industry needs to select a lithography method for 22 nm half-pitch DRAM and 16 nm half-pitch Flash memory by the end of 2012. This same date was specified in the 2009 roadmap, but a decision has not yet emerged. This reflects the difficult technical issues facing leading-edge lithographers. ArF (193 nm) immersion lithography cannot be extended much below 40 nm half-pitch, and ArF immersion with double patterning will not meet the half-pitches needed at the end of 2012.

The possibilities for further progress are triple or quadruple patterning, EUV lithog-raphy, or some novel alternative pattern-ing technique. The novel techniques cur-rently identified in the ITRS are maskless lithography (ML), nanoimprint lithography (NIL) or directed self-assembly (DSA).

Potential SolutionsPotential lithographic solutions for

DRAM and MPU critical levels are shown in Figure 1a, and potential solutions for Flash memory critical levels are shown in Figure 1b. The leading candidates for both are EUV first and ArF immersion with multiple patterning second.

EUV exposure tools use 13.4 nm light. EUV lithography has demonstrated the printing of minimum features less than half the size of the best that immersion lithography can do. It uses all reflective optics and reticles, requires exposures

in a vacuum, and requires novel light sources to provide sufficient exposure power. These are big challenges, but the industry has been working on them, and now EUV pilot exposure tools are avail-able and installed at several leading-edge fabs.

ITRS CHAPTER:LithographyMark NeisserSEMATECH

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The light source power for these tools, however, is behind schedule. Through the first half of 2012, neither power nor uptime was sufficient to expose the full lots of wafers needed for pilot production. This capability is necessary for semiconduc-tor manufacturers to commit to EUV for device production. Source manufacturers have made progress on both power and uptime, and might provide enough power for pilot production by the end of 2012. If they can do this together with a cred-ible promise of enough power for volume manufacturing in 2015, then companies can commit to EUV as their leading-edge lithography technique.

Alternative next-generation patterning techniques are not ready for various rea-sons. Maskless lithography involves direct writing of patterns in resist with e-beams. No mask is needed, which is appealing,

especially for low-volume applications. For any reasonable throughput, however, mas-sively parallel writing with a thousand or thousands of e-beams at once is needed. Such tools are under development, but no working prototypes exist today.

Nanoimprint involves stamping patterns in a photosensitive material using a 1X tem-plate and then curing the patterns in place. Tools are available for prototype work that can print high-resolution patterns, but defectivity after patterning multiple wafers is an issue that has not yet been resolved.

Directed self-assembly demonstrates great resolution and holds the promise for inexpensive pitch and/or critical dimension (CD) reduction. Evaluations of DSA have increased dramatically because of its great progress. However, because this technique can prepare only simple repetitive patterns, designs for chips must be modified if it is

Figure 1a. 2012 Table Lith3A – DRAM and MPU Potential Solutions

ITRS CHAPTER: Lithography Nikon. Evolution in Action. | www.nikonprecision.com

to be used. Also, full-wafer DSA defectivity needs to be demonstrated. Both of these issues will take substantial time to resolve.

Since none of these patterning technolo-gies will be ready for pilot line use by the end of 2012, multiple patterning, such as triple or quadruple patterning, will be the only available alternative to EUV. Multiple patterning would involve such complicated processing and long process flows that the

industry is faced with a dilemma if planned EUV source powers are not available: Choose between using EUV in 2013 despite slower throughput and higher costs than planned; or accept long product develop-ment cycles, complicated process flows, high mask costs, and numerous process steps resulting in long production times.

Near-Term ChallengesLooking at the near-term challenges

from this year’s roadmap (Figure 2), the top five challenges clearly need to be resolved to make either EUV or multiple patterning work for the upcoming nodes. The first two issues are the difficulty and complexity of multiple patterning. The next two reflect the issues that are key for mak-ing EUV lithography a successful technol-

ogy. The fifth challenge involves the diffi-culty and already stretched performance of current lithography. This can also be seen in the 2012 Lithography tables that will be published with the roadmap, where many near-term needs are colored red, mean-ing “manufacturable solutions are not yet known.”

NAND Flash timeline

Narrow options

Narrow options

Figure 1b. 2012 Table Lith3A – Flash Potential Solutions

Directed self-assembly demonstrates great resolution and holds the promise for inexpensive pitch and/or

critical dimension (CD) reduction.




Long-Term ChallengesIn the longer term, either a path for

improving the resolution of EUV lithogra-phy or an alternative form of patterning that is manufacturable will be needed to maintain progress according to the indus-try roadmap. Improving EUV resolution

will require either increasing the numeri-cal aperture (NA) or reducing the EUV wavelength to less than the current 13.4 nm wavelength. Either option will require more source power and improved mirror

technology for EUV optics and reticles. A second challenge will be implementing EUV double patterning as device patterns get smaller. Even if single patterning will resolve the fundamental pitch of the pat-tern, two-dimensional structures could require double patterning. Doing this with

EUV will put pressure on throughput and cost, and is another reason source power must be increased.

Of all the alternative technologies in the roadmap, DSA has had by far the most

ITRS CHAPTER: Lithography

Near-Term Challenges (2011-2018)

(16 nm Logic/DRAM @ HVM; Flash 11 nm @ optical narrowing with 16 nm in HVM)

Cost and cycle time of multiple patterning - especially for more than 2x

Optical mask complexity

EUV source power

Defect "free" EUV mask availability

Mask infrastructure availability

EUV resist that meets sensitivity, resolution, LER requirements

Process control on key parameters such as overlay, CD control, LWR with multiple patterning

Retooling requirements for 450 mm transition (Economic & Technology Challenges)

Figure 2. 2012 Table Lith1A -- Near-Term Challenges

Long-Term Challenges (2019 - 2025)

(11 nm hp @ HVM)

Higher source power, increase in NA, chief ray angle change on EUV; mask material and thickness optimization

EUV with multiple exposures for 2D patterns

Defect-free DSA processing

DSA-compatible design rules

Selection of new EUV wavelength taking resist, mask, source and tool technology into account

Metrology tool availability to key parameters such as CDU, thickness control, overlay, defect

Figure 3. 2012 Table Lith1B -- Long-Term Challenges

published activity in the past year. It has the promise of high throughput and high resolution with low processing cost. But it has two major challenges to overcome. One is the challenge of defects. Some progress has been reported that shows potential for low defects, but no one has reported a manufacturable level of defects. The second is design. Using dem-onstrated processes, DSA can make arrays of parallel 1:1 lines and spaces, but turning these lines and spaces into actual device patterns will require cut levels and other secondary exposures and processing. To use the resulting patterns in real devices will also require special designs and design software.

Metrology is another challenge. As CDs diminish, specifications require higher res-olution and more precise measurements. In some cases, such as particles embed-ded in resist, suppliers measure the defect size that they can measure rather than the actual defect size needed. Improved metrology will pose a significant challenge for future nodes. Figure 3 lists all the chal-lenges.

SummaryThe semiconductor industry is look-

ing to EUV lithography to enable smaller feature resolution and further progress in shrinking the minimum pitches of semicon-ductor devices. The alternative, extending ArF immersion lithography to the criti-cal levels of upcoming device nodes, will require triple or quadruple patterning and would impose greater process complexity, high costs and low throughput.

The alternative patterning technolo-gies of maskless lithography (direct-write e-beam), nanoimprint and directed self-assembly will not be ready in time for the next lithography choice. The rate of EUV

infrastructure development and particu-larly the rate of progress in improving EUV light sources will ultimately determine what path the industry takes.

AcknowledgementsThe author would like to acknowl-

edge the efforts of the ITRS Lithography Working Group in making this article possible. A full list of members of the Lithography Working Group can be found here.

About the Author

Mark NeisserMark Neisser is the lithography materi-

als research manager at SEMATECH. He has worked in the semiconductor industry for more than 25 years and has extensive experience in lithography, lithography resolution enhancement development, and lithography materials such as photoresists, antireflective coatings and lithography ancillary materials. He received his Ph.D. in organic chemistry from the University of Michigan. He has published more than 50 papers and is an inventor on more than two dozen U.S. patents.

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Of all the alternative technologies in the roadmap, DSA has had by far the most published activity

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Hitachi High Technologies America (HTA) supplies state-of-the-art dry plas-ma etch systems to world-leading SC and HDD manufacturers. HTA customers rely on Hitachi etch technology, innovation and reliability to help them succeed in creating today’s most advanced micro-processors, DSPs, analog ICs, memory devices and HDD TFHs. Hitachi etch systems are renowned for their superior technology and production-proven reli-ability in the most demanding SC and HDD manufacturing environments.

New materials and processes in the SC and HDD industries push the limits of etch technology and require etch tools that can be highly flexible and extend-ible. The Hitachi microwave ECR (M-ECR) plasma source with its high-plasma den-sity operating at ultra-low pressure is the most capable source in the industry. Whether you’re etching basic poly gates and STI or latest-generation metal gates and low- dielectrics, the Hitachi M-ECR is the performance leader.

For new novel materials, includ-ing non-volatile metals/metal oxides, Hitachi’s EMCP etch technology allows for industry-leading process perfor-mance with true manufacturing capabil-ity. Whether it’s alumina for HDD TFHs or metallic alloys for MRAM/FeRAM devices, the EMCP delivers process results while allowing for long mean wafers between cleans for these non-volatile materials.

Beyond Hitachi’s leading etch tech-nology, HTA provides award-winning service support and spare parts man-agement for Hitachi etch products. HTA will design customer-specific ser-vice plans and parts management to ensure your Hitachi etch tools per-form optimally and help you to meet your stringent development and pro-duction goals.

Add Hitachi etch technology to your processes today and know you’ll be ready for tomorrow’s demanding etch requirements.

Hitachi High Technologies America – A Better Way to Etch

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The Front End Processes (FEP) road-map focuses on future process require-ments and potential solutions related to scaling MOSFETs, DRAM storage capaci-tors and non-volatile RAM (Flash, phase-change and ferroelectric). The roadmap encompasses the materials, electrical and physical specifications, tools, and the unit and integrated processes starting with the silicon wafer substrate and extending through the contact silicidation processes and the deposition of strain layers.

Included in the technology and process areas covered are high-performance, low-operating-power and low-standby power logic devices; memory devices including DRAM, Flash, phase-change memory and FeRAM; thermal/thin films/doping; chemical mechanical polishing (CMP); starting materi-als; surface preparation; and plasma etch.

The FEP section of the ITRS forecasts the scaling-driven (dimensional, perfor-mance and power) technology require-ments and potential solutions for each of the above technology areas. These requirements are largely model-based.

The potential solutions serve to bench-mark known examples of possible solu-tions; they should not be considered the

only approaches. Many of the solutions are enabled by innovations in materials and structures. Indeed, innovative, novel solutions are sought, the need for which is identified by the red regions of the requirements tables.

MOSFET Scaling: New Materials, Structures

High-k metal gate processes finally made their way into wide-scale produc-tion in 2011, just as the end of planar bulk CMOS appeared on the near horizon. Because gate length (Lg) scaling has slowed until extreme ultraviolet (EUV) lithography production issues can be resolved, CMOS technology continues to evolve through the use of non-planar and fully depleted silicon-on-insulator (FDSOI) devices.

These non-conventional MOSFET struc-tures were being introduced into manu-facturing in 2012 for non-planar multi-gate devices, and are anticipated in 2015 for planar/non-planar FDSOIs. The challenges associated with integrating these diverse new materials and structures were a cen-tral theme of the 2011 FEP chapter, and remain so in 2012.

ITRS CHAPTER:Front End ProcessesMike Walden,1 Joel Barnett,2 Raj Jammy,3 Chris Hobbs3 1MEMC 2Tokyo Electron America 3SEMATECH

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Channel strain engineering to increase mobility, which was introduced into manu-facturing several technology generations ago, dominates MOSFET scaling now and likely in the future. Strain provides up to 40% of performance enhancement cur-rently, but continued improvement in strain engineering and its application to new device structures (non-conventional CMOS) are identified as difficult challenges.

Another option to increase mobility without significant disruption to current

manufacturing strategies is through the use of high-mobility channel materials, such as germanium and III-Vs on silicon. Efforts to heterointegrate these new chan-nel materials continue to be intensely pur-sued for additional performance gains, and efforts are expected to continue into 2013. The implementation into manufacturing of these materials will not be trivial, creating an entirely new portfolio of processing and integration challenges.

The transition from extended bulk CMOS to such non-classical device struc-tures is not expected to take place at the same time for all applications and all chip manufacturers. Instead, a scenario is envisioned where a greater diversity of technologies are competitively used at the same point in time. Some manufacturers might transition to non-classical devices earlier, and others will adopt extensions of incumbent technologies. This is reflected in the tables projecting high-performance

and low-power device technology require-ments for multiple approaches in 2013 through 2019.

In 2011, FEP worked closely with the Design and PIDS groups on a Vcc scaling roadmap and associated device metrics, including Ion, Ioff, CV/I, etc., for high-performance, low-performance and low-standby-power (LSTP) devices. The values guided the ITRS trends for module met-rics (gate stack, junctions, contacts, etc.). These efforts continued into 2012, and will

be the foundation for 2013 revisions.The scaling roadmap for high-perfor-

mance (HP), low-operating-power (LOP) and LSTP technologies were captured as separate tables in the 2011 ITRS FEP update. This categorization in separate tables becomes more relevant as the tech-nology options (and scaling roadmap) for performance and power start to vary rather significantly for future device gen-erations. For example, the advanced high-k/metal gate stack technology appears imperative for HP devices in 2012 and beyond, while conventional SiON/poly could still be the mainstream choice for low-cost LSTP devices through 2012. Also, by capturing the scaling pathway for HP, LOP and LSTP in different tables, specific module-level scaling challenges associated with the technologies for performance and/or power can be addressed. However, since LOP parameters are increasingly similar to HP (different only by adjusting

ITRS CHAPTER: Front End Processes Hitachi XT Next - A Better Way to Etch | www.hitachi-hta.com

Vt and Vdd), there is a proposal to drop this table in 2013.

Gate stacks are still one of the most dif-ficult challenges for future device scaling. Despite a few reports in literature, con-tinued scaling of higher-k stacks below a 0.6 nm equivalent oxide thickness (EOT) remains a major hurdle. Gate electrode work function, resistivity and compatibility with CMOS technology are key attributes for any scaling efforts. And though there is a strong desire to continue with incumbent technology options, new-candidate gate electrode materials might be needed.

Replacement gates appear to have become widely accepted, but additional challenges remain. These include contin-ued scaling of the dummy gate opening

for subsequent high-k metal gate inser-tion, the abruptness of shallow junctions, parasitic resistance and contact silicida-tion. The introduction of new materials is also expected to pose added challenges and drive new techniques to dope and activate for low external series resistance. In addition to the scaling-imposed need to produce very shallow, highly activated junctions, the limited thermal stability of most high-k and high-mobility materials is expected to place new boundaries on thermal budgets associated with dopant activation.

Memory AdvancesIn memory, standalone DRAM devices

are being scaled aggressively with vari-

Figure 1. The FEP Chapter scope is noted within this illustration of a planar CMOS. Other structures are depicted in the inset.

The transition from extended bulk CMOS to such non-classical device structures is not expected to

take place at the same time for all applications and all chip manufacturers.

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ations of stacked capacitor structures. High-k materials are now in production for DRAM capacitors using metal-insulator-metal (MIM) structures. High-k materials were required in 2012 for floating gate Flash memory interpoly dielectric and are expected to be needed by 2013 for tunnel dielectric.

Flash continues to aggressively scale, with the first sub-20 nm devices released in 2011. Sub-15 nm device plans appear to be moving toward 3D stacked imple-mentations in a charge trap embodiment rather than the floating gate used today. FeRAM has a narrow commercial presence in specialty non-volatile applications using ferroelectric and ferromagnetic storage materials. Though two manufacturers have announced phase-change memory (PCM) devices as commercial memory offerings, the mass market has not yet materialized.

CMP, which has been extensively used for many years in shallow trench isola-tion (STI) formation and back end of line (BEOL), now sees its use in the front end expanding. This is particularly crucial in the manufacture of memory devices and implementation of gate-last metal gate integration schemes. Uniformity, selectivity and pattern density dependency continue to be hurdles for CMP, although the indus-try has risen to the associated challenges.

In starting materials, it is expected that bulk silicon will continue to dominate while alternatives, such as SOI substrates, will be increasingly used for specialized end product applications before entering the mainstream. The search for potential sub-strate alternatives will continue to be an application-driven necessity. The need for next-generation 450 mm silicon substrates to continue productivity gains poses an important economic challenge. Based on historical diameter change cycles, the

industry is already several years behind the pace to prepare the 450 mm silicon substrate for device manufacturing in 2015, though recent announcements have seemingly accelerated these efforts.

Front-end cleaning processes will con-tinue to be impacted by the introduction of new front-end materials such as higher-k dielectrics, metal gate electrodes, mobility-enhanced channel materials, non-planar channels and 3D memory devices. Scaled devices are expected to become increas-ingly shallow, requiring that cleaning pro-cesses become completely benign in terms of material removal and surface roughening. Scaled and new device structures will also become increasingly narrow and fragile, limiting the physical aggressiveness of the cleaning and drying processes that could be employed. In addition, these new device structures will require precise cleaning and characterization of vertical surfaces.

Defect densities are significant in light of the small feature sizes being pushed in memory and logic. Critical surface parti-cle sizes below 28 nm are currently not measurable and because epitaxial and ALD dielectric processes are now defect mag-nifiers, the models might no longer apply. In many fabs, a limit is derived from an assumed 1/x2 defect distribution mapping to a 40 nm sensitivity (currently the most stable measurement level). To provide a more accurate estimate of the number of defects allowed on a production wafer at a pre-gate clean, the yield value input to the surface prep models was increased—from 99% to 99.9%—in 2011 and retained in 2012. This simple change has resulted in values that more directly correlate to equipment particle specifications and pro-vide a more tangible roadmap.

Plasma etch patterning is a key process used across the entire process flow. In

ITRS CHAPTER: Front End Processes Hitachi XT Next - A Better Way to Etch | www.hitachi-hta.com

front end of line (FEOL) STI, gate, spacer, embedded SiGe, stress-memorization technique (SMT), contact open and per-haps silicon via are all impacted by dry etch. Technology scaling for gate density requires both critical dimension (CD) scal-ing and tighter CD distributions. The total variation of gate CD in the ITRS (12% of the physical gate width) is shared among several contributing sources, such as line width roughness (LWR) and process vari-ations (including across chip, across wafer, wafer to wafer and lot to lot). Through-pitch variation is not included because single gate pitch is assumed and used in advanced chips at the 20 nm technology node and beyond. The presence of LWR is becoming the biggest contributor to CD variation at the 20 nm technology node and beyond.

As non-planar transistors become necessary, etch becomes more challeng-ing. FinFET configurations bring new constraints to selectivity, anisotropy and damage control. New materials and structures drive the many new etch chal-lenges. Through-pitch gate CD variations (gate LWR, across-chip variation and across-wafer variation) must be modi-fied because of etch micro-loading, which becomes more critical as the gate CD shrinks. Optimization of the optical prox-imity correction (OPC) models is crucial to minimize gate CD variation among various patterns. To further improve their accuracy, etch-induced loading effects should be included in the OPC model. Similarly, distinction of dense vs. isolated pattern etch micro-loading effects are critical for SiGe recess etch. Emerging 3D chip stacking technology is using reac-tive ion etching to form through-silicon vias (TSVs) for die-to-die stacking, which impact the FEOL devices.

SummaryIn 2011, the FEP group worked with

other subgroups to refine the timelines (and tables) associated with the introduc-tion of emerging materials and devices. Changes were made across the FEOL spectrum to account for the correspond-ing infrastructure and process modules required for non-planar multi-gate devices and Ge or III-V/heterogeneous integration into advanced logic.

For memory devices, changes were made to account for the aggressive scal-ing of Flash and the implementation of 3D stacks in a charge trap embodiment. Strategic overview of the technology directions and the challenges that must be addressed for FeRAM and PCM devices were also provided. In 2012, only minor adjustments were implemented as prepa-rations were made to incorporate whole-sale changes in the 2013 roadmap.


the efforts of members of the ITRS Front End Processes Working Group in making this article possible. A full list of members of the Front End Processes Working Group can be found here.

About the Authors

Mike Walden Mike Walden is director, technical prod-

uct marketing at MEMC. He holds an M.S. in electrical engineering from Virginia Tech, and has more than 20 years’ experience in the silicon/semiconductor industry, including 11 years with IBM. He has been involved with the NTRS/ITRS since 1991, and is currently co-chair of the FEP Starting Materials group.




ITRS CHAPTER: Front End Processes

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Joel BarnettJoel Barnett received his B.S. in chemi-

cal engineering from the University of California-Berkeley in 1984. He is strategic project manager for surface preparation systems at Tokyo Electron America. He is the co-chairman of the SEMATECH Surface Preparation and Cleans Conference, and chair of the ITRS Surface Preparation team.

Raj JammyRaj Jammy is vice president of materials

and emerging technologies at SEMATECH. Previously on assignment from IBM, he has joined the SEMATECH staff and will continue to direct SEMATECH’s Front End Processes division as well as lead efforts to tap into emerging technologies with disruptive scaling potential. Jammy holds a doctoral degree in electrical engineering from Northwestern University.

Chris Hobbs

Chris Hobbs is the CMOS scaling pro-gram manager at SEMATECH. Prior to this, he was the non-planar project manager at SEMATECH and worked on advanced high-k/metal gate integration at Freescale and Motorola. Hobbs holds a doctoral degree in electrical engineering from North Carolina State University.

• Link to 2011 ITRS Front End Processes Chapter



BACK END OF LINEClick here to return to Table of Contents

In this section’s coverage of the inter-connect roadmap, Naeemi, Maloney and Stucchi rightly point out that Cu intercon-nect technology has enabled continued scaling and maturation in mainstream man-ufacturing for 15 years and counting. Rather than Cu having better conductivity than the Al(Cu) alloy it replaced, it has actually been Cu’s increased allowable current densities and larger range of multilevel damascene wire scaling factors (both smaller and larg-er) that have proven to be the key enablers for continued BEOL scaling. Without these two Cu attributes, Moore’s Law would have been stuck by the wiring!

The authors point out current and future challenges; these are familiar problems, but they are drastically growing in severity. For example, barrier thickness scaling to single nanometers, CMP control, insulator trade-offs in dielectric constant vs. mechanical

Dan EdelsteinIBM Fellow, Manager of BEOL Technology Strategy, T.J. Watson Research Center, IBM

strength, damage-free patterning, etc. It seems one major problem not reflected in this table is the radically increasing wire effective resistivity penalty from quantum size effects (on top of barrier volume frac-tion). Whether it’s Cu or an alternate metal-lic conductor (including carbon-based), it seems unrealistic to expect a flat 2.2 μ -cm effective resistivity vs. scaling for wires. Instead, listing the projected increases might trigger paradigm shifts in circuit wir-ing methodologies, including increased use of multilevel wiring hierarchies in all prod-ucts, not just the high-performance ones.

In any case, the degree of “redness” in the interconnect roadmap table confirms the severity of the problems and, as the authors suggest, conveys a sense of urgen-cy to the industry for breakthroughs and workarounds if we are to keep pace with the ITRS scaling trends.

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Tokyo Electron (TEL) is a leading supplier of innovative semiconductor production equipment (SPE) and flat panel display (FPD) production equip-ment worldwide. Product lines include coater/developers, thermal processing systems, plasma etchers, single-wafer deposition systems, surface prepara-tion systems, test systems, advanced packaging systems, gas cluster ion beam technology and metrology systems. In addition, TEL distributes high-quality computer systems, semiconductor devices and electronic components of other leading suppliers, as well as com-puter-network-related products.

To support this diverse product base, TEL has strategically located R&D, manufacturing, sales and service loca-tions all over the world. TEL is a publicly held company listed on the Tokyo Stock Exchange. Originally established in

Japan in 1963, TEL has grown to nearly 90 offices globally that engineer, manu-facture, sell and service semiconductor manufacturing equipment. TEL is cur-rently the world’s second-largest manu-facturer of semiconductor equipment.

TEL realizes that quality of life improves for all as business and civic organizations work collaboratively, making our world a better place in which to live and work. As an integral corporate value, we support a spirit of service by giving back to communities in which we have a presence across the globe. We intend to continue our contribution to the sustainable devel-opment of society by acting as a core base for the information and commu-nication technology sector, while also carrying on our effort to achieve tech-nological innovation through the devel-opment of new businesses.

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Over the past 15 years, copper inter-connect integration has matured from a leading-edge, relatively new technology toward a standard materials and process set. Over this period, its scalability has been repeatedly demonstrated through continuous improvement in materials, tool-sets, design and layout, and is a testament to the global community of technologists charged with interconnect fabrication. In a diminishing-returns fashion, however, the challenges facing interconnect going for-ward are increasingly daunting.

A collection of the most pressing chal-lenges documented in the 2012 ITRS Interconnect chapter (yellow representing identified but immature solutions, and red representing challenges with no known manufacturable solutions) is shown in Table 1.[1] Assembling the significant chal-lenges facing the interconnect community in this manner is visually striking, and con-veys the urgency that the interconnect world feels as it works to keep pace with the ITRS.

Among the key challenges the table highlights: the need for controllable, uni-form and contiguous deposition of barrier

metal for metal 1 at thicknesses below 2 nm after 2014; the need to minimize cop-per erosion from CMP, especially at tight pitch; the requirement to continually drive contact and via resistance to ever-lower values in the face of shrinking geometries and more dominant effects of barrier and other materials; the need for develop-ment of dielectrics of decreasing permit-tivity while maintaining sufficiently strong mechanical properties; and the required development of damage-free clean and etch processes.

Clearly, then, there is no shortage of challenging projects currently available to the OEM, IDM and materials companies participating in semiconductor intercon-nect—which is good news, since overcom-ing these red brick walls is critical to stay-ing on the cost reduction curve (Figure 1) that has been so vital to the continued economics that help to drive the semicon-ductor industry.[2] Furthermore, it seems unlikely that incremental materials, process and equipment improvements, trickling in at rates typical of other traditional, more mature industries, will be sufficient to overcome the technical challenges being

ITRS CHAPTER: Interconnect

Azad Naeemi,1 David J. Maloney,2 Michele Stucchi3 1Georgia Institute of Technology 2Intermolecular Inc. 3imec

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faced (although the outward movement of any given brick wall by just one technol-ogy node certainly has value). The devel-opment of step-change, radical improve-ments and novel, disruptive technologies might well be what is required for the semiconductor industry to drive onward.

It is hoped that, far from painting a gloomy view of the future for semicon-ductor interconnect, the appropriate R&D communities are invigorated by the strik-ing image embodied in Table 1. In a sense, the raison d’être of the ITRS is to spur new and creative approaches to seemingly intractable problems. There is plenty of room to participate in solving these prob-lems, for organizations ranging from small startup and venture-funded operations to established multinational corporations.

Equally important is the fundamental, curiosity-driven research from the world’s institutions of higher learning that is abso-lutely necessary in underpinning private-sector development. This research leads to the startups that create new materials, tools and processes and, equally impor-tantly, this research produces the univer-sity graduates who are so essential to sus-tainable innovation.

Encouragingly, solutions for many of the challenges referenced in this article would likely be implemented very quick-ly—thereby providing immediate payback and, it is hoped, suitable reward for disrup-tive innovation. As an example, as copper lines have been scaled to ever-smaller dimensions from about the 220 nm node in 1998 to the 14 nm node today, the asso-

Figure 1. Cost per transistor trend.[2]

ITRS CHAPTER: Interconnect TEL. Celebrating 50 Years. | www.tel.com

ciated copper diffusion barrier has taken an increasing, and currently disproportion-ate, volume of available conductor space of the very narrow trenches now required. This trend is illustrated in Figure 2.[3] If a suitable, drop-in replacement barrier to

copper diffusion that is no more than 1 nm

thick were available today, it would instantly be in high demand. Alternatively, the development of a conductor material to replace copper that requires no barrier would also be very attractive to the indus-try (if not as immediately implementable).

Clearly, though, both of these potential

Figure 3. The image on the left shows LELE-induced process variation (source: Stucchi et al., imec, IITC 2012), and the right image shows process-induced misalignment of via and metal line (source: Boyan Boyanov, Intel).

Frac

tiona

l Cu

area

Barrier thickness (nm)

1.00

0 1 2 3

12 nm HP17 nm HP28 nm HP

0.40

0.60

0.80

Limited metal ALDbarrier

Figure 2. Fractional Copper vs. Barrier Thickness.[3]

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pathways are very challenging and require innovation.

For another example, as scaling has continued to the 14 nm node and beyond, new reliability concerns are constantly emerging. Degradation in time-dependent dielectric breakdown (TDDB) is now one of the major concerns threatening early system failures. Processes such as dou-ble patterning using litho-etch-litho-etch (LELE) create offsets in wire dimensions and spacings[4] as shown in the left side

of Figure 3. These offsets add to the exist-ing local spacing variations induced by line-edge roughness (LER), thus further raising the electric field in the dielectric material between adjacent wires. In a simi-lar manner, the slightest via misalignment in narrowly spaced interconnects (Figure 3, right), even if permitted by current design rules, locally increases the electric field up to 2 MV/cm2 for advanced low-k materials. These effects will obviously lead to premature TDDB failures.

ITRS CHAPTER: Interconnect TEL. Celebrating 50 Years. | www.tel.com

Figure 4. Delay vs. copper and other possible choices for emerging interconnects.[5]

Interconnect in the Post-CMOS Era

As the electronics industry now looks realistically toward the post-CMOS era, interconnects will continue to be an ever-growing challenge. As always, the introduc-tion of new materials must be validated by breakthrough performance improvements that will justify the concomitant increases in cost and cost-of-ownership for the new tools, materials and processes. A post-CMOS era suggests possible deviations from the current silicon-based infrastructure, which will be costly and potentially difficult to support by the current semiconductor eco-system without significant performance improvements. For example, Figure 4 shows some possible options for interconnects for devices operating on computational state variables other than electronic charge. Unfortunately, interconnects for most novel state variables are inherently slow. This limi-tation can be overcome if the interconnect is shortened; however, shorter intercon-nects can be achieved only if novel devices have smaller footprints or fewer devices are needed for the same set of tasks.[5]

However, the move to non-CMOS-based computing is not imminent. In the meantime, with no clear path forward for novel interconnect introduction, there is a strong need for novel and creative solu-tions that offer a means to break through some of the red brick walls in Table 1. Any simplification of the current processing complexity through introduction of new tools, processes and materials could push out some of the red brick walls for at least a generation or two.

Tighter design specifications might be required to compensate for more fragile ultralow-k materials, and will no doubt introduce a higher cost and complexity. Finally, the ultimate success of finding new breakthrough interconnect technolo-gies continues to rest with the ecosystem of IDMs, suppliers, startup companies and universities, and the willingness to take creative risks to circumvent the red brick walls in the ITRS.


the efforts of the ITRS Interconnect Working

Year of Production 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026

Metal 1 wiring pitch (nm) 64 54 48 42 38 34 30 27 24 21 19 17 15 13 12

Metal 1 wiring half-pitch (nm) 32 27 24 21 19 17 15 13 12 11 10 8 8 7 6

Metal 1 A/R (for Cu) 1.80 1.90 1.90 1.90 2.00 2.00 2.00 2.00 2.00 2.10 2.10 2.10 2.10 2.20 2.20

Barrier/cladding thickness (for Cu M1 wiring)(nm)

2.6 2.4 2.1 1.9 1.7 1.5 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5

Cu erosion at minimum pitch (nm), 10% height, 50% areal density, 500 m square array

5.8 5.1 4.6 4.0 3.8 3.4 3.0 2.7 2.4 2.2 2.0 1.8 1.6 1.5 1.3

Contact A/R 33.3 39 32 38 48 50 63 68 74 81 90 87 119 115 123

Metal 1 wiring pitch (nm) * 90 80 72 64 56 50 44 40 36 32 28 26 22 20 18

Specific contact resistance ( -cm2) for n+ Si

1.2E-08 9.8E-09 8.2E-09 6.9E-09 5.8E-09 4.8E-09 4.0E-09 3.4E-09 2.8E-09 2.3E-09 2.0E-09 1.7E-09 1.4E-09 1.1E-09 9.3E-10

Specific contact resistance ( -cm2

2

) for p+ Si

1.8E-08 1.5E-08 1.3E-08 1.1E-08 9.2E-09 7.4E-09 6.2E-09 5.1E-09 4.3E-09 3.6E-09 3.0E-09 2.5E-09 2.1E-09 1.5E-09 1.1E-09

Specific via resistance ( -cm ) 2.9E-10 2.5E-10 2.1E-10 1.7E-10 1.4E-10 1.2E-10 1.0E-10 8.4E-11 7.0E-11 5.8E-10 4.8E-10 4.0E-10 3.3E-10 2.7E-10 2.2E-10

Conductor effective resistivity ( -cm) 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2

Interlevel metal insulator – effective 2.82-3.16

2.55-3.00

2.55-3.00

2.55-3.00

2.40-2.78

2.40-2.79

2.40-2.80

2.15–2.46

2.15–2.46

2.15–2.46

1.88-2.18

1.88-2.18

1.88-2.18

1.65-2.09

1.65-2.09

Copper diffusion barrier

Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Manufacturable solutions are NOT known

and etch stop – bulk

3.5-4.0 3.0-3.5 3.0-3.5 3.0-3.5 2.6-3.0 2.6-3.0 2.6-3.0 2.4-2.6 2.4-2.6 2.4-2.6 2.1-2.4 2.1-2.4 2.1-2.4 2.0-2.2 2.0-2.2

Table 1. Significant Challenges Facing Interconnect

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Group in making this article possible. A full list of members of the Interconnect Working Group can be found here.

References1. ITRS Interconnect Chapter, 2011 edition.2. “Microprocessor Cost per Transistor

Cycle,” www.singularity.com/charts/page62.html.

3. M. Mayberry, “What Lies Ahead for Interconnects and Devices,” Proc. IITC, Keynote, 2012.

4. M. Stucchi, Z. Tokei, S. Demuynck and Y.K. Siew, “Impact of Advanced Patterning Options, 193 nm and EUV, on Local Interconnect Performance,” Proc. IITC, 2012.

5. S. Rakheja and A. Naeemi, “Modeling Interconnects for Post-CMOS Devices and Comparison With Copper Interconnects,” IEEE Trans. Electron Devices, Vol. 58, p. 1319-1328, 2011.

About the Authors

Azad NaeemiAzad Naeemi is an assistant professor

with the School of Electrical and Computer Engineering at the Georgia Institute of Technology. His areas of research include performance modeling for emerging nano-electronic and spintronic devices and inter-connects, and circuit- and system-level implications of emerging technologies.

David J. MaloneyDavid J. Maloney is an account technol-

ogy director at Intermolecular, and previous-ly held several technical and management roles during a 15-year career with DuPont.

He holds chemistry degrees from McGill University (B.S.) and Texas A&M University (Ph.D.) and an MBA from UC Berkeley’s Haas School of Business.

Michele StucchiMichele Stucchi is a senior research engi-

neer at imec in Belgium. He received a mas-ter’s degree in electrical engineering at the University of Bari, Italy. His activities include characterization, modeling and reliability aspects of on-chip interconnects on 2D and 3D stacked ICs.

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METROLOGY, INSPECTION & FAILURE ANALYSIS


It is a privilege to introduce and highlight the major advances and future challenges in 2012 for updating the Metrology and Yield Enhancement chap-ters of the ITRS.

Alain Diebold and Christina Hacker present revisions in the Metrology Technology Requirements tables, where 3D measurements are key. Drivers include scaling, extreme ultraviolet (EUV) lithography and directed self-assembly (DSA), non-planar transistors, and emerging materials and devices. DSA patterning using block copolymers is of high interest.

It is important to note that measure-ment needs for critical dimensions (CDs) of isolated and dense lines, as well as for contact features, require accelerated research. There are many challenges asso-ciated with CD and defect measurements, and meeting the metrology needs for future generations will require advances in scatterometry and CD-SEM. New chan-nel materials and non-planar transistor structures continue to dominate front-end metrology concerns. One key new meas-urement need is for the measurement of contact resistance for nanostructures.

Lothar Pfitzner and Sabrina Anger present a summary from the Yield Enhancement TWG that depicts the current and future requirements for high-yield manufacturing of DRAM, MPU and Flash, and identifies show-stoppers and potential solutions for manufacturing.

The most important challenge in the near term for dimensions above 16 nm is estimated to be detection of small yield-limiting defects and their identification in contrast to nuisance defects. A second-priority challenge is process stability vs. absolute contamination level. The chal-lenge of detecting organic contamina-tion on surfaces persists. It is currently not possible in the fab to detect and identify nonvolatile organics on surfaces. Laboratory-scale instrumentation is not available.

Next-generation inspection along with in-line defect characterization/analysis and next-generation lithogra-phy are key challenges below 16 nm. Particle control as a whole is expected to gain even more importance with relation to next-generation lithography (NGL) technologies.

David SeilerChief, Semiconductor & Dimensional Metrology Division, NIST

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During 2012, the main emphasis of the Metrology Technology Working Group (TWG) was to revise the Metrology Technology Requirements tables and initiate new text for the 2013 revision of the ITRS. The key areas of interest from the ITRS were in the 3D nature

of measurement needs and in revising the Lithography Metrology Technology Requirements table to clarify critical dimension (CD) measurement require-ments. The need to measure 3D features and the films and structures fabricated on these features illustrates the link between

ITRS CHAPTER: Metrology lithography metrology and measure-ments done for Front End Processes (FEP) or Interconnect. These 2012 Metrology Roadmap updates are discussed below.

Key Technology Advances Impacting Metrology

In addition to scaling, three process technologies continue to drive the need for advances in metrology, including new lithography processes such as extreme ultraviolet (EUV) lithography and directed self-assembly, non-planar transistors, and emerging materials and devices. All of these require the measurement of 3D fea-ture dimensions.

One example is the finFET, where advances in finFET processing and manu-facturability have resulted in Intel’s use of the tri-gate transistor for the 22 nm half-pitch. Published images of the tri-gate show that the fin shape is not rectangu-lar, and the first manufactured fins have a rounded top.[1] This shape is critical because it is believed that the current flow is in the rounded region and not on the rectangular sidewalls.[2] The differ-ence is shown in Figure 1, and the impact of the shape on both lithography and FEP metrology is discussed below.

Lithography MetrologyThe 2012 Metrology Roadmap update

emphasizes revised on-wafer measurement requirements. The double patterning section of this table was revised, and sections on finFET and EUV patterning were added. The Lithography Metrology (Wafer) Technology Requirements table (Table 1) provides some of the key information. It is also important to note that, once again, the measurement need for CDs for isolated and dense lines, as well as for contact features, requires accel-erated research as indicated by the timing of the red indicator for no known solutions. This is also summarized in Table 1.

Based on the presentations made at the 2012 SPIE Advanced Lithography confer-

Alain C. Diebold,1 Christina Hacker21College of Nanoscale Science and Engineering, University at Albany 2National Institute of Standards and Technology

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Figure 1. CD metrology is challenged by the need to measure 3D line shape of new processes such as directed self-assembly of block copolymers (BCP). The left image shows an example of CD-small angle X-ray scattering (CD-SAXS) of BCP lines; at right, the estimated line profile with dashed lines indicates a 95% fit confidence. Figure courtesy Joe Kline (NIST).

Figure 2. In the pole figure (top) of multistep ALD HfO2 for monoclinic M(-111) plane (2 =28.4°, d-spacing of 3.15 Å), the red ring at the center shows fiber texture with the grains pointing almost normal to the surface. The bottom chart shows GIIXRD spectra of the same ALD HfO2. Vertical line positions indicate the monoclinic or tetragonal crystal planes responsible for the XRD peaks (the blue line shows position of M(-111) peak). Since the M(-111) reflection is very weak in the GIIXRD data, this figure shows the importance of using multiple XRD methods to access the crystal structure of ultra-thin high HfO2. Figure courtesy Relja Vasic.




ence, interest is high in patterning based on directed self-assembly (DSA) using block copolymers. There are many challenges associated with CD and defect measure-ments because of the similarities in the optical properties of the two most used copolymers. Recently, the CDs and feature shape of an array of block copolymer lines were measured using transmission small angle X-ray scattering (tSAXS).[3]

Advances in scatterometry and CD-SEM are required in order to meet the metrology needs for future generations. Mueller Matrix Scatterometry (MMS) provides more infor-mation at each wavelength than traditional ellipsometry-based scatterometry, enabling measurement of anisotropic structures, and MMS is being investigated as a means of advancing scatterometry.[4] Advances in CD-SEM include improved corrections for image drift.[5] CD-SAXS is being evalu-ated as a future CD measurement method.

Challenges associated with tSAXS include the fact that a transmission test structure has never been used in manufacturing.

FEP MetrologyNew channel materials and non-planar

transistor structures continue to dominate the discussion of FEP metrology. New channel materials include silicon; germa-nium alloys, germanium and III-V material stacks all require measurements for pro-cess and defect control. Although X-ray methods can provide characterization for blanket wafer samples, characterizing defects in the channel areas of patterned transistor structures is exceedingly diffi-cult. The goal is to provide high-through-put, non-destructive methods.

Continued scaling of high-k materials is driving the development of new processes that result in higher dielectric constants for hafnium oxide film stacks. Some of the pro-

posed processes result in single or mixed phases of monoclinic (k~16), cubic (k~29) or tetragonal (k~70) crystal forms of hafnium oxide.[6] Results from X-ray characteriza-tion of some of these films is presented in Figure 2. New optical models and an understanding of the variability of the grain texture are some of the metrology require-ments for these higher-k materials.

New memory materials have many unsolved problems that require advances in both fundamental materials characteri-zation and process metrology. The switch-ing mechanism for the function of redox-based memory is the subject of continued investigation.[7-8] Filaments are believed to form, and the reversibility of the fila-ments remains an open question.

InterconnectThe barrier thickness values and associ-

ated metrology precision were updated in 2012 to reflect the values found in the Interconnect Technology Requirements.

The metrology associated with through-sili-con vias for 3D interconnect was previously discussed in the 2010 review of the ITRS Metrology Roadmap in Future Fab 36.

Emerging Research Materials and Devices

One key new measurement need is for the measurement of contact resistance for nano-structures. Advances in graphene metrology continue to reflect the high interest in the academic and national laboratory communi-ties. The long-range order of CVD graphene is clearly visible in aberration-corrected scan-ning transmission electron microscopy imag-es as shown in Figure 3.[9] Though images of grain boundaries are starting to appear in publications, finding clean grain boundaries during high-resolution imaging is extremely challenging.[10] Theoretically predicted dif-ferences in electron transmission through dif-ferent grain boundary types are being tested using advanced TEM.[11-12]


the efforts of the ITRS Metrology Working Group in making this article possible. A full list of members of the Metrology Working Group can be found here.

References1. D. James, “Intel to Present on 22 nm Tri-

Gate Technology at VLSI Symposium,” Chipworks Real Chips Blog, Solid State Technology, April 12, 2012.

2. E. Levine, private communication.3. C. Wang et al., “Characterization of

Cross-Sectional Profile of Epitaxially Assembled Block Copolymer Domains Using Transmission Small Angle X-Ray Scattering,” Proc. Alternative Lithography Technologies IV, SPIE Advanced Lithography, (2012) 8323-25.

ITRS CHAPTER: Metrology Future Fab Special ITRS Focus

Table 1. Key Lithography (Wafer) Metrology Technology Requirements

Figure 3. Aberration-corrected STEM image of CVD graphene. Figure courtesy Florence Nelson (CNSE) and Juan Carlos Idrobo (ORNL).


4. G.R. Muthinti, A.C. Diebold and B.L. Peterson, “Investigation of E-Beam Patterned Nanostructures Using Mueller Matrix Based Scatterometry,” Proc. Metrology, Inspection and Process Control for Microlithography XXVI, SPIE Advanced Lithography, (2012) 8324-23.

5. A. Vladar, private communication.6. S. Consiglio et al., “Crystallinity of

Electrically Scaled Atomic Layer Deposited HfO2 from a Cyclical Deposition and Annealing Scheme,” J. Electrochem. Soc., Vol. 159, No. 6, (2012), p. G80-G88.

7. T. Sakamoto et al., “Electronic Transport in Ta2O5 Resistive Switch,” Appl. Phys. Lett., Vol. 91, 092110 (2007).

8. W.M. Tong et al., “Radiation Hardness of TiO2 Memristive Junctions,” IEEE Trans. Nuclear Science, Vol. 57, No. 3, (2010), p 1640-1643.

9. F. Nelson et al., “Aberration-Corrected Microscopy of CVD Graphene and Spectroscopic Ellipsometry of Epitaxial Graphene and CVD Graphene for Comparison of the Dielectric Function,” ECS Trans., Vol. 45, No. 4, p. 63-71.

10. P.Y. Huang et al., “Grains and Grain Boundaries in Single-Layer Graphene Atomic Patchwork Quilts,” Nature, Vol. 469, No. 7330, (2011), p. 389-392.

11. O.V. Yazyev and S.G. Louie, “Electronic Transport in Polycrystalline Graphene,” Nature Materials, Vol. 9, No. 10, (2010), p. 806-809.

12. A.W. Tsen, “Tailoring Electrical Transport Across Grain Boundaries in Polycrystalline Graphene,” Science, Vol. 336, No. 6085, (2012), p. 1143-1146.

About the Authors

Alain C. DieboldAlain C. Diebold is an Empire Innovation

Professor of Nanoscale Science at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, as well as the executive director of CNSE’s Center for Nanoscale Metrology. His research focuses on the impact of nanoscale dimensions on the physical prop-erties of materials, and he also continues to work in the area of nanoelectronics metrol-ogy. He is co-chair of the International Metrology Technical Working Group, and chair of the Manufacturing Science and Technology Group of the American Vacuum Society.

Christina A. HackerChristina A. Hacker is a researcher

in the Semiconductor and Dimensional Metrology Division at the National Institute of Standards and Technology (NIST) in Gaithersburg, Md. Her research interests include surface and interface chemistry, including interface modification and sur-face-sensitive analytical techniques, with particular emphasis on chemical, physical and electronic properties of organic mon-olayers for molecular electronics. She has a Ph.D. in analytical chemistry from the University of Wisconsin-Madison. She is a member of the American Chemical Society, the Electrochemical Society, Sigma Xi, and the Society of Women Engineers.

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Yield enhancement is the key to com-petitive semiconductor manufacturing. In the semiconductor industry, the wafer sort yield is given by the portion of ICs produced within the specifications. Yield enhancement (YE) for manufacturing of integrated devices addresses the improve-ment from R&D yield to mature yield in high-volume production, thus covering contamination control, inspection of struc-tures and critical dimensions (CDs), model-based yield prediction and calculation, and defect and yield correlation.

YE therefore deals with three major objectives starting from the collection of defect data via respective data manage-ment through to the definition of defect data excursions. These objectives in par-ticular include inspection tools and strate-gies, automated defect classification, data correlation and identification of excursions, and the resulting definition of specifica-tions. The YE chapter of the International Technology Roadmap for Semiconductors (ITRS) depicts the current and future requirements for high-yielding manufactur-ing of DRAM, MPU and Flash. It also identi-fies showstoppers for manufacturing and discusses potential solutions.

Chapter Scope ChangesAccording to the reorientation of the

scope of the chapter that was introduced by the 2011 roadmap edition, the Yield Enhancement chapter still consists of the two sub-chapters Wafer Environment and Contamination Control (WECC) and Characterization, Inspection and Analysis (CIA). Activities in yield enhancement thus were focused on these two aspects.

The key challenges driving the YE com-munity remain unchanged in principle. However, we have modified the wording in some cases to improve clarity. The most important key challenge on a near-term scale for dimensions above 16 nm is estimat-ed to be the detection of small yield-limiting defects and their identification in contrast to nuisance defects. It is a challenge to detect multiple killer defect types and to differ-entiate them simultaneously at high cap-ture rates, low cost of ownership and high throughput. Furthermore, it is difficult to identify yield-relevant defects within a vast number of nuisance and false defects.

A second-priority challenge still is pro-cess stability vs. absolute contamination level. This includes the correlation to yield test structures, methods and data that are

ITRS CHAPTER: Yield EnhancementLothar Pfitzner, Sabrina AngerFraunhofer Institute for Integrated Systems and Device Technology (IISB)

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needed for correlating defects caused by wafer environment and handling to yield. This requires determination of control limits for gases, chemicals, air, precur-sors, ultrapure water and substrate surface cleanliness.

The challenge of detecting organic con-tamination on surfaces, which was added as a key challenge with lower priority in 2011, persists. It is currently not possible in the fab to detect and speciate nonvolatile organics on surfaces. There is no laborato-ry-scale instrumentation available.

Next-generation inspection is still expect-ed to be the first key challenge in the long term, i.e. for dimensions below 16 nm. As bright-field detection in the far field loses its ability to discriminate defects of interest, it has become necessary to explore alter-native technologies that can meet inspec-tion requirements beyond the 13 nm node. Several techniques should be given consid-eration as potential candidates for inspec-tion: high-speed scanning probe micros-copy, near-field scanning optical micros-

copy, interferometry, scanning capacitance microscopy, and e-beam inspection. This assessment should include each technique’s ultimate resolution, throughput and potential interactions with samples (contamination, or degree of mechanical damage) as key success criteria. In addition, in-line defect characterization and analysis and next-gen-eration lithography remain key challenges in the long term.

Contamination ControlRecently, major attention has been

given to activities in WECC, which con-tinues to provide contamination control limits for media as ultra pure water (UPW), pure gases and air in cleanrooms and clean compartments (Figure 1). Control limits have been reviewed with respect to their known yield impact in critical process steps (as shown in table YE3 in the Yield Enhancement chapter).

WECC activities specifically focused on airborne molecular contamination (AMC) in enclosed wafer environments such as

Figure 1. This GCMS chromatogram represents a typical result of organic contamination control and cleanroom monitoring activities.

ITRS CHAPTER: Yield Enhancement Future Fab Special ITRS Focus

FOUPs. The description and assessment of solutions improving the contamination situation in FOUPs has been fostered, thus resulting in the introduction of new tables: YE4, AMC Monitoring Methods; and YE4a, Supporting Table for Online Methods. In particular, YE4 reveals relevant analytical procedures that are capable of monitoring the adherence of the technology require-ments listed in table YE3. By doing so, a comparison of online vs. offline analytical methods is given, as well as method limita-tions and respective detection limits. The table also now incorporates FOUP environ-ment sampling.

In accordance with the high degree of attention that is drawn at the AMC activi-ties, review for an “AMC definition” is one scope of future work. Activities will also focus on review of “potential solutions” and adjustment of AMC limits. However, because more importance is being placed on the means of producing reticles and new manufacturing technologies, and the respective effects of contamination on those processes, activities also will concen-trate on the introduction of contamination related to extreme ultraviolet (EUV) lithog-raphy and of moisture as a new chemical contamination for the description of the reticle environment. In this context, critical steps for moisture control in FOUP envi-ronments will be identified as well. Further aspects of future work will include the defi-nition and standardization of “organics.” Discussions about adding bare wafer sup-plier requirements will be continued.

There are no changes in the roadmap with respect to ions and metals in UPW, which are still considered critical. Taken as a whole, electrically active particles are considered more critical than electrically inactive particles. However, since online metrology for particles in liquid currently

does not address killer particle size, we are targeting increased knowledge of filtration efficiency for killer particles. A standard for the filter performance validation there-fore will be developed in collaboration with SEMI.

Particle control as a whole is expected to gain even more importance with rela-tion to next-generation lithography (NGL) technologies, which have stricter require-ments concerning particle control, such as with EUV mask cleaning and nanoimprint lithography. Evaluation of respective con-tamination effects and recommendation of limit values is within the scope of the period 2012-2013. We also aim to review the definition of critical organics based on front-end processing (FEP) input. A new and better definition of critical organics is needed to make use of failure mode and effects analysis (FMEA).

Moore ExtensionsIn 2011, CIA defined its scope as fac-

ing the demands of broad applications—such as with More Moore (MM) and More than Moore (MtM) technologies. Also taken into account were power electron-ics, mechatronics and MEMS applications, as well as characterization, inspection and analysis demands and requirements of packaging and assembly. This major change in scope was decided and con-firmed in the meetings of 2010, 2011 and 2012. Accordant tables and potential solu-tions covering this scope will be prepared for the revision in 2013.

In addition, we are still discussing a further extension of the mentioned scope toward a better balance of defect/contam-ination detection and fault diagnostics/control of electrical defects. It is a cur-rent subject for debate, whether referring not only to physical and process defects,





but also to device defects and abnormal electrical characteristics of a device pro-vides some benefit for yield enhancement with respect to continued shrinking of devices and a lack of accordant measure-ment capacity. Acquisitions of electrical characteristics of devices and determina-tion of pass or fail characteristics of chips probably involve advantages in time and in measuring possibility.

Extending the CIA activities in this regard also seems to be a corollary of the advent of MtM and 450 mm technology, and the inclusion of back-end yield in the CIA focus. Including a statistical/systemat-ic approach into yield enhancement activi-ties is one major point of discussion in this respect. Another one is the introduction of tables and requirements concerning yield enhancement on device, chip and system level into the ITRS 2013 edition.

SummaryIn conclusion, improvement of the

Yield Enhancement chapter prospectively focuses on the adjustment of the outline and the content of the chapter in order to correctly reflect the current status and the future requirements, especially with respect to yield enhancement for manufacturing of MM, MtM, larger-diameter substrates and masks. Keeping tables for front-end pro-cessing updated, adding back-end yield enhancement specifications, and consider-ing assembly and packaging yield enhance-ment will be done in practice.


the efforts of the ITRS Yield Enhancement Working Group in making this article pos-sible. A full list of members of the Yield Enhancement Working Group can be found here.

About the Authors

Lothar PfitznerLothar Pfitzner holds an M.S. in mate-

rials science and a Ph.D. in electronics engineering, both from the University of Erlangen-Nuremberg. Since 1985, he has headed the Semiconductor Manufacturing business unit of the Fraunhofer Institute for Integrated Systems and Device Technology (IISB) in Erlangen, Germany. Since 1988, Pfitzner has been a lecturer on semiconductor manufacturing techniques for mechanical and electrical engineering students at the University of Erlangen-Nuremberg, and was appointed professor of microelectronics in 2003.

Sabrina AngerSabrina Anger is a scientist at

Fraunhofer IISB in Erlangen, Germany. Her scientific background includes defect characterization of semiconductors and respective metrology techniques. Anger entered the ITWG Characterization, Inspection and Analysis of the ITRS Yield Enhancement Chapter in 2012. She received her diploma in applied natural science from the Technical University Bergakademie Freiberg in 2004.

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ITRS CHAPTER: Yield Enhancement

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ASSEMBLY, TEST & PACKAGING TECHNOLOGIES

Consumers are leading the integration of electronics into the fabric of our society. Smartphones and tablets have superseded PCs and laptops as the predominant mar-ket drivers for the electronics industry. Social media, cloud computing, Internet commerce, and communications are all fueling significant growth of the network-ing and data center infrastructures, which are overtaking traditional server products.

Moore’s Law scaling continue to move forward, with foundries announcing 14 nm finFET capabilities by 2014, while MEMS and sensors are becoming mainstream devices. Silicon interposers with through-silicon via (TSV) technology are gathering momen-tum for 3D and heterogeneous integration, undoubtedly advancing the technology for the promise of More than Moore.

Although Electronic Packaging and Test is referred to as the “back end” of the semiconductor industry, it is the front end of the electronic product industry. Today, in the electronic landscape, it stands at the front line of the congruence of disrup-tive market pull and technology innova-tion push. The two articles in this section summarize the state-of-the-art technology, and addresses related major challenges and potential solutions. These articles are timely and crucially important for everyone in the electronics community, but a “must

William T. ChenSenior Technical Advisor, ASE (U.S.) Inc.

read” for engineers and scientists in the packaging and test arena.

The first article, “Assembly and Packaging,” describes major challenges for the industry and the fundamental shift of packaging technology as the enabler, as well as the gate to meet those challenges. The article covers major innovations in single-chip packaging, wafer-level packag-ing, system in package (SiP) and 3D inte-gration. The article concludes by outlining the activities of the Assembly & Packaging TWG in 2012, and near- and long-term challenges.

The second article, “Test and Test Equipment,” emphasizes design for test (DFT) as the major solution to contain test costs, given the ever-increasing transis-tor count within IC devices. There are two major sections: logic DFT and non-logic MPU and SoC DFT. The article concludes with a description of the 2012 Test TWG update and outlook for 2013.

These two articles will surely whet the appetite for readers to expand their knowl-edge by referring to the more compre-hensive articles that can be found on the ITRS 2012 website. As these two articles go to press, the two working groups will be reporting their 2012 work products and 2013 plans at the 2012 ITRS conference in Hsinchu, Taiwan.

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“More than Moore” is driving devel-opments in the back end, with some unique dynamics in play. The objective, of course, is to enable increased density of packaged chips by focusing on 3D integration. While decreases in device dimensions continue, advanced 3D pack-aging techniques, such as through-sili-con vias, eWLB, Cu Pillar bumping and WLCSP, appear likely to provide dra-matic improvements in functionality and performance in the foreseeable future.

As dimensions in advanced pack-ages shrink, the back end is begin-ning to adopt many of the same tools and processes used in the front end. Manufacturing equipment, including lithography, etch and deposition tools, is being reconfigured to meet back-end application requirements.

Rudolph is working closely with its customers to develop and enhance a wide range of process control solutions required for advanced packaging. A number of fabs are currently investigat-ing new uses for metrology systems in

back-end applications. Ultimately, they want to implement the same kinds of sophisticated process control capabili-ties that have proven to be so valuable in the front end. And we are encounter-ing entirely new packaging processes that require innovative solutions and novel sensors to perform both inspec-tion and basic metrology.

Industry experts forecast vigorous growth for advanced packaging in the years ahead. This is an exciting time to be a “back-end player”!

Image source: Qualcomm, Semicon West 2010

Advanced Packaging Is a Vibrant and Exciting Market

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ASSEMBLY & PACKAGING


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The electronics industry is driven by consumer demands for new products that now impact essentially every phase of our lives. Electronics is penetrating new markets in medical care, entertainment, transportation, communication, agriculture, energy and environmental areas. Each area has unique requirements for reliability, operating environment, etc., requiring inno-vative, specialized packaging technologies. The ongoing requirements for smaller size, higher performance, expanded function-ality, lower power and lower cost have been successfully addressed at the elec-tronic component level. Design improve-ments, shrinking geometries and innovative manufacturing methods have allowed the advantages of Moore’s Law scaling to be maintained even as we approach the limits imposed by the physics of the devices.

Today, however, the performance and power required for ICs is no longer scal-ing at the same rate as we scale feature size. New materials and new device types will be necessary to address this shortfall. Changes in assembly and packaging tech-nology have helped take up the slack with

new package types and improved func-tional density enabled by new packaging materials and processes. The packaging community has responded with wafer-level packaging; new generations of flip-chip chip-scale packages (CSPs); various forms of system-in-package (SiP), including 3D stacked die and stacked packages; fine-pitch surface-mount, silicon and glass interposers (2.5D); and 3D IC.

SiP architecture is the enabling tech-nology for More than Moore equivalent scaling through functional diversifica-tion. This allows many different types of electronic, optical and electro-mechanical components to be integrated into a sin-gle package. New package architectures such as package-on-package (PoP) and package-in-package (PiP), already in vol-ume production, are examples of early SiP technology.

Despite these innovations, packaging has not scaled at the same pace as ICs. As a result, packaging is currently a gating issue in the drive for expanded functionali-ty at higher performance that is lower cost and in a smaller package.

ITRS CHAPTER: Assembly & Packaging W.R. BottomsThird Millennium Test Solutions

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The major challenges for the electron-ics industry are the result of more capable, data-hungry consumer products and the movement to the “cloud” for data stor-age and data processing. This gives rise to demands for higher bandwidth, lower latency and lower power.

The need for lower power has tradition-ally been driven by the demand for longer battery life for portable consumer prod-ucts. Today, the power required for data centers, data communication and cloud computing is just as critical. The landscape for data processing and data communica-tion has changed dramatically in recent years as the move to deliver all data eve-

rywhere all the time is driving explosive growth in the requirement for communi-cations bandwidth. That pace of change is not slowing with cumulative average annual growth rate (CAAGR) forecast to continue at greater than 100% at least through 2015.

The most critical challenges for the electronics industry now include:• Meeting the demand for rapidly increas-

ing bandwidth at every point in the data communications infrastructure (includ-ing physical density of bandwidth to IC packages in our portable devices).

• Decreasing the power per unit function in data centers and in the communica-

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ITRS CHAPTER: Assembly & Packaging Advancing Tomorrow’s Technology | www.rudolphtech.com

tions infrastructure by more than two orders of magnitude in the next 10 years.

The solution to these critical challenges requires a change in the way we approach packaging. Although we will continue to make important progress on cost and per-formance for single-chip packaging, the fundamental progress we need requires an integration of design and simulation for chip, package, PCB and final product. The short product lifecycles and high cost of prototype production make it impracti-cal to build, test and revise prototypes in product development. We must move the “experiments” and “optimization” from the lab to the computer through modeling and simulation. The design and simulation tools are not yet adequate, and improvements are needed to meet this goal, as illustrated in Figure 1.

Single-Chip PackagingThe dramatic rise of the mobile mar-

ket with smartphones, tablets, portable personal devices and portable entertain-ment systems has brought an expanded set of technology challenges in form fac-tor (height and size), weight, functional diversification such as RF and video, sys-tem integration, reliability, time to market, and cost. Changes in single-chip package design, materials and manufacturing pro-cesses have been implemented to address these challenges. New package processing techniques such as wafer-level packaging (WLP) increase parallelism, driving down cost, size and power requirement.

In addition, there have been major changes in materials, such as conver-sion from gold to copper for wire bonds. Copper wire bonds will be used in a major-ity of packages by early next year, and

this is driving change for a majority of the materials set and significant changes in the manufacturing equipment infrastructure. New underfill materials with improved ther-mal and mechanical properties and new die attach materials are being adopted.

There is also a wide range of changes in materials to reduce the package pro-cessing temperature—a requirement for some new device types and new pack-age architectures. The drive to reduce height has resulted in everything getting thinner, from the die itself to all layers in the packaging process. This calls for insulating materials with lower dielectric constant to keep the interconnect capac-itance low, thereby avoiding increases in power consumption.

The packaging of new device types ranging from compound semiconductors for both power and photonic applications to MEMS used for a wide variety of sensors and other devices in both single-chip and multi-chip packages brings new challenges. The mechanical and thermal properties of compound semiconductors such as SiC and GaN are significantly different from silicon. They support higher-temperature opera-tion, but are less tolerant of mechanical stresses. Each of these device types pre-sents unique packaging challenges:• Optoelectronic devices must permit

photons to enter and leave the package while still protecting the package from the environment.

• MEMS sensors and transducers such as microphones and speakers must allow access to the atmosphere, yet protect the package contents from light, water vapor and particulate contamination.

• MEMS devices such as pressure sensors and flow controllers may require liquid to enter the package at high pressure while protecting the electronic compo-

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nents from exposure to the liquid and stress that may be caused by the high pressures.

Many of these new device types will have hot spots and/or performance dependent on temperature stability. This may require heating as well as cooling inside the package, particularly for stabi-lizing CMOS and certain photonic appli-cations. Driven by the continuation of Moore’s Law scaling, difficult challenges still exist for single-chip packages. The introduction of new device types and the ever-present pressure to reduce size, cost and power consumption while increasing

performance requires constant innovation. These challenges include requirements for use of single-chip packages as compo-nents in multi-chip package architectures such as PoP and PiP.

Wafer-Level PackagingWafer-level packaging (WLP), led

by the wafer-level chip-size package (WLCSP), has been one of the most rap-idly growing package types for several years. It enables the smallest size, higher performance and low cost for low- to medium-pin-count packages.

Today, WLP technology is expanding to larger-pin-count packages through the use


Direct connection

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Horizontal

BGA package Flip-chip module

Wire bondingdie stacked

Package on package

Through-silicon via

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Figure 2. Categories of System-in-Package Structures

of reconstituted wafers, enabling fan-out wafer-level packaging. The reconstituted wafer has die spaced in a polymer matrix such that there is a perimeter of polymer surrounding each die. This is used during the redistribution layer (RDL) process to “fan out” to an area larger than the origi-nal die, thereby enabling a larger number of pins in the package. Many other addi-tions to WLP technology are underway to expand the applications that can be addressed:• Wafer-level substrates with passives in

silicon or passives in the RDL - Integrating passive structures into the

RDL by thin-film dielectric deposition

- Embedded active and passive devices• Wafer-level assembly—die to wafer—of

Si (memory, MPU), MEMS, III/V (InP, GaAs, GaN, etc.) and SiGe devices at wafer level

• Integrated shielding (RF and power)• Functional layer integration (actuators,

sensors, antennas)• Through-silicon-via (TSV) formation

and metallization, wafer thinning and adjusted bonding technologies for stacked die on wafer and wafer-to-wafer stacks

• Optical chip-to-chip interconnects• TSVs on WLP to allow double-sided

connectivity, including PoP applications

1

Board-level system design

SiP Lightens a Burden on Designing a System Board

SiP-level system design

SiP on a 4-layer boardIndividually packaged

devices on a 6-layer board

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Figure 3. SiP benefits in comparison with traditional packaging




• Higher-complexity applications such as SiP, 3D configurations and passive device integration. This includes face-down and face-up approaches on active Si devices, carriers with passives, etc.

WLP developments are motivated by the recognition that parallel processing on the wafer opens lower-cost, high-per-formance alternatives to traditional pack-aging. WLP includes not only processing on active devices, but also processing of silicon die with integrated passives, other substrates such as glass, and reconstituted polymer wafers with embedded die. There are many challenges to be overcome in WLP for this vision of expanded applica-tions to be realized. They include materials and processes with reduced temperature, interlayer adhesion and stress, test strat-egy for stacked WLP applications, reduced metal roughness for RF applications, thick metals for high current, etc.

System in PackageSiP technology is rapidly evolving from

a specialty technology used in a narrow set of applications to a high-volume technol-ogy with wide-ranging impact on electron-ics markets. The broadest adoption of SiP to date has been for stacked memory/logic devices and small modules used to inte-grate mixed-signal devices and passives for smartphone applications. Numerous con-cepts for 2D and 3D SiP packaging are now emerging, driven largely by the demands of portable consumer products. Categories of SiP structures are illustrated in Figure 2. The unique issues associated with 3D SiP are in the 3D section.

SiP offers the benefits of smaller footprint with fewer connecting traces between devices, which result in reduced PCB layer count and thereby lower cost.

Additionally, shorter signal paths in SiP reduce electromagnetic emission and crosstalk. These features enable cost reduction and performance improvement as illustrated in a system composed of a microprocessor and DDR memories in Figure 3.

The board-level system design incor-porated traditional single-chip packages assembled on a PCB, while the SiP-level system design was embedded in the SiP. The SiP system design reduced footprint by 80%, electromagnetic emission by 20 dB/μV and the number of PCB layers from six to four.

The benefits offered by SiP-level system design include lower total cost, reduced power and higher performance in addition to the higher signal quality associ-ated with reduced noise and electromag-netic emission. These SiP-based optimum system solutions typically can be achieved only by close collaboration among semi-conductor, package and system suppliers.

SiPs must deal with all the challenges of single-chip packages in addition to new challenges:• Differential thermal expansion associ-

ated with heterogeneous integration• Hot spots• Integration of MEMS, RF, photonics,

power and CMOS components into a single package

• Isolation of components within the package to limit crosstalk and other noise sources

• Power integrity for multiple voltages in the package

3D IntegrationThe packaging industry has been

focused on maximizing performance while minimizing size and cost in a 2D world for most of its history. The obvious extension


to the third dimension has been discussed and forecast for several years, with little success in moving to volume production. There are now 3D packaged products using TSVs shipping in volume for cell-phone cameras, for example, but high-volume production for complex 3D-SiP architectures are still only “demonstration” products. The potential benefits include higher performance, reduced power requirements, smaller size and eventually lower cost than conventional 2D packag-ing. Examples of 3D-SiP integration are illustrated in Figure 4.

Advanced packages incorporating interposers, introduced by Xilinx, are now in volume production using 2.5D integra-tion. The benefits of higher bandwidth, lower power and reduced latency of the interposer architecture are significant, and several other products are in development using this technology. These 2.5D products

incorporate almost all of the processes and materials required for full 3D-SiP inte-gration, where the full benefits of 3D are even more compelling. With 2.5D products already underway, several companies have announced plans for 3D-TSV shipments in 2013. The first devices will be Si-on-Si and involve low power with a limited number of layers in the stack due to thermal man-agement concerns, among other issues.

There remain many difficult challenges for complex 3D-SiP packaging, including heterogeneous integration, thermal man-agement, test access, alignment accuracy in stacking, handling of very thin wafers and die, and power integrity in the stack. Although these issues are important, per-haps the greatest impediment to imple-mentation of high-volume 3D integration has been coming down the learning curve for 3D integration processes to realize the promise of lower cost. The interposer tech-

Figure 4. Examples of 3D SiP products




nology is providing a lower-risk opportunity to run these processes at high volume and come down the learning curve.

Assembly and Packaging Activity for 2012

In addition to revising our tables for 2012, the Assembly and Packaging TWG

has been preparing for the major revision coming in 2013. We have held multiple workshops addressing photonics pack-aging, workshops with the ERM TWG on requirements for new packaging materi-als, and one workshop on MEMS packag-ing requirements with another planned for early in 2013. We have also started the


Difficult challenges 16 nm Summary of issues

Margin in packaging is inadequate to support investment required to reduce cost

Wafer-level packaging and 3D equipment cost is not scaling with product cost

Increased device complexity requires higher-cost packaging solutions

Electromigration at high current density for interconnect (die, package)

Thermal dissipation

Improved current density capabilities

Higher operating temperature

Substrate wiring density to support >20 lines/mm

Lower-loss dielectrics

"Hot spot" thermal management

Package substrates with lines and spaces below 10 m

Partitioning of system designs and manufacturing across numerous companies will make required

optimization for performance, reliability and cost of complex systems very difficult

Complex standards for information types and management of information quality along with a structure for

moving this information will be required

Organic device packaging requirements not yet defined (will chips grow their own packages)

Biological interfaces will require new interface types

Power supply quality

Power delivery in stacked die

Reducing power supply voltage with high device switching currents

Power integrity

Small die with high pad count and/or

high power density

High-frequency die

System-level design capability to

integrate chips, passives, substrates

and 3D structures

Emerging device types (organic,

nanostructures, biological) that require

new packaging technologies

Package cost does not follow the die

cost reduction curve

Table 2. Difficult Challenges for Geometries 16 nm

Difficult challenges 16 nm Summary of issues

Mixed-signal co-design and simulation environment

Rapid turnaround modeling and simulation

Integrated analysis tools for transient thermal analysis and integrated thermal mechanical analysis

Electrical (power disturbs, EMI, signal and power integrity associated with higher frequency/current and lower-

voltage switching)

System-level co-design needed now

EDA for "native" area array required to meet the roadmap projections

Models for reliability prediction

CTE mismatch and warpage for large interposers

Defect density at very thin interfaces

Low-cost embedded passives: R, L, C

Embedded active devices

Quality levels required not attainable on chip

Electrical and optical interface integration

Wafer-level embedded components

Handling technologies for thinned die and wafers (particularly for bumped wafers)

Impact of different carrier materials (organics, silicon, ceramics, glass, laminate core)

Establish new process flows

Reliability

Testability

Coordinated design tools and

simulators to address chip, package

and substrate co-design

Interposer and embedded components

Thinned die packaging

Table 1. Difficult Challenges for Geometries 16 nm

process of adding traditional roadmap tables for availability of new materials and power devices based on compound semi-conductor materials.

Difficult ChallengesThere are many difficult challenges

associated with continued cost reduction, size reduction, improved performance and improved power efficiency for all types of packages. In addition, the number of device types is expanding with heterogeneous integration, photonics, photovoltaics and MEMS devices. New package architectures such as advanced wafer-level packaging, complex SiP and 3D TSV-based SiP integra-tion are emerging to address market needs.

These challenges have spawned an increasing number of consortia, where the cost of research is shared. The result has been an acceleration of progress in an environment where individual partici-pants in the industry have fewer resources allocated to research. The annual list of difficult challenges for assembly and pack-aging provides some focus to cooperative efforts to meet these challenges before they become roadblocks to continued progress. This list for 2012 is presented in Tables 1 and 2.

SummaryThe cost of packaging is increasing as

the package assumes more of the cost of system integration that has traditionally been the function of the PCB. New pack-aging solutions such as complex SiP and 3D-TSV integration enable more of the system integration to move to the pack-age to improve performance, decrease size and power requirement, and lower total product cost. These changes present many difficult challenges, requiring new design tools, new materials, new equip-

ment, and closer collaboration between device, package and product designers.

Acknowledgments The author would like to acknowl-

edge the efforts of the ITRS Assembly & Packaging Working Group in making this article possible. A full list of members of the Assembly & Packaging Working Group can be found here.

About the Author

W.R. BottomsW.R. Bottoms, chairman of the board

of Third Millennium Test Solutions, received a Ph.D. in solid-state physics from Tulane in 1969. He currently serves as chair of the Assembly & Packaging Technical Working Group for the ITRS and as chair of the Packaging and Package Substrates Technical Working Group for the International Electronics Manufacturing Initiative (iNEMI).

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Based in Tokyo with subsidiar-ies around the globe, Advantest Corp. (NYSE: ATE, TSE: 6857) is the world’s foremost manufacturer of automatic test equipment (ATE) for the semiconduc-tor industry, and a leading manufacturer of measuring instruments used in the design, production and maintenance of electronic systems, including fiber-optic and wireless communications equipment and digital consumer products. Advantest is the largest global producer of ATE for memory semiconductors and also the leading supplier of test systems to the fast-growing SoC segment. The company proudly serves the IDM, fabless and OSAT markets, and has products integrated into the most advanced fabrication lines in the world.

Active in the front end of semiconduc-tor manufacturing as well, Advantest’s cut-ting-edge Multi-vision Metrology Scanning Electron Microscope (MVM-SEM) technol-ogy is helping to define the EUV roadmap and extend 193i lithography. The new E3630 3D Metrology & Imaging SEM tool is an advanced mask metrology system that enables photomask manufacturers to measure the critical dimension (CD) of the nano or fine-geometry patterns on a pho-tomask, and offers enhanced measurement

techniques for 3D side wall angles (SWA), height and other topographical features.

For 24 consecutive years, Advantest has been ranked among VLSI Research’s 10 best semiconductor equipment com-panies, and was named the best ATE company in 2012. The ranking is based on customer satisfaction in terms of technical leadership, product performance, process and software support, and service. In SoC test, Advantest achieved the industry’s highest rating in cost of ownership; and in memory test, the company led the industry with the highest rating in the categories of uptime and usable throughput.

In April 2012, Advantest announced the successful integration of Verigy Inc. into its corporate structure. Acquired in 2011, Verigy’s origins in the test and measure-ment division of Hewlett-Packard endowed it with a rich stock of cutting-edge solu-tions for semiconductor design verification and evaluation. By merging Verigy into its operations, the Advantest Group enhanced its R&D capabilities and boosted its pres-ence in the non-memory market to domi-nate in select areas of test. The companies’ complementary strengths in products, cus-tomer base, R&D, sales and service have increased their competitiveness in the global market.

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TEST & TEST EQUIPMENT


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Controlling the test cost of evolving and increasingly complex ICs and devices is a key focus of the ITRS Test chapter. Test equipment is expensive, but the cost of a transistor continues to decline accord-ing to Moore’s Law. Therefore, it makes sense to make use of ever lower-cost transistors in place of costly test tools whenever possible. This smart partition-ing approach has driven the evolution of design for test (DFT), and has resulted in controlled test cost over time. DFT is a key element in the ITRS test roadmap.

Transistor GrowthThe number of transistors will continue

to grow exponentially throughout the road-map period. In 2012, microprocessor (MPU) transistors per die are approximately 8 bil-lion and will rise to a little over 100 billion by 2025. System-on-a-chip (SoC) transis-tors begin at approximately 1 billion per die in 2012 and rise to roughly 10.1 billion in the same time period. Figure 1 shows the 2012 forecast for transistor growth.

Table 1 shows a 2015 MPU and con-sumer SoC device composition snapshot.

For both MPU and SoC, more than 80% of all transistors are used for memory while only 13% of transistors are in cores. Random logic makes up the remaining transistor percentage. Although the percentage of core transistors is nearly the same for MPU and SoC, it can be seen from the table that SoC devices have a much larger number of total cores compared with MPU devices. MPU cores are generally largely homogene-ous, with only a few unique core types that are specialized to integer, floating point or graphic processing. The SoC devices may have many heterogeneous cores of various sizes and a much larger number of unique IP block types that could include cores sim-ilar to MPU devices, but might also include

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2015 Forecast MPU SoC

Total cores 14 224

Unique cores 4 23

% Memory transistors 82% 86%

% Random logic transistors 5% 0.3%

% Core transistors 13% 13%

Table 1. MPU and SoC Transistor Mix

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capabilities for digital signal processing, analog-to-digital conversion, encryption and decryption, etc.

Logic DFTEven though roughly 80% of transistors

on MPU and SoC devices are memory, it is the testing of the 13–18% logic transistors that will generally drive the overall test cost. The test architecture designed into the MPU or SoC will determine the overall data volume required. The larger the data volume, the larger the test time and cost.

Functional and structural test are two test methodologies employed to validate the operation of a digital circuit; however, it is common to use a combination of both functional and structural test.

Functional test attempts to validate the operation of a device by employing a large set of stimulus and response data

that simulate the operation of the device. Functional data volume grows expo-nentially with increased transistor count because of an increase in the number of functions built into the chip. Structural test attempts to validate the internal integrity of functional blocks in a device, but not the operation. Structural scan test data volume grows only as a multiplier of the number of transistors and has the advan-tage that it can be automatically built in the circuit design via EDA tools.

Since scan data volume increases along with transistor count, technique improvements are needed in scan to pre-vent the data volume from growing overly large along with the 15x growth in transis-tors over the 2012–2025 period. Scan test without enhancement techniques is repre-sented in the logic roadmap as a flat test methodology.

Figure 1. ITRS Logic Transistor Growth

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A hierarchal or divide-and-conquer approach to structural test breaks the overall circuit design into blocks that can be individually designed for testing. Hierarchal partitioning will reduce the overall length of scan chains; and though it will increase the quantity of scan pat-terns, the resulting overall data volume will be somewhat less than the volume using flat test architecture. For large tran-sistor counts, a hierarchal approach to testing also makes the test insertion pro-cess easier for the design tools. There are also advantages to debugging a device with a hierarchal test design because it is generally easier to localize a defect.

Another technique that can be used to reduce the data volume is to add data decompression and compression engines to the design. Stimulus test data is sent to the device under test (DUT) for

decompression, and the resultant data is compressed on the DUT before being output and compared or captured by the tester. Overall data volume onto and off of the DUT is reduced because of com-pression. A downside of compression is that it could be more difficult to localize a test failure because of the compressed response. Tools and techniques are avail-able to assist the test engineer in localiz-ing the defect.

A test design approach that makes use of both hierarchal test portioning and scan data compression will result in the greatest effective reduction of test data volume.

Figures 2 and 3 show the data volume improvement that can be achieved by using hierarchal test design, scan com-pression and hierarchal plus scan compres-sion. Note that hierarchal test design in

Figure 2. MPU Compression Factors

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MPU devices results in only a very small compression factor of 1.3x. This is largely because of the large homogeneous cores and few unique core types.

SoC devices with their large number of varied cores can achieve a 2–5x effec-tive data volume compression using only hierarchal test design. The greatest com-pression, however, is achieved when using scan data compression along with a hier-archal segmentation of test insertion. MPU devices can achieve a data volume reduc-tion factor of 100–1,000, and SoC devices can theoretically achieve a compression level up to 100,000. Compression fac-tors of 100 are typical using current tools and methodologies. Compression factors of greater than 1,000 have been demon-strated, but are not commonplace today.

Non-logic MPU and SoC DFTDFT techniques can be applied to most

types of devices. As previously discussed, memory uses more than 80% of the transis-tors on logic and SoC devices. The memory is generally not in a single array, but is used as registers, small arrays and large arrays of varying memory types distributed through-out the design as part of functional blocks.

Memory is usually tested using on-chip built-in self-test (BIST) and might use built-in self-repair (BISR). The overall test time and incurred cost consumed by BIST can be much less than what would be required by direct access test (DAT) and the use of an external memory tester. ROM can easily have a test engine designed that creates a checksum of all data in the ROM and compares the data to an encoded

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Figure 3. SoC Compression

checksum. If the checksum values match, the ROM is defect-free.

DRAM and SRAM are volatile devices and cannot use the checksum technique, so they are usually evaluated by incor-porating a test engine that writes and reads the memory. The test engine can be designed for simple test sequences or could be a complex design that can effec-tively test memory cells under worst-case operating and disturb conditions, and also have the ability to repair a defect by implementing a redundant memory ele-ment in place of a defective element.

Analog DFT is not as advanced as digi-tal DFT, and can vary from simple feed-back structures to on-die data capture and analysis. Though most digital ICs use wide-spread standardized techniques, analog DFT is usually a custom implementation.

MEMS devices are mechanical struc-tures that require unique test apparatuses to simulate movement, magnetic fields, pressure or chemical presence. MEMS devices not only need to be validated as structurally and functionally good, but might require calibration. Because some MEMS devices are integrated with digi-tal or analog circuits on a common sub-strate, the benefits of circuit DFT can be employed in DFT for MEMS. Techniques such as using the earth’s gravity or mag-netic field strength have been employed to validate and calibrate MEMS structures.

Changes in the 2012 Test Roadmap Update

The ITRS test roadmap has been updat-ed for 2012. There were no major changes to the 2012 roadmap test tables, but there were a number of added parameters and table adjustments.

DRAM non-performance wafer test parallelism has been adjusted to full wafer

out in time. DRAM at-speed performance testing has been added to the probe card table for 2012; however, performance test-ing is limited to 32 die in parallel in 2012 and rising to 64 die in parallel out in time.

Probing force and at-performance wafer probing parameters for MPU, NAND and LCD have also been added to the probing table for 2012.

The DFT table has been adjusted to reflect the latest learning, delaying some improvements into later years of the road-map. Memory DFT had been mistakenly dropped from the memory table in 2010 and has been added back in.

The logic table was completely redone in 2011 and refined for 2012. Most of the logic table is now model-based, and numerous adjustments have been made as a result of minor changes to the number of gates in the largest core, the average core size and the number of cores.

An increase in the number of radio ports is reflected in the RF table to align with the reality that wireless communica-tion is replacing wired connections.

Looking to 2013

Because 3D devices have become a major driver to the test roadmap, 3D test issues and potential solutions will be added to the 2013 edition. Image sensors will have increased coverage starting in 2013.

AcknowledgementsThe author would like to acknowledge

the efforts of the ITRS Test Working Group in making this article possible. A full list of members of the Test Working Group can be found here. The Test chapter also represents significant contributions from a large number of participants representing a wide cross-section of the industry. It is




aligned with the chapters from the Design, Interconnect, Assembly and Packaging, and RF/AMS Technology Working Groups (TWGs).

About the Author

Roger Barth Roger Barth is a senior member of the

technical staff with Micron Technology, and is the chair of the ITRS Test Working Group. He has more than 35 years of semiconductor experience. His back-ground includes memory process devel-opment, product and test development, and industry analysis. He holds B.S. and M.S. degrees in electrical engineering from the University of Illinois Urbana-Champaign.

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RELATED CHAPTERS

Environment, Safety, & Health • Front End Processes• Lithography• Interconnect• Assembly & Packaging• Factory Integration

RF and A/MS Technologies• Design & System Drivers

Emerging Research Devices • Emerging Research

Materials

Emerging Research Materials • Emerging Research Devices

MEMS • RF and A/MS Technologies• Assembly & Packaging• Test & Test Equipment• Interconnect• Emerging Research

Materials

Modeling & Simulation • Design & System Drivers• Process Integration,

Devices, & Structures• Yield Enhancement• Lithography• Front End Processes• Interconnect

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Devices, & Structures• Front End Processes• Lithography• RF and A/MS Technologies• Test & Test Equipment• Yield Enhancement

Process Integration, Devices, & Structures • Design & System Drivers• Front End Processes• Lithography• Factory Integration

Factory Integration • Process Integration,

Devices, & Structures• Environment, Safety,

& Health• Metrology• Modeling & Simulation• Yield Enhancement• Front End Processes

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Front End Processes • Design & System Drivers• Process Integration,

Devices, & Structures• Lithography• Interconnect

• Metrology• Yield Enhancement

Interconnect• Design & System Drivers• Front End Processes• Yield Enhancement• Metrology• Assembly & Packaging

Yield Enhancement • Design & System Drivers• Modeling & Simulation• Metrology• Test & Test Equipment• Lithography• Front End Processes• Interconnect• Factory Integration

Metrology • Yield Enhancement• Test & Test Equipment• Lithography• Front End Processes• Interconnect

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Assembly & Packaging • Design & System Drivers• Yield Enhancement• Interconnect• Test & Test Equipment• Process Integration,

Devices, & Structures• Environment, Safety,

& Health

Many of the Chapters within the ITRS overlap considerably. In order to aid you in finding which Chapters overlap, below you’ll find an index of the ITRS articles in this issue with links to suggested further reading.

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Advantest www.advantest.com 116

Brewer Science www.brewerscience.com 28

Hitachi www.hitachi-hta.com/semiconductor 80

Nikon www.nikonprecision.com 4 74

Rudolph www.rudolphtech.com 106

TEL www.telcertifiedused.com 88

Total Facility Solutions www.tfs-us.com 63

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