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TiVo Proprietary and Confidential - Do Not Distribute!
Design Verification Tests—Hardware Consumer DesignP/N DDOC-00000-000, Rev. A1
Fusion USB DVT ReportApril 2008
TiVo Proprietary and Confidential - Do Not Distribute!
Document Revision History 1
1. Update the revision number on the cover page.
REV No. Revision date Revised by Changes include
A1 4/22/2008 Ealasaid A. Haas Original document
TiVo Proprietary and Confidential - Do Not Distribute! 1
April 2008
Contents
1.0 Overview
2.0 Specifications Diagram
3.0 Drop/Droop Test3.1 Fusion Drop/Droop Test Results
4.0 Droop Test4.1 Bus-Powered Droop Test Results in Tek format
5.0 Inrush Test5.1 Inrush Test Results in Tek format
6.0 Full Speed Signal Quality Test6.1 Signal Quality Test Results in Tek format
7.0 High Speed Signal Quality Test7.1 Signal Quality Test Results in Tek format
8.0 Low Speed Signal Quality Test8.1 Signal Quality Test Results in Tek format
9.0 High Speed Chirp Test9.1 High Speed Chirp-Test Results in Tek format
TiVo Proprietary and Confidential - Do Not Distribute!
Design Verification Tests—Hardware Consumer Design
1.0 OverviewThe contents of this binder are authorized for EXTERNAL use.
This report contains the DVT test results and relevant specifications for the USB components of the Fusion DVR.
The tests were conducted on the TiVo premises.
TiVo Model Number: TCD652160
Project: Fusion
TiVo Proprietary and Confidential - Do Not Distribute!
Design Verification Tests—Hardware Consumer Design
2.0 Specifications DiagramThis section contains the Fusion Ethernet, USB; Base SATA Connector Specifications Diagram
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DIFF_ENET_RX_N
DIFF_ENET_RX_P
DIFF_ENET_TX_N
DIFF_ENET_TX_P
USB0_VCC
USB0_GND
USB1_VCC
DIFF_USB1D_PUSB1_GND
ACTLED
LNKLED LED_LNK
EPHY_VCT
USB0_PWRON_N
USB1_PWRFLT_N
DIFF_USB1D_PDIFF_USB1D_NUSB1_PWRON_N
USB2_PWRON_N
DIFF_USB0D_PDIFF_USB0D_N
DIFF_ENET_TX_N
USB0_PWRFLT_N
USB2_PWRFLT_N
DIFF_USB2D_NDIFF_USB2D_P
DIFF_ENET_TX_P
DIFF_ENET_RX_NDIFF_ENET_RX_P
DIFF_SATA_TX1_PDIFF_SATA_TX1_NDIFF_SATA_RX1_PDIFF_SATA_RX1_N
EPHY_VCT
USB1_PWRFLT_N
USB0_PWRFLT_N
USB2_PWRFLT_N
USB1_GND
USB0_VCC
USB0_GND
USB1_PWRON_N
USB0_PWRON_N
USB2_PWRON_N
SATA_TXDP1
SATA_TXDN1
SATA_RXDN1
LED_ACT
DIFF_SATA_RX1_P SATA_RXDP1
DIFF_SATA_RX1_N
DIFF_SATA_TX1_N
DIFF_SATA_TX1_P
USB1_VCC
DIFF_USB0D_NDIFF_USB0D_P
DIFF_USB1D_N
V3V
V2_5V
V3V
V5V
V3V
DIFF_USB2D_N 24
SATA_TXDN1 39
SATA_TXDP1 39
SATA_RXDP1 39
SATA_RXDN1 39
DIFF_USB2D_P 24
GP_ENET_ACTIVITY12
GP_ENET_LINK12
Document Rev Sheet of
Fusion
Tivo Inc. Confidential and Proprietary. All Rights Reserved
BSCH-00048-000 F1
Ethernet, USB; Base SATA Conntector
16 56Thursday, June 28, 2007
Document Rev Sheet of
Fusion
Tivo Inc. Confidential and Proprietary. All Rights Reserved
BSCH-00048-000 F1
Ethernet, USB; Base SATA Conntector
16 56Thursday, June 28, 2007
Document Rev Sheet of
Fusion
Tivo Inc. Confidential and Proprietary. All Rights Reserved
BSCH-00048-000 F1
Ethernet, USB; Base SATA Conntector
16 56Thursday, June 28, 2007
A1.1REMOVE Y2601
Stitch GND aroundXTAL and caps insideGND layer cutout
Place 49.9 termination resistors close to BCM740X
Route TXP/M and RXP/M pairs differentially, matched short lengths, with 100 ohm differential impedance, adjacent to ground plane.
SATA & USB - Layout Guidelines & Notes
1. The Dp and Dn traces are length matched, with max differential skew, within 20mils2. Differential trace length must be less than 5 inches3. No more than 2 vias per trace, prefer zero.4. Never split the ground plane under differential pair routing5. Route differential pairs above the GND plane.6. Differential impedance is 100 Ohms for SATA and 90 ohms for USB.7. Adjacent differential pairs should be separated by at least 3 times the trace width.(e.g. 7.5 mil trace, leave >22.5mils between adjacent diff pairs)8. Stich gnd vias around each differential pair, but NOT between a given pair.9. SATA xtal +/- 50 ppm Tolerance +/- 100 ppm Stability
USB VCC and GND lines have high current(500mA). Make these traces 25 mil min.
Bottom
Dual USB Power Controller
Top
10/100 Ethernet I/O2.0 USB Port 2 I/O2.0 USB Port 1 I/O
Internal Sata, Baseline(Remove when SATA Multiplier Installed)
100 Ohm
100 Ohm
100 Ohm Differential
90 Ohm
90 Ohm
90 Ohm Differential
90 Ohm
90 Ohm
100 Ohm Differential
100 Ohm
100 Ohm
100 Ohm
100 Ohm
100 Ohm
100 Ohm Differential
Front Panel
Rear Panel, Top
Rear Panel, Bottom
Ethernet, USB, SATA Controllers
P1.05 25Dec2006- Add Transient Suppressor, D42 to Ethernet and D41 to USB differential data pairsP1.06 30Dec2006- Delete Transient Suppressors, D42 to Ethernet and D41 to USB differential data pairs- Change C2611 and C2618 From CCAP-00006-100 to CCAP-00006-200 to combine line item with tuner use- Change C463 from CCAP-00012-000 to CCAP-00012-200 to elminate single instance of 0805 package.- Change C2609 From CCAP-00091-100 to CCAP-00091-200 to combine line item.
P1.06:Single instance of0805 0.1uF eliminatedUsing 12-200
- Change C2607 and C2608 From CCAP-00098-100 to CCAP-00098-200 to combine line item.P1.06: - Change C401 100uF, 150mOhm, CCAP-00111-000 to 100uF, 60mOhm, CCAP-00034-060 to combine 100uF TANT line itemP1.064: - [BOM ONLY] Change C2611 and C2618 From 22pF CCAP-00006-200 to 27pF CCAP00021-000 for minimum in-circuit frequency ppm error, 25MHz SATA crystal Y2602.C1 22Feb07 - 16 [BOM ONLY] (DNI) CN1
D1 22Mar07 - 16 Change SATA Connector CN1 From Tyco to Molex
D01 07Mar07 - 16 Change SATA Connector CN1 From Thru-hole CCON-00067-000 to SMT CCON-00089-000
D01 07Mar07 - 16 Change SATA Connector CN1 From Thru-hole CCON-00067-000 to SMT CCON-00089-000
D1 22Mar07 - 16 Change SATA Connector CN1 From Tyco to Molex
F1 24May07 - 16 {BOM Only} ACTLED - invert BCM7401 GP_ENET_ACTIVITY output: Change U28 From non-inverting CXIC-00044-000 to inverting CXIC-00259-000; Change R72 From 100 Ohm CRES-00011-100 to 200 Ohm CRES-00160-100 to reduce "Active" LED current to 6mA.
F1 24May07 - 16 {BOM Only} LNKLED - invert BCM7401 GP_ENET_LINK output: Change U29 From non-inverting CXIC-00044-000 to inverting CXIC-00259-000; Change R71 From 100 Ohm CRES-00011-100 to 200 Ohm CRES-00160-100 to reduce "Link" LED current to 6mA.
C26050.1UF
16VCCAP-00012-100
10%X7R 0603
C26050.1UF
16VCCAP-00012-100
10%X7R 0603
R2616 (DNI)1.0K
1%CRES-00009-100
1/10W 0603
R2616 (DNI)1.0K
1%CRES-00009-100
1/10W 0603
1CT : 1
TD+
TD-
RD
+N
C4
NC
5R
D-
NC
7N
C8
12345678
1CT : 1
75 75 75
1000pF 2kV SHIELD
RJ45
LED1
75
LED2
1 2 3 4
USB 2 (TOP)
31 2 4
USB 1 (BOT)
YEL
GRN
ORG
21
12
18
1
611
RJ451
10
4
USB 1
24
17
2USB 2
2
3
7
3
5
25
8
4
1
3
20
5
23
9
7
10
1
27
8
9
262
2
Bel Fuse pin numbers within circle. USB_RJ45_INLINE symbol pin numbers above circles.
22
14
28
19
34
64
15
CN60812-1X1T-36CCON-00068-000
Ethernet
1CT : 1
TD+
TD-
RD
+N
C4
NC
5R
D-
NC
7N
C8
12345678
1CT : 1
75 75 75
1000pF 2kV SHIELD
RJ45
LED1
75
LED2
1 2 3 4
USB 2 (TOP)
31 2 4
USB 1 (BOT)
YEL
GRN
ORG
21
12
18
1
611
RJ451
10
4
USB 1
24
17
2USB 2
2
3
7
3
5
25
8
4
1
3
20
5
23
9
7
10
1
27
8
9
262
2
Bel Fuse pin numbers within circle. USB_RJ45_INLINE symbol pin numbers above circles.
22
14
28
19
34
64
15
CN60812-1X1T-36CCON-00068-000
Ethernet
V_21DM22DP23G_24
V_15DM16DP17G_18
TX+9
TXC12
TX-10
RX+11
RXC15
RX-14
LED
120
LED
119
LED
218
LED
217
MT1 25MT2 26MT3 27MT4 28SH1 21SH2 22SH3 23SH4 24
R2032.2K5%CRES-00018-100
1/10W 0603
R2032.2K5%CRES-00018-100
1/10W 0603
C2618 27PF
25VCCAP-00021-200
5%NPO 0402
C2618 27PF
25VCCAP-00021-200
5%NPO 0402
R260749.9
1%CRES-00176-100
1/10W 0603
R260749.9
1%CRES-00176-100
1/10W 0603
C4630.1UF
16VCCAP-00012-200
10%X7R 0402
C4630.1UF
16VCCAP-00012-200
10%X7R 0402
C2621 0.01UF 50V CCAP-00011-10010%X7R 0603C2621 0.01UF 50V CCAP-00011-10010%X7R 0603
L43
CIND-00010-0001.5A
HF50ACC321611-T
12060.04 OHM
L43
CIND-00010-0001.5A
HF50ACC321611-T
12060.04 OHM
R26091.0K1%CRES-00009-100
1/10W 0603
R26091.0K1%CRES-00009-100
1/10W 0603
C2619 0.01UF 50V CCAP-00011-10010%X7R 0603C2619 0.01UF 50V CCAP-00011-10010%X7R 0603
TP2607TP2607
R261710K5%CRES-00010-100
1/10W 0603
R261710K5%CRES-00010-100
1/10W 0603
C2611 27PF
25VCCAP-00021-200
5%NPO 0402
C2611 27PF
25VCCAP-00021-200
5%NPO 0402
R2623 0
50mOHMCRES-00001-2001A 0402
R2623 0
50mOHMCRES-00001-2001A 0402
L40
CIND-00010-0001.5A
HF50ACC321611-T
12060.04 OHM
L40
CIND-00010-0001.5A
HF50ACC321611-T
12060.04 OHM
1237 6 5 4
CN1
SATACCON-00089-000
(DNI)67800-5001PCB Footprint = SATA_VERT_SMT_7P
1237 6 5 4
CN1
SATACCON-00089-000
(DNI)67800-5001PCB Footprint = SATA_VERT_SMT_7P
1234567
M1
M2
R26370
50mOHMCRES-00001-1001A 0603
R26370
50mOHMCRES-00001-1001A 0603 C277
22UF6.3V
CCAP-00102-00020%X5R 1206
C27722UF
6.3VCCAP-00102-000
20%X5R 1206
R2624 0
50mOHMCRES-00001-2001A 0402
R2624 0
50mOHMCRES-00001-2001A 0402
C26030.1UF
16VCCAP-00012-100
10%X7R 0603
C26030.1UF
16VCCAP-00012-100
10%X7R 0603
Y2601(DNI)25Mhz
CXTL-00011-000+/-50PPM+/-30PPM
Y2601(DNI)25Mhz
CXTL-00011-000+/-50PPM+/-30PPM
12
C46847UF16V ALYTICCCAP-00058-000
C46847UF16V ALYTICCCAP-00058-000
C260110UF
6.3VCCAP-00138-100
10%X5R 0603
C260110UF
6.3VCCAP-00138-100
10%X5R 0603
TP2608TP2608
TP2606TP2606
C26021000PF
25VCCAP-00032-100
5%NPO 0603
C26021000PF
25VCCAP-00032-100
5%NPO 0603
C2607
25VCCAP-00098-200
5%NPO 0402
(DNI)12PFC2607
25VCCAP-00098-200
5%NPO 0402
(DNI)12PF
U43MIC2026-1BMCXIC-00117-000
U43MIC2026-1BMCXIC-00117-000
ENA1 FLGA 2
FLGB 3ENB4
OUTB 5
GND 6
IN7
OUTA 8
C46747UF16V ALYTICCCAP-00058-000
C46747UF16V ALYTICCCAP-00058-000
TP2609TP2609
L42
CIND-00010-0001.5A
HF50ACC321611-T
12060.04 OHM
L42
CIND-00010-0001.5A
HF50ACC321611-T
12060.04 OHM
TP2611TP2611
C2608
25VCCAP-00098-200
5%NPO 0402
(DNI)12PFC2608
25VCCAP-00098-200
5%NPO 0402
(DNI)12PF
C2622 0.01UF 50V CCAP-00011-10010%X7R 0603C2622 0.01UF 50V CCAP-00011-10010%X7R 0603
TP2605TP2605
C26040.1UF
16VCCAP-00012-100
10%X7R 0603
C26040.1UF
16VCCAP-00012-100
10%X7R 0603R260649.9
1%CRES-00176-100
1/10W 0603
R260649.9
1%CRES-00176-100
1/10W 0603
C401100UF16V TANT
CCAP-00034-060
10%0.060 OHM 7343
C401100UF16V TANT
CCAP-00034-060
10%0.060 OHM 7343
C260915PF
25VCCAP-00091-200
+/-.25PFNPO 0402
C260915PF
25VCCAP-00091-200
+/-.25PFNPO 0402
U29MC74VHC1GU04CXIC-00259-000
EthernetPCB Footprint = TI_DBV_SNGL_GATE_5PIN
U29MC74VHC1GU04CXIC-00259-000
EthernetPCB Footprint = TI_DBV_SNGL_GATE_5PIN
A2 Y 4
VCC
5
GND
3
NC1
R260549.9
1%CRES-00176-100
1/10W 0603
R260549.9
1%CRES-00176-100
1/10W 0603
R2022.2K5%CRES-00018-100
1/10W 0603
R2022.2K5%CRES-00018-100
1/10W 0603
C2620 0.01UF 50V CCAP-00011-10010%X7R 0603C2620 0.01UF 50V CCAP-00011-10010%X7R 0603
FB2601
CIND-00001-000200MA
MMZ2012S601A08050.3 Ohm
FB2601
CIND-00001-000200MA
MMZ2012S601A08050.3 Ohm
R712001%CRES-00160-100
1/10W 0603
R712001%CRES-00160-100
1/10W 0603
R2620
2001%CRES-00160-100
1/10W 0603
R2620
2001%CRES-00160-100
1/10W 0603
R2012.2K5%CRES-00018-100
1/10W 0603
R2012.2K5%CRES-00018-100
1/10W 0603
R260849.91%CRES-00176-100
1/10W 0603
R260849.91%CRES-00176-100
1/10W 0603
U28MC74VHC1GU04CXIC-00259-000
EthernetPCB Footprint = TI_DBV_SNGL_GATE_5PIN
U28MC74VHC1GU04CXIC-00259-000
EthernetPCB Footprint = TI_DBV_SNGL_GATE_5PIN
A2 Y 4
VCC
5
GND
3
NC1
L41
CIND-00010-0001.5A
HF50ACC321611-T
12060.04 OHM
L41
CIND-00010-0001.5A
HF50ACC321611-T
12060.04 OHM
Y260225Mhz
CXTL-00011-000+/-50PPM+/-30PPM
Y260225Mhz
CXTL-00011-000+/-50PPM+/-30PPM
12
Ethernet
USB
SATA
U100-16BCM7401Revision = C1CXIC-00248-000
CPUEthernet
USB
SATA
U100-16BCM7401Revision = C1CXIC-00248-000
CPU
USB20_DP1 AF6USB20_DN1 AE6
USB20_PWRON1 AB8USB20_PWRFLT1 AF9
USB20_DP2 AF7USB20_DN2 AE7
USB20_PWRON2 AD9USB20_PWRFLT2 AE9
SATA_TXDP1 A6SATA_TXDN1 B6
USB_XTALIAF4
USB_XTALOAF5
USB_RREFAD6
EPHY_TDN A11EPHY_TDP B11
SATA_RXDP1 B5SATA_RXDN1 A5
EPHY_VREFC10
EPHY_RDACC11
USB11_DP1 AF8USB11_DN1 AE8
USB11_PWRON1 AC9USB11_PWRFLT1 AA8
EPHY_RDN B10EPHY_RDP A10
SATA_FSTESTF9SATA_PLLTESTC7
SATA_CLK25_XTALIA7
SATA_CLK25_XTALOB7
USB_MONPLLAB6USB_MONCDRAC6
TP2602TP2602
R722001%CRES-00160-100
1/10W 0603
R722001%CRES-00160-100
1/10W 0603
TiVo Proprietary and Confidential - Do Not Distribute!
Design Verification Tests—Hardware Consumer Design
3.0 Drop/Droop Test
3.1 Fusion Drop/Droop Test Results
Test Summary
Unit under test
Tested S/N
Test date(s) 4/23/2008
Test location TiVo, Inc.
Test Engineer Dennis Del Carlo
Conclusion Pass
Fusion Drop/Droop Test Fusion TSN 652 0001-8046-6A60 Test Equipment Tektronix TDSUSBF 071-1063-00 Multimeter Fluke Model 87 MEASURE AT Fusion Output 1. Set Load 1 Switch of TDSUSBF to center off, set Load 3 Switch to center off. (Off, no load) 2. Connect Fusion USB port to J1, with 1 meter USB cable. 3. Connect Fusion USB port to J2, with 1 meter USB cable 4. Measure VBUS at J1 and J2, no load; record as No Load Voltage. 5. Switch Load 1 and Load 3 to 500mA load position. 6. Measure VBUS at J1 and J2 each with 500mA load switched on; record as Load Voltage. Lower Upper No Load Voltage 4.96 4.96 Load Voltage 500 ma 4.77 4.77 VBUS Droop at 500ma 0.190 0.190 Pass / Fail Pass Pass
TiVo Proprietary and Confidential - Do Not Distribute!
Design Verification Tests—Hardware Consumer Design
4.0 Droop Test
4.1 Bus-Powered Droop Test Results in Tek format
Test Summary
Unit under test
Tested S/N
Test date(s) 4/22/2008
Test location TiVo, Inc.
Test Engineer
Conclusion Pass
file:///C|/TekApplications/TDSUSB2/report/TSN%20652-0001-8046-6A60-droop-tek.htm
Bus-Powered Droop Test Results in Tek format
Device ID: TSN 652-0001-8046-6A60
Device Description: High Speed , DVR MODEL TCD652160.
Date: Wed Apr 23 14:19:14 PDT 2008
Droop Test Result: Pass
Measurement Name
Measured Droop Voltage
USB Limits Status
Droop Test 28.000mV <330mV Pass Droop value measured at: Port 1 of HUT
TDSUSB2 software version: 1.9.1
file:///C|/TekApplications/TDSUSB2/report/TSN%20652-0001-8046-6A60-droop-tek.htm4/23/2008 2:22:46 PM
TiVo Proprietary and Confidential - Do Not Distribute!
Design Verification Tests—Hardware Consumer Design
5.0 Inrush Test
5.1 Inrush Test Results in Tek format
Test Summary
Unit under test
Tested S/N
Test date(s) 1/15/2008
Test location TiVo, Inc.
Test Engineer
Conclusion Pass
Inrush Test Results in Tek format
Device ID: fsfe_001
Device Description: Full Speed , Dummy Device.
Date:Tue Jan 15 14:16:56 PST 2008
Inrush Test Result: Pass
Measurement
NameCharge
Capacitance USB
Limits
Waiver
LimitsStatus
Inrush Test4.440960u
C906.3183n F
<49.0000
0u C
<196.000
0u CPass
TDSUSB2 software version: 1.9.1
TiVo Proprietary and Confidential - Do Not Distribute!
Design Verification Tests—Hardware Consumer Design
6.0 Full Speed Signal Quality Test
6.1 Signal Quality Test Results in Tek format
Test Summary
Unit under test TCD652160
Tested S/N
Test date(s) 12/20/2007
Test location TiVo, Inc.
Test Engineer Dennis Del Carlo
Conclusion Pass
Signal Quality Test Results in Tek format
Device ID: fsfe_001
Device Description: Full Speed, Far End Device, Up Stream Testing, Tier 6, Dummy Device.
Date: Thu Dec 20 15:14:26 PST 2007
Overall Result: Pass*
Waveform Plot
Eye Diagram
Results based on USB-IF / Waiver Limits :
Measurement Name Minimum Maximum Mean pk-pk Standard DeviationRMS
Population Status
Measurement Name Minimum Maximum Mean pk-pk Standard Deviation Population Status
Eye Diagram Test - - - - - - - Pass
Signal Rate 11.91556Mbps 12.08993Mbps 12.00219Mbps 0.0000bps 55.78330kbps 12.00285Mbps 31 Pass
Crossover Voltage 1.470407 V 1.606011 V 1.544779 V 135.6043mV 44.19866mV 1.545376 V 18 Pass
EOP Width - - 166.0977ns - - - 1 Pass
Consecutive Jitter -488.8744ps 476.7385ps 0.0000s 965.6129ps 278.4314ps 270.1181ps 17 Pass
Paired JK Jitter -139.9193ps 86.80902ps -57.23172ps 226.7283ps 76.24811ps 91.44683ps 8 Pass
Paired KJ Jitter -145.6585ps 19.11635ps -51.57139ps 164.7749ps 53.62642ps 71.58613ps 7 Pass
Additional Information :
Rise Time: Min: 7.2213ns Max: 8.0240ns Mean: 7.6676ns Std: 273.02ps RMS: 7.6718ns Population: 8
Fall Time: Min: 7.3805ns Max: 7.9602ns Mean: 7.6497ns Std: 158.11ps RMS: 7.6512ns Population: 9
* The Overall Result for this test is Pass, because individual status of the measurements is Pass and it is performed on Tier 6 (as per USB-IF).
TDSUSB2 software version: 1.9.1
TiVo Proprietary and Confidential - Do Not Distribute!
Design Verification Tests—Hardware Consumer Design
7.0 High Speed Signal Quality Test
7.1 Signal Quality Test Results in Tek format
Test Summary
Unit under test
Tested S/N
Test date(s) 12/20/2007
Test location TiVo, Inc.
Test Engineer
Conclusion Pass
Signal Quality Test Results in Tek format
Device ID: fsfe_001
Device Description: High Speed, Near End Device, Up Stream Testing, Tier 1, Dummy Device.
Date: Thu Dec 20 15:00:29 PST 2007
Overall Result: Pass*
Waveform Plot
Eye Diagram
Results based on USB-IF / Waiver Limits :
Measurement Name Minimum Maximum Mean pk-pk Standard DeviationRMS
Population Status
Measurement Name Minimum Maximum Mean pk-pk Standard Deviation Population Status
Monotonic Property - - - - - - 0 Pass
Eye Diagram Test - - - - - - - Pass
Signal Rate 459.4871Mbps 499.6538Mbps 479.9329Mbps 0.0000bps 9.160196Mbps 480.1691Mbps 513 Pass
EOP Width - - 16.56090ns - - - 1 Pass
EOP Width (Bits) - - 7.948123 - - - 1 Pass
Rise Time 659.9592ps 803.2581ps 726.3759ps 143.2989ps 42.27301ps 727.5935ps 107 Pass
Fall Time 691.0569ps 826.2003ps 773.4787ps 135.1434ps 27.04750ps 773.9470ps 107 Pass
Monotonicity test is performed on the test limits of 15.0% and 85.0%.
Additional Information :
Consecutive Jitter range : -129.0ps to 148.7ps RMS Jitter 57.44ps
KJ Paired Jitter range : -64.00ps to 54.17ps RMS Jitter 24.27ps
JK Paired Jitter range : -53.36ps to 55.96ps RMS Jitter 24.56ps
*The Overall Result for this test is Pass, because one or more individual status of the measurements is Pass. For this test, the recommended configuration
for USB2 testing (as per USB-IF) is on Tier 1.
TDSUSB2 software version: 1.9.1
TiVo Proprietary and Confidential - Do Not Distribute!
Design Verification Tests—Hardware Consumer Design
8.0 Low Speed Signal Quality Test
8.1 Signal Quality Test Results in Tek format
Test Summary
Unit under test
Tested S/N
Test date(s) 12/20/2007
Test location TiVo, Inc.
Test Engineer
Conclusion Pass
Signal Quality Test Results in Tek format
Device ID: fsfe_001
Device Description: Low Speed, Near End Device, Up Stream Testing, Tier 6, Dummy Device.
Date: Thu Dec 20 15:23:12 PST 2007
Overall Result: Pass*
Waveform Plot
Eye Diagram
Results based on USB-IF / Waiver Limits :
Measurement Name Minimum Maximum Mean pk-pk Standard DeviationRMS
Population Status
Measurement Name Minimum Maximum Mean pk-pk Standard Deviation Population Status
Eye Diagram Test - - - - - - - Pass
Signal Rate 1.492834Mbps 1.508246Mbps 1.500037Mbps 0.0000bps 4.126709kbps 1.499968Mbps 30 Pass
Crossover Voltage 1.667506 V 1.839996 V 1.759122 V 172.4896mV 50.07425mV 1.759804 V 23 Pass
EOP Width - - 1.331282us - - - 1 Pass
Consecutive Jitter -2.160031ns 2.062411ns 0.0000s 4.222442ns 1.266140ns 1.237029ns 22 Pass
Paired JK Jitter -1.811237ns 3.242755ns -89.42197ps 5.053992ns 1.580994ns 1.502526ns 10 Pass
Paired KJ Jitter -2.852340ns 1.033740ns -87.18670ps 3.886080ns 1.074808ns 1.023373ns 10 Pass
Rise Time 98.18807ns 105.9743ns 102.3523ns 7.786188ns 2.327476ns 102.3764ns 11 Pass
Fall Time 98.40769ns 106.4920ns 103.5255ns 8.084334ns 2.435308ns 103.5515ns 11 Pass
* The Overall Result for this test is Pass, because individual status of the measurements is Pass and it is performed on Tier 6 (as per USB-IF).
TDSUSB2 software version: 1.9.1
TiVo Proprietary and Confidential - Do Not Distribute!
Design Verification Tests—Hardware Consumer Design
9.0 High Speed Chirp Test
9.1 High Speed Chirp-Test Results in Tek format
Test Summary
Unit under test
Tested S/N
Test date(s) 12/20/2007
Test location TiVo, Inc.
Test Engineer
Conclusion Pass
Chirp-Test Results in Tek format
Device ID: fsfe_001
Device Description: High Speed , Host EL_33,EL_34 Testing , Dummy Device.
Date:Thu Dec 20 17:42:48 PST 2007
Chirp Test Result: Pass
Measurement
NameMeasurement Value USB Limits Status
Chirp Response Time 92.40000uS Time =100.0000uS Pass
Chirp-K&J Duration49.20008uS &
50.80270uS
40.00000uS to
60.00000uS Pass
TDSUSB2 software version: 1.9.1