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USN 06EC56
Fifth Semester B.E. Degree Examination, Dec.2013 /Jan.20l4Fundamentals of CMOS VLSI Design
Time: 3 hrs. Max. Marks:100Notez Answer FIVEfull questions, selecting
at least TWO questions from each part.
PART _ AI a. Explain the working of enhancement mode transistor with neat nMOSFET structures at
different conditions of applied voltages. Also draw the o/p characterjstics and identify thedifferent regions of operation. (08 Marks)
b. How many fiask layers are required in a basic nMOS process? Explain the function of eachof these maskS. - (07 Marks)
c. What is a .noise mar.eil?. Obtain the values of V1s, Vru, Vol and Von from transfer
characteristics of a typical inverter. (05 Marks)
2 a. Explain },-based design rulcs for contact cuts and,iu, *itt neat diagrams. (12 Marks)b. Draw the stick diagram for the CMOS implementation of the Boolean expression
Y=AB+C. (08Marks)
3 a- Explain the working of dynamic CN{OS logic with necessary diagram and waveforms. Whatare the problems encountered in this logic? Explain how CMOS domino logic eliminates theabove drawbacks with necessary diagrams. (10 Marks)
b. Discuss the working, merits and demerits of the following logic structures with two inputNAND gate realization as an example: i,) Complementary CMOS logic; ii) Pseudo NMOSlogic. (10 Marks)
4 a. Two nMOS inverters are cascaded to drive capacitive load Cr,: 168C, as in Fig.Q.4(a).Calculate the pair delay (V;n to Voul) in terms of t for the inverter geometry indicated infigure. WhaJ are the ratios of each inverter? If strays and wirings are allowed for, it would bereasonable' to increase the capacitance to ground across the o/p of each inverter by 4nCr.What is the pair delay allowing for strays? Assume t : 0.1nsec to evaluate thir pai*elfil;ur,
*- lvo4I Lr-fif*
Inverter 1
Lpu : 161"
Wru:21"Lpa:2XWpo:21"
Inverter 2Lrr:2XWor:2Lpa:2)"Wpa: 81"
Fig.Q.a(a)What is the problem encountered in driving a large capacitive load? How this proilffiTinbe overcome using cascaded inverters? Obtain the expression for total delay for N stages ofnMOS and CMOS inverters in terms of width factor f and delay r. What is the problemencountered in cascaded inverters? Explain how it is overcome.
trol/b"Y
I of2
(12 Marks)
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06EC56
For More Question Papers Visit - www.pediawikiblog.com
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