Newsfile

BiCMOS gate array eliminates level converters

Manufactured using a 1.3 lam BiCMOS process, the latest ASIC device from Hitachi is the HG21T20 gate array. With 2000 gates, it supports TTL, ECL and pseudo-ECL interfaces, making it suitable for applications in high speed computers, image processing systems and high performance test equipment.

It allows the user to mix TTL and ECL interface levels and to select totem pole, three state or open- collector TTL outputs. This removes the need for external level converters, simplifying the interface to external ECL circuitry and eliminating the delays associated with external level converters.

Gate delay is only 450 ps, which allows toggle frequencies of above 150 MHz. Power dissipation is 0.24 mW per gate at 10 MHz and there is a 24 mA drive capability on the output buffers. (Hitachi Europe Ltd, Electronic Components Division (Northern Europe), Whitebrook Park, Lower Cookham Road, Maidenhead, Berkshire SL6 8YA, UK. Tel: 0628 585000)

Evaluation platform for SPARC embedded processor

An evaluation board has been introduced by LSI Logic for the L64901 32 bit SPARC embedded processor and the companion L64951 integrated system controller. The board runs at 20 MHz and provides 12 MIPS performance, enabling users to prototype a SPARC embedded system within weeks.

The SPARC Xpress serves as a prototype system and should be useful in hardware and software development. The board is particularly suitable for developing laser printers, disc controllers, scanners, ISDN, FDDI, image processing, VME and I/O processing applications.

In addition to the L64901 and L64951, it contains from 1 to 8 Mbyte of DRAM, up to 2 Mbyte of EPROM, 32 kbyte of cache memory for

instruction and data, a high speed 32 bit 96 pin daughter connector and two serial ports. (LSI Logic Europe PIc, Grenville Place, The Rin& Bracknell, Berkshire RG12 1BP, UK. Tel: 0344 426544)

64 Mbit DRAM manufacturing technology

Using the company's stacked capacitor cell design and a newly developed phase shift lithographic process, the manufacturing tech- nology for a 64 Mbit RAM has been established by Fujitsu. An improve- ment on the company's original 64 Mbit DRAM, it could lead to rapid development of quantity manufacture within the next few years.

The phase method employs i-line lithography, and allows finer patterns to be formed by using the inter- ference effects generated between phase-non-inversed and phase- inversed waves. It can be used with existing technology.

The layout patterns are able to use all angles, rather than just the 45 ° and 90 ° used conventionally, enabling a smaller cell to be achieved using the same design rules.

The i-line phase shift lithography is used in conjunction with the company's fin structure, three- dimensional, stacked cell design. The fin structure cells do not experience deterioration in the breakdown voltage of their insulator films, despite the fact that both films and cell plates are formed in ultra small gaps.

The cells are designed with double fins, and provide a cell capacitance of more than 30 fF for a 1.8 lam 2 cell area. It also has very low coupling capacitance between bit lines because the cell plate acts as a shield, eliminating parasitic coupling. (Fujitsu Microelectronics Ltd, Hargrave House, Belmont Road, Maidenhead, Berkshire SL6 6NE, UK. Tel: 0628 761 O)

Functionally compatible 256k flash memories

Functionally compatible electrical specifications for 256k single-voltage

flash memories have been announced by Texas Instruments and Atmel. Systems designers will therefore have two manufacturing sources for single 5 V flash memories. The specifications cover the 28 pin TMS29F26 and 32 pin TMS29F259 flash EEPROMs from TI, and the corresponding AT29C256 and AT29C257 from Atmel.

The devices use a single 5 V power supply for program, erasure and read operations, in contrast to 12 V flash memories which require dual power supplies. They also have an internally timed programming algorithm that performs a full chip erase and write operation, and require only a fifth of the power of 12 V devices.

Flash memories are being used in a growing number of applications such as automotive systems, instrumenta- tion, embedded controllers, military equipment and remote installations requiring in-system program update. According to Dataquest, the worldwide flash EEPROM market expanded from $5 million in 1988 to over $30 million in 1990, with a figure of $1.1 billion forecast for 1995. (Texas Instruments, Manton Lane, Bedford MK4"I 7PA, UK. Tel: 0234 223252)

2 Mbit surface mount SRAM

Organized as 256k x 8, the 2 Mbit surface mount SRAM from Micro Call can replace existing 128k x 8 monolithic devices without modifi- cation to the PCB. The EDI 8F8257 is based on two 128k x 8 static RAMs in TSOP packages, mounted on a multi- layered epoxy laminate substrate. It is available in three power consump- tion variants, including one with a data retention function at 2 V for battery-backed applications. Speeds are available from 85 to 150 ns.

A decoder buried in the substrate interprets the two higher order address lines to select one of the SRAMs, ensuring compatibility with future monolithic devices.

All inputs and outputs are TTL compatible and operate from a single 5 V supply. (Micro Call Ltd, 17 Thame Park Road, Thame, Oxon OX9 3XD, UK. Tel: 0844 261939)

122 Microprocessors and Microsystems