Full-swing BiCMOS Schmitt trigger

C.-S. Wang S .-Y. Yu a n S.-Y. KUO

Indexing terms: Schmitt trigger, BiCMOS circuit, Full swing BiCMOS design, Low power/low voltage

Abstract: A novel full swing BiCMOS Schmitt trigger, consisting of a BiCMOS inverter and a CMOS latch circuit, is proposed. This new circuit outperforms a conventional CMOS Schmitt trigger significantly. Even when the supply voltage is lowered down to l.SV, the new Schmitt trigger still maintains good operatjional quality. Based on the PSPICE simulations, the proposed BiCMOS circuit has less transmission delay and delay power product, as well as no static current under various supply voltages and output loads. The power consumption of the BiClMOS Schmitt trigger is actually slightly less than that of the CMOS counterpart. The circuit is also a full swing design. With these characteristics, this circuit is very suitable for high-speed and low- power applications.

1 Introduction

The Schmitt trigger is a circuit used extensively in both the analog and the digital systems. Its main application is to reduce the circuit sensitivity to noises and disturbances. Conventional Schmitt triggers (Fig. 1) are based on the positive feedback theory [l]. Another type of Schmitt trigger is based on the different threshold voltages of MOS transistors in a CMOS Schmitt trigger [2, 31, as shown in Fig. 2.

The detail design of Fig. 1 is presented in [4]. The switching point is dependent on the ratioed operation of NMOS and PMOS transistors. However, this circuit will exhibit racing phenomena after the transition starts. To improve this situation, the reshaping CMOS Schmitt trigger was proposed, as shown in Fig. 2. Based on the concept described in [SI, the circuit can function based on ratioless CMOS technology and obtains higher speed than the conventional one in Fig. 1. In this paper, we propose a new BiCMOS Schmitt trigger. It is a full swing design, designed for high speed and low power applications, and will still work even when the voltage supply drops down to 3.3V or even 1.5V. 0 IEE, 1997 IEE Proceedings online no. 19971 142 Paper received 10th September 1996 The authors are with the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, Republic of China

M6

.i-

t, Fig. 1 Conventional CMOS Schmitt trigger

I

-

Fig. 2

2 Circuit description

Reshaping CMOS Schmitt trigger

I; -

The proposed circuit and its operation are depicted in Figs. 3 and 4, respectively. It consists of a BiCMOS inverter and two CMOS inverters (as a latch circuit). This circuit can be divided into two sub-circuits, one of them is the BiCMOS inverter A, and the other is the latch circuit B. The performance of sub-circuit A was detailed in [6-91. The output voltage range is limited by the voltage drop across the base emitter junction of the BJT driver [lo, 111. The sub-circuit B will not only pull

IEE Proc.-Circuit.9 Devicar Syst., Vol. 144, No. 5, October 1997 303

the output to full swing but also serve as a latch circuit. The operation of the circuit is described in the follow- ing. First, we set the V,, and the V , voltage levels, where V,, must be less than V,. When the input volt- age goes to OV, M1 and M2 are on, M2 and M3 are off, Q2 is off, Q1 is on and the output node X is pulled to V,,. When the input voltage is raised in between V,, and V,, M1, M3 and M4 are off, M2 is on and both Q1 and Q2 are turned off. The output node remains at VDD, since the latch output node Z has already dropped to QV. When V,, goes up above V,, M1 and M4 are off, M2 and M3 are on and Q1 is off, Q2 is on, and the output node X is pulled down to OV. Similarly, when Vi, is reduced from V,, to a voltage no less than VTl, both Q1 and 4 2 are turned off and the output node voltage is still OV. The transition occurs when V,, is lower than V,, and higher than V,. The threshold voltage V,, can be determined by VIL and VIH [5] (assuming V, = - V,, = V,,) as follows:

V I L = ( V D D - K) - ( V D D - 2K) (KR/ (KR +

vIH = V, + (vDD - 2 ~ ) / ( 2 ~ , + 1)l”

(1)

( 2 )

VIL + VIH 2 VT1 E ( 3 )

I----------- I I

I I_

Fig.3

1 -6 r

1.

1 .

1 > 5 0.

>O

0.

0

0 .

- 0 . 2 1 I I I I 0 0.2 0 . L 0.6 0.8 1.0 1 .2 1.1, 1.6

Yrl, ” Fig. 4 Operation ofnew BiCMOS Schmitt trigger

where KR = K,/K, and K, = $2 Cox W,IL,. V,, becomes smaller if the ratio K2/Kl is larger. Similarly,

VT2 V B E 2 + & n 3 $- (103/K3)l/’ (4) 304

The threshold voltage V , is determined by the geome- try of M3. V, will become smaller if W31L3 is larger, assuming the body effect is neglected. To reduce the delay time of the triggering circuit, we increase the widths of both transistors M1 and M3. However, this will also increase the power consumption. For example, assume that W, = 2 . 8 p , W3 = 3.5pm, L = 0 . 3 5 p , V D D = 1.5V and f = 10MHz. From the PSPICE simu- lation of the proposed circuit, we have V,, = 0.329V, V , = 1.154V, total current IDS = 2.645pA, total power P, = 3.91pW, and transmission delay Td = 1.41ns (nanoseconds). By reducing only W, to 1 . 4 ~ we got

1.78pW, and Td = 2.1111s. Similarly, if only W, is reduced to 1.75pn, V,, will become 0.329V, V , = 1.214V, I,, = 2.599pA, P, = 3.9pW, and Td = 1.6111s. Based on the above observation, the total power con- sumption is mainly dependent on W,. In this circuit, the pull-up time is proportional to the ratio in eqn. 1. The delay time of the circuit is reduced when W, increases [SI. If M l and M2 are both in saturation mode,

V T , = 0.219V, V n = 1.155V, I,, = l . l 8 8 f i , P, 1

l 2 (5) I D 1 = Kl r 1 + d m

K2/Kl(VDD - 2K)

where we assume V,, = Vtp = V, for simplification.

1 . 6 1 I

7 . L

1 . 2

1 .o 0 . 8

o 0.6

P 0 . L

> a, 0)

Y

0 . 2

0

- 0 . 2 1 ~ x I O - ~ 1 . 5 ~ 1 0 - ~ 2xIO1 2 . 5 ~ 1 0 ~ ~

t ime, s Fig. 5 v,, V,,, and V,,, versus time

~ V,, VB, Vout

_ _ _ ~ .... .

We use the subthreshold current [12] to drive the lower part of the subcircuit A to function when Vin goes upwards. The circuit works under large enough V,, (for example, 5V), however, because of our design techniques, the circuit can function normally even under the condition that V,, < Vrn3 + VBE2 owing to the minimum subthreshold current being large enough to drive the BJT Q2 to sink the current at the node X. The operation under such low V,, is explained in the following. Fig. 5 shows the Vi,, VBn, and Vout curves versus time. According to this Figure, we can derive the Vgs3 (V,,, = Vi, ~ V,,,) versus time which is shown in Fig. 6. When Vi, crosses V,, 4 2 must begin to sink current to ground. At this time, the Vgs3 is still lower than the threshold voltage Vln3. In order to get a larger subthreshold current, we connect the drain of M3 to V,,. When we examine the simulation results even closer to this condition, which is not shown here, the subthreshold current is so large that Q2 which sinks the charge at node X will reach Q2’s saturation region very quickly, which means that the subthreshold current is

IEE Pvoc -Circuits Devices Syst., Vol. 144, No. 5, October 1997

always large enough to drive the lower part of the subcircuit A to function correctly. The subthreshold current is so effective that we can even lower the VDD to 1 . l V and the proposed circuit can still work properly. The upper part of the subcircuit A is a normal inverter, and thus this part functions normally and does not make use of the subthreshold current.

0.8

I I

time, s ~ X I O - ~ 1 . 5 ~ 1 0 - ~ 2x10-7 2 . 5 ~ 1 0 - ~

Fig. 6 rg,, versus time __

4:; . . . . . . . . . .

The nature of a Schmitt trigger will make the subcir- cuit B be turned on at transition time, and the adapting of subcircuit A will make Q1 and Q2 also be turned on only at transition time. Thus no static power will be consumed at a steady state.

3 Comparisons between BiCMOS and CMOS Schmitt triggers

We use PSPICE to simulate and compare the proposed circuit with both the conventional CMOS Schmitt trig- ger [2] and the reshaping CMOS Schmitt trigger [ 3 ] . The comparisons are made by using the methods sug- gested in [ 131, including the transmission delay, delay- power product, etc., with additional hysteresis voltage versus each output load. However, frequencies and supply voltages were not specified for the circuit in [13] since it is an inverter.

Table 1: The PSPICE device parameters of the BiCMOS technology

CMOS Bipolar

Fm nm pF m A f F f F f F

0.5 0.895 -0.972 25 182.9 3.3 100 ‘1.5 40 40 50

0.35 0.895 -0.972 25 182.9 1.5 100 1.5 40 40 50

For fair comparison at different supply voltages (and geometries), all the circuits have the same device parameters, as shown in Table 1. The MOS device geometries (at different supply voltages according to Table 1) are shown in Table 2. Transistors of the same sizes are used in the latch of Fig. 1 and the subcircuit B of Fig. 3.

3. I Transmission delay Fig. 7a and b show the dependence of transmission delay on load capacitance with V,, at 3.3V ( L = 0 . 5 ~ ) and 1.5V ( L = 0 . 3 5 ~ ) , respectively. The delay times of these circuits are measured as the average of the rise and fall times from V,, = VDD/2 to V, = V D D / 2

IEE Proc -Circuits Devices Syst , Vol 144, No 5, October 1997

Table 2: The geometries of the circuits

WIL Conventional [21 Reshaping I31 Proposed

wm 0.35 0.5 0.35 0.5 0.35 0.5

M I 2.810.35 410.5 0.35/0.35 410.5 2.810.35 0.510.5

M2 2.810.35 1.510.5 0.512 0.510.5 0.710.35 110.5

M3 0.3510.35 0.510.5 0.3510.35 0.510.5 3.510.35 311.0

M 4

M 5

M 6

M7

M8

M9

M I 0

3.510.35 510.5 3.510.35 410.5 0.710.35 0.7510.5

3.510.35 510.5 2.810.35 410.5 1.410.35 210.5

2.810.35 410.5 1.410.35 210.5 0.710.35 110.5

1.410.35 210.5 1.410.35 210.5 1.410.35 210.5

0.710.35 110.5 0.710.35 110.5 0.710.35 110.5

1.410.35 210.5 1.410.35 210.5 - -

0.710.35 110.5 0.710.35 110.5 - -

for square-waveform input at 1 MHz. Increasing load capacitance will increase the transmission delay. As shown in the circuit simulation results, the proposed circuit is more than twice as fast as the CMOS triggers with CL = 1.5pF in Fig. 70, and 0.5pF in Fig. 7b. For a larger output load, the BiCMOS Schmitt trigger has a higher performance than the CMOS Schmitt trigger, as expected. Fig. 7b shows that the conventional CMOS Schmitt trigger cannot function at a proper speed when the CL is larger than 1.5pF and the reshaping CMOS cannot work when the CL is larger than 4pF. The proposed circuit maintains a near con- stant transition delay (less than 4.2% compared with the reshaping CMOS configuration and CL = 4pF).

LO 1 P

r

CL, PF b

Fig. 7 -0- conventional CMOS ...O... proposed BiCMOS a L = 0.5pn1, VDD = 3.3V

Transmission delay v e m s load capacitance ~ ~ A - - reshaping CMOS

b L = 0 . 3 5 ~ ~ VDD = 1.5V

305

c 3 1

b- __ +- - 4 ---U- --A- ----A- --@

-.. __. _ _ ..- .. _ _ _ _. _ _ - r7 -,--- T - # - - P > ( 1

01 1 I O 100 1000 10000 100000 frequency, kHz

a

n C

________._--.Q _ _ _ _ _ _ -----.a ---.------_ 0 ----------a------ ---- -2 2

0 I 1 ' ' ' ' 1 ' ' I " 1

0 .I 1 10 100 1000 10000 frequency, kHz

b

- - A - - reshaping CMOS

b L = 0 . 3 5 ~ ~ V,, = 1.SV

Fig. 8 -0- conventional CMOS 13.. proposed BiCMOS

a L = 0 . 5 ~ ~ V,, = 3.3V

Transmission deluy versus frequency

100 1:

0 1 1 2 3 i, 5

a

0 .1 10 1 yQ, v

b

- - A - - reshaping CMOS

b L = 0.35wm; CL = 0.5pF

Fig. 9 -0- coiiventional CMOS . . 0 .. proposed BiCMOS a L = 0.5pnn; CL = 0.5pF

Trunsmission delay versus supply voltage

Fig. 8 shows the transmission delay versus the fre- quency with CL = 0.5pF. The proposed circuit achieves the highest operation and speed among all the three types of circuit, at all Gequencies.

We also compared the performance when the supply voltage is reduced. The proposed circuit in Fig. 9a ( L = 0 . 5 ~ ) has almost the same speed as the reshaping CMOS circuit, and both circuits are much better than the conventional CMOS circuit. However, when the supply voltage goes above 1.7V, the transition delays of both CMOS designs are much larger than the delay in the proposed circuit. In Fig. 9b (L = 0.35pn), the proposed circuit significantly outperforms both the CMOS counterparts.

10 n -$--A

---A---&---*---*--- -

frequency, kHz b

- - A - - reshaping CMOS Fig. 10 -0- conventional CMOS ...O... proposed BiCMOS a L = O . S w ; f = 1MHz; V,, = 3.3V; CL = 0.5pF b L = 0 . 3 S w ; f = 1MHz, VDD = 1.5V; CL = 0.SpF

Delay-power product versus fuequency

3.2 Dela y-power product The Schmitt trigger has a hysteresis region. The push- pull transistors do not operate at the same time. There- fore changing the frequency and load capacitance can hardly affect the power consumption. However, power consumption is still affected by both the delay time and the MOS sizing, as discussed previously. The compari- son of power only is not fair without considering the effect on speed (even though, with the same parameters our circuit still has slightly less power consumption than the other two, owing to the nature of the Schmitt trigger and the proposed design technique). It is better to use the delay-power product for comparison. The delay-power products versus frequency, load capaci- tance and supply voltage are shown in Figs. 10-12. These Figures show that the proposed circuit achieves the best delay-power product under various conditions (frequency, load capacitance, and supply voltage) [13].

IEE Puoc.-Ciucuits Devices Syst., Vol. 144, No. 5, October 1997 306

1000

; 0 7 x 100

L Q)

5 ? I - Q) V

---0

0 . 1 ~

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 L.0 L.5

b CL, PF

Fig. 1 1 -0- conventional CMOS

Delay-power product versus load capacitance - - A - ~ reshanine CMOS

I -

,. O . . proposed BiCMOS a L = 0 . 5 p ; V,, = 3.3V b L = 0 . 3 5 ~ ; VDD = 1.5V

0.001 t I

1 2 3 L 5

a "DO ,'

0.01 I 1 2 3 L 5

'DD, ' b

Fig. 12 -0- conventional CMOS D. proposed BiCMOS a L = 0.5pm; V,, = 3.3V; CL = 0.5pF; f= lMHz b L = 0 . 3 5 ~ ; V,, = 1.5V: CL = 0.5pF; f= lMHz

Delay-powev product versus supply voltage - - A - - reshaping CMOS

3.3 Hysteresis voltage The hysteresis voltage V, is measured with V, = V, - VTl under a sinusoidal input waveform o f f = 1MHz. Fig. 13 shows the relationship between the hysteresis voltage and the load capacitance. As the load capaci- tance is increased, the V, of each of the three circuits including the proposed circuits is also increased (and hence can not maintain the same transition points). However, the proposed circuit has the smallest increase in V, when the load capacitance increases and hence it is the most stable circuit under different load capaci- tances (no more than 0.22V variation from OpF to 5PF).

0 . 8 l I f I 0 1 2 3 4 5

CL, PF a

0 1 2 3 4 CL, PF

b Fig. 13 -0- conventional CMOS 0 . proposed BiCMOS

U L = 0 . 5 ~ ; VDD = 3.3V

Hysteresis voltage versus load capacitance - - A - - reshaping CMOS

6 L = 0 . 3 5 ~ ; VDo = 1.5V

a

0. 4 1.5 2 0 2.5 3.0 3.5 4.0 4.5 5.0

'DO, " Fig. 14 L = 0 . 5 ~ ; CL = 0.5pF:f= IMHz 0 v72

Input threshold V,, and VT2 versuspower supply voltages

vTI

IEE Proc.-Circuits Devices Syst.. Vol. 144, No. 5, October 1997 307

0 0

1 . 8 -

I .6

a- GI 1 .I, 0 = 1 . 2 -

VI 1 . 0 - r

0 >

0

. - 0) 5 0 . 0 - F

0.6-

0 . 4 -

0 . 2

0 5 Acknowledgment

0 0 This research was supported by the National Science 0 -

- Council, Taiwan, R.O.C., under Grant NSC 84-2213- E002-035.

6 References a a a A 1 SMITH, M.J.S.: ‘On the circuit analysis of the Schinitt trigger’,

IEEE J. Solid-State Circuits, 1988, 23, (l), pp. 292-294 2 HAZNEDER, H.: ‘Digital microelectronics’ (Benjamin Cum-

ming, 1991) 3 KIM, D., KIH, J., and KIM, W.: ‘A new waveform-reshaping

circuit: an alternative approach to Schmitt trigger’, IEEE J. Solid-

a

a

1 1 I I I I I I / I ‘ 1 , 1 ’ 0 ’ 1

308 IEE Proc.-Circuits Devices Syst , Vol. 144, No. 5, October 1557